Ball grid array memory for memory subsystems

Abstract

This application relates to ball grid array storage for memory subsystems. An apparatus includes a memory component having a plurality of ball grid array (BGA) components, where each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent to the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to ball grid array storage for memory subsystems. BACKGROUND

[0002] A memory subsystem can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at and retrieve data from the memory devices. SUMMARY

[0003] In one aspect, the present application provides an apparatus comprising: a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes: a plurality of memory blocks; and a BGA component controller and firmware adjacent to the plurality of memory blocks to manage the plurality of memory blocks; and a processing device included in the memory component to perform memory operations on the BGA components.

[0004] In another aspect, the present application provides a method comprising: performing, by a controller included in a memory component of a memory device, a memory operation on data stored in a plurality of ball grid array (BGA) components of the memory component, wherein each respective one of the BGA components includes: a plurality of memory blocks to store the data; and a BGA component controller and firmware adjacent to the plurality of memory blocks to manage the memory operation performed on the data stored in the plurality of memory blocks; communicating a result of the memory operation performed on the data from the controller included in the memory component to an additional controller operatively coupled with the memory component; and communicating the result of the memory operation performed on the data from the additional controller to a host.

[0005] In yet another aspect, the present application provides an apparatus comprising: a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes: a plurality of NAND memory blocks; and a BGA component controller and firmware adjacent to the plurality of memory blocks to manage the plurality of NAND memory blocks; a processing device included in the memory component to perform memory operations on the BGA components; a controller operatively coupled with the memory component to manage data communicated between a host and the plurality of BGA components; and an interface included in the memory component, the interface comprising a plurality of input / output (I / O) channels to couple the BGA components to the processing device. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will become more fully understood from the detailed description and the accompanying drawings, given below, as well as the various embodiments of the disclosure. The drawings, however, should not be viewed as limiting the disclosure to particular embodiments. Rather, they are for explanation and understanding only.

[0007] Figure 1 An example computing environment including a memory sub-system according to some embodiments of the disclosure is described.

[0008] Figure 2 is a block diagram of an example ball grid array storage for a memory sub-system according to some embodiments of the disclosure.

[0009] Figure 3 is another block diagram of an example ball grid array storage for a memory sub-system according to some embodiments of the disclosure.

[0010] Figure 4 is a flow diagram of an example method for ball grid array storage for a memory sub-system according to some embodiments of the disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0012] Aspects of the disclosure relate to ball grid array storage for memory sub-systems, and in particular to memory sub-systems including multiple ball grid array (BGA) components. The memory sub-systems can be storage devices, memory modules, or a mix of storage devices and memory modules. Examples of storage devices and memory modules are described below in connection with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0013] A memory sub-system can include a memory device that stores a large amount of data, for example, more than one hundred (100) terabytes (TB) of data. Some memory sub-systems can have a high throughput, for example, fifty (50) to 100 gigabytes per second (GB / s). However, a memory sub-system that can store a large amount of data can not have a high bandwidth. As used herein, the term "bandwidth" can refer to the maximum amount of data that can be transferred in a certain amount of time. For example, a flash memory device can be a high storage capacity flash memory device that can store a large amount of data but does not necessarily have a bandwidth that scales with capacity.

[0014] Due to the interfaces of the memory devices and the paths through which data travels, high storage capacity memory devices can not have high bandwidth. As used herein, the term "interface" can refer to a shared boundary across which two or more separate components of a computer system exchange information. Peripheral Component Interconnect Express (PCIe) is an interface standard for connecting components of a computer system. The version (e.g., generation) of the interface and the amount of input / output (I / O) lanes connected to the interface can determine the bandwidth of a memory device. As used herein, the term "I / O lane" can refer to a wire connected to one or more interfaces to transfer data between the one or more interfaces.

[0015] The paths through which data travels can affect the bandwidth of a memory sub-system. For example, data can travel through different memory components and interfaces within a memory sub-system. Traveling through different components and interfaces can decrease the speed of data transfer because data can travel through memory components at a lower rate than it travels through interfaces. Further, different interfaces through which data can travel can have different bandwidths. Traveling through different memory components and interfaces can decrease the net bandwidth of a memory sub-system. As used herein, "net bandwidth" can refer to the amount of data transferred in a certain time when data travels from a source memory device to a destination memory device.

[0016] Further, the storage capacity of a memory device can increase at a faster rate than the bandwidth of the interfaces coupled to the memory device. This can result in a certain amount of storage in a high capacity memory being underutilized because data cannot be accessed fast enough to utilize the full storage capacity of the memory device. Bandwidth limitations can result in using memory devices with smaller capacities to avoid building unusable memory into a memory sub-system.

[0017] Some conventional approaches attempt to increase the net bandwidth of a memory sub-system and decrease the amount of unusable storage capacity by adding memory devices, such as, for example, additional NAND memory devices, to the memory sub-system. Although such approaches can improve the net bandwidth of a memory sub-system, additional NAND memory devices occupy space within the memory sub-system. Any space occupied by additional NAND memory devices decreases the amount of space available within the memory sub-system to implement memory components that perform different functions. Additional NAND memory devices can also cause the memory sub-system to consume additional power. Occupying additional space and consuming additional power is undesirable because it results in the memory sub-system being larger and using more power to operate as intended.

[0018] Aspects of the disclosure address the above and other deficiencies by incorporating multiple ball grid array (BGA) assemblies (e.g., ball grid array solid state drive (BGASSD) assemblies) into a memory sub-system. For example, incorporating BGA assemblies into a memory sub-system in accordance with the disclosure can increase the bandwidth and storage capacity of the memory sub-system without increasing the size or power consumption of the memory sub-system. As used herein, the term “BGA assembly” refers to a memory assembly that includes memory (such as NAND flash memory and DRAM memory), firmware, and a controller chip, all in a single package. For example, in some embodiments, multiple BGA assemblies within a memory device of a memory sub-system can be coupled to a controller that is configured to perform operations on data stored in the multiple BGA assemblies.

[0019] Figure 1 An example computing environment 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is described. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such.

[0020] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing environment 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 An example of a host system 120 coupled to one memory sub-system 110 is described. The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and to read data from the memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0022] The host system 120 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example.

[0023] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs) such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0024] Examples of non-volatile memory devices (e.g., memory devices 130) include NAND-type flash memory. Each of the memory devices 130 can include one or more arrays of memory cells. The memory cells can include single-level cells (SLCs) that can store one bit of data per cell, multi-level cells (MLCs) that can store two bits of data per cell, triple-level cells (TLCs) that can store three bits of data per cell, quad-level cells (QLCs) that can store four bits of data per cell, and / or penta-level cells (PLCs) that can store five bits of data per cell, etc. As used herein, the term multi-level cell is used to refer to a cell configured to store more than one bit of data per cell (e.g., MLC, TLC, QLC, PLC, etc.). In some embodiments, a particular memory component can include an SLC portion of memory cells as well as MLC, TLC, QLC, and / or PLC portions of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0025] Although non-volatile memory components such as NAND-type flash memory are described, the memory devices 130 can be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or not-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0026] The memory sub-system controller 115 can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with specialized (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, a special- purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0027] The memory sub-system controller 115 can be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling operations of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0028] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While Figure 1 The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but instead relies on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0029] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations associated with the memory devices 130, such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0030] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive and decode an address from the memory sub-system controller 115 to access the memory devices 130.

[0031] In some embodiments, the memory device 130 includes a local media controller 135 that operates with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] The memory sub-system 110 can include a memory component 113. The memory component 113 can include various circuitry to facilitate storing large amounts of data (e.g., greater than 100 TB of data) in a memory device 130 with high bandwidth (e.g., 50 to 100 GB / s). In some embodiments, the memory component 113 can include a plurality of BGA components 112-1,..., 112-N (individually or collectively referred to as BGA components 112) to store data, and a processing device (e.g., a controller 136) to manage the BGA components 112.

[0033] In some embodiments, the memory device 130 includes at least a portion of the memory component 113. Further, the memory device 130 can include a local media controller 135 configured to execute instructions for performing the operations described herein. In some embodiments, the memory component 113 is part of the memory sub-system 110, an application, or an operating system.

[0034] In a non-limiting example, a device (e.g., the memory sub-system 110) can include a memory component 113. The memory component 113 can reside on a memory device 130. As used herein, the term “reside on” refers to something being physically located on a particular component. For example, the memory component 113 “resides on” the memory device 130 refers to a case where hardware circuitry comprising the memory component 113 is physically located on the memory device 130. The term “reside on” can be used interchangeably herein with other terms such as “deployed on” or “located on.”

[0035] The memory sub-system 110 (e.g., the memory device 130) can include a memory component 113 having a plurality of BGA components 112-1,..., 112-N (individually or collectively referred to as BGA components 112), where each respective one of the BGA components 112 includes a plurality of NAND memory blocks (e.g., Figure 2NAND memory blocks 222-1,..., 222-N) shown in FIG. 1, a BGA component controller (e.g., Figure 2 The BGA component controllers 216-1,..., 216-N) and firmware adjacent to the plurality of NAND memory blocks to manage the plurality of NAND memory blocks. In some embodiments, the BGA component controller of each respective one of the BGA components 112 can independently manage each respective NAND memory block in the respective BGA component 112. For example, the BGA component controller of a BGA component 112 can execute instructions to transfer data to and from one or more of the plurality of NAND memory blocks of the BGA component without transferring data to or from other NAND memory blocks of the BGA component.

[0036] The processing device (e.g., controller 136) is included in the memory component 113 to perform memory operations on the BGA component 112 (e.g., on data stored in the BGA component 112). The memory operations can include, for example, computational operations performed on data stored in the BGA component 112 (e.g., in the blocks of the BGA component). The controller 136 can be coupled to the BGA component 112 via an interface. For example, the interface can include a plurality of processing device and BGA component input / output (I / O) channels to couple the BGA component 112 to the controller 136. In some embodiments, the controller 136 can be coupled to the interface using the same number of processing device I / O channels as the number of BGA component I / O channels used to couple the BGA component 112 to the interface.

[0037] A controller (e.g., a memory sub-system controller) 115 can be operably coupled with the memory components 113 to manage data transferred between a host (e.g., a host system) 120 and the plurality of BGA components 112. In some embodiments, the controller 115 can perform host request operations corresponding to requests from the host system 120, where the host request operations are different from memory operations performed by the controller 136. In some embodiments, memory operations to manage the BGA components 112 can be performed on the BGA components 112, while operations to satisfy host requests can be performed on the controller 136. In some embodiments, the controller 136 and the plurality of BGA components 112 can be located on the same memory chip. In some embodiments, the controller 136 and the plurality of BGA components 112 are located on different memory chips. Further, the controller 115 can receive requests from the host system 120 to perform memory operations on the BGA components 112. The memory operations can be performed on the BGA components 112 by the controller 136, and results of the memory operations can be transferred (e.g., sent) from the controller 136 to the controller 115, which can transfer the results of the operations to the host system 120.

[0038] Figure 2 is a memory sub-system (e.g., a memory sub-system 100) according to some embodiments of the present disclosure, Figure 1a block diagram of an example BGA-stored memory subsystem 110). The memory subsystem includes a memory component 213 having a plurality of BGA components 212-1,..., 212-N (BGA components 212). Each of the BGA components 212 can include a plurality of memory blocks 222-1,..., 222-N (collectively or individually referred to as a plurality of memory blocks 222), a BGA component controller 216-1,..., 216-N (individually or collectively referred to as BGA component controllers 216), and firmware adjacent to (e.g., below) the plurality of memory blocks 222 to manage the plurality of memory blocks 222 (e.g., a BGA component 212 can include a plurality of memory blocks 222-1, a BGA component controller 216-1, and firmware adjacent to the memory blocks 222-1, etc.). Further, each BGA component 212 can include a BGA component interface 214-1,..., 214-N (individually or collectively referred to as BGA component interfaces 214). In some embodiments, the plurality of memory blocks 222 of a respective BGA component 212 can be interchangeable with memory blocks of different storage capacities. Further, the plurality of memory blocks 222 of each respective one of the BGA components 212 can comprise a plurality of vertically stacked NAND dies. The memory component 213 can also include a controller 236 to perform memory operations on the BGA components 212. The memory component 213 includes an interface 232 to couple the BGA components 212 to the controller 236. The BGA components 212 can be coupled to the interface 232 via a plurality of BGA component I / O channels 228-1,..., 228-N (individually or collectively referred to as BGA component I / O channels 228), and the controller 236 can be coupled to the interface 232 via a plurality of processing device I / O channels 234-1,..., 234-N (individually or collectively referred to as processing device I / O channels 234). In some embodiments, the interface 232 is a PCIe interface.

[0039] The ability to swap multiple memory blocks 222 of the BGA assemblies 212 with memory blocks of different storage capacities can benefit the memory sub-system by increasing the scalability of the memory sub-system. As used herein, the term "scalability" refers to the ability of the memory sub-system to increase or decrease performance in response to changes in application and system processing demands. The memory sub-system is tasked with storing an increased amount of data and performing an increased amount of memory operations. Building a scalable memory sub-system is a cost-effective way to meet this increased demand. A scalable memory sub-system allows components within the memory sub-system to be swapped for memory components that can meet the increased demand without unexpectedly decreasing performance. In previous approaches, if the demand for the memory sub-system increases beyond a threshold of the performance of the memory sub-system as currently constructed, the non-scalable memory sub-system can be replaced. However, replacing the entire memory sub-system is more time-consuming and expensive than swapping components within a scalable memory sub-system. Scalability of the memory sub-system can be the ability of the memory sub-system to store an increased amount of data and perform an increased amount of memory operations without an unexpected decrease in performance of the memory sub-system. The unexpected decrease in performance of the memory sub-system can include at least an unexpected decrease in bandwidth and / or storage capacity.

[0040] Swapping at least one of the multiple memory blocks 222 with at least one of the memory blocks having a higher storage capacity can increase the scalability of the memory sub-system. For example, swapping at least one of the multiple memory blocks 222 with at least one of the memory blocks having a higher storage capacity can increase the storage capacity of the BGA assemblies 212 without causing an unexpected decrease in performance of the memory sub-system. Swapping multiple ones of the multiple memory blocks 222 in each of the BGA assemblies 212 can result in a significant increase in storage capacity in the memory sub-system without causing an unexpected decrease in performance of the memory sub-system.

[0041] Increasing the BGA assembly I / O lanes 228 of the BGA assembly interfaces 214 can also increase the scalability of the memory sub-system. For example, increasing the BGA assembly I / O lanes 228 of each of the BGA assembly interfaces 214 from one BGA assembly I / O lane 228 to two BGA assembly I / O lanes 228 can increase the scalability of the memory sub-system because the increased number of BGA assembly I / O lanes 228 can increase the amount of data that can be transferred from the BGA assemblies 212 to the controller 236 in a particular time period. This increased capacity of transferred data can allow the memory sub-system to meet an increased demand for data transfer within the memory sub-system without an unexpected decrease in performance.

[0042] Each of the respective BGA components 212 (e.g., the BGA component interface 214 of each respective BGA component 212) can include a plurality of channels to couple the plurality of memory blocks 222 of the respective BGA component 212 to the BGA component interface 214. The bandwidth of the channels can depend at least on the type of interface (e.g., the BGA component interface 214), the generation of the interface, and the number of I / O lanes (e.g., the BGA component I / O lanes 228) of the interface. For example, the type of interface can be a PCIe interface (e.g., a fourth (4) or fifth (5) generation PCIe interface), and the number of I / O lanes can be the sum of one (1) or two (2) I / O lanes from each BGA component 212. In some embodiments, the plurality of channels can have a combined bandwidth that is greater than the bandwidth of the interface 232. The combined bandwidth of the plurality of channels having a greater bandwidth than the bandwidth of the interface 232 is beneficial because it allows the interface 232 to utilize its full bandwidth. If the combined bandwidth of the plurality of channels is less than the bandwidth of the interface 232, then the interface 232 will only be able to transfer data as fast as the channels can transfer data to the interface 232. This can result in the interface transferring data at a speed that is less than its available bandwidth.

[0043] In some embodiments, the BGA component controller 216 of each respective BGA component 212 is located below the plurality of memory blocks 222 of the respective BGA component 212. As shown in Figure 2 As shown in FIG. 3, the BGA component controller 216 can be located between the plurality of memory blocks 222 and the BGA component interface 214. The BGA component controller 216 can perform memory operations, where the memory operations performed on the BGA component 212 include computational operations performed on data stored in the plurality of memory blocks 222 of the BGA component 212.

[0044] Figure 3 is another block diagram of an example BGA storage for a memory sub-system (e.g., the memory sub-system 110) in accordance with some embodiments of the present disclosure. Figure 3 A memory component 313 is illustrated that includes a plurality of BGA components 312-1, 312-2,..., 312-N (individually or collectively referred to as BGA components 312) and a controller 336. The controller 336 can be positioned in close proximity to the plurality of BGA components 312. Placing the controller 336 in close proximity to the plurality of BGA components 312 can be beneficial by reducing the amount of time required to transfer data between the controller 336 and any of the plurality of BGA components 312. Reducing the amount of time required to transfer data between the controller 336 and the plurality of BGA components 312 can reduce the amount of time required to complete memory operations on data sent from a host to the memory component 313.

[0045] The number of BGA components 312 in memory component 313 can vary. In some embodiments, sixteen (16) BGA components may be present in memory component 313, and in other embodiments, thirty-three (32) BGA components may be present in memory component 313. Other embodiments may have different numbers of BGA components 312 in memory component 313. The number of BGA components 312 in memory component 313 and the type of interface in each BGA component 312 can determine the interface used to couple the BGA component 312 to the interface (e.g., Figure 2 The number of I / O channels of interface 232 shown in the figure. For example, if sixty-four (64) BGA components 312 each have a PCIe4 (fourth generation PCIe) BGA component interface, then each BGA component 312 can use two I / O channels to couple to the interface (e.g., Figure 2 (Interface 232 in the example). Therefore, in this example, the BGA component 312 uses 128 I / O channels coupled to the interface. In other embodiments, if each of the 16 BGA components 312 is coupled to the interface using a PCIe 5 (fifth generation PCIe) BGA interface, then each BGA interface can use one I / O channel coupled to the interface. In this embodiment, the BGA component 312 can use 16 I / O channels coupled to the interface.

[0046] The number of I / O channels used to couple BGA components 312 to the interface may depend on the combined bandwidth of the channels that couple the memory blocks within each BGA component 312 to the interface of each BGA component 312. In some embodiments, it is necessary to couple memory blocks to the BGA component interface to channels with a combined bandwidth greater than one hundred (100) gigabytes per second (GB / s). If the memory component interface is a PCIe4 interface, then 64 BGA components 312, each with an interface containing two I / O channels, can generate channels with a combined bandwidth of 103 GB / s. However, if the interface is a PCIe5 interface, then 32 BGA components 312, each with an interface containing one I / O channel, can generate channels with a combined bandwidth of 103 GB / s. Furthermore, if the 64 BGA components 312 each use one I / O channel to couple to the PCIe5 interface, then the channels within the BGA components 312 will have a combined bandwidth of 148 GB / s.

[0047] Figure 4is an example method 438 for BGA storage of a memory sub-system according to some embodiments of the present disclosure. At operation 442, the method 438 can include performing, by a controller included in a memory component of a memory device, a memory operation on data stored in a plurality of BGA components of the memory component, where each respective one of the BGA components includes a plurality of memory blocks to store the data and a BGA component controller and firmware adjacent to the plurality of memory blocks to manage memory operations performed on data stored in the plurality of memory blocks. For example, the controller, memory component, memory device, and BGA components can be the controller 136, memory component 113, memory device 130, and BGA components 112, respectively, of Figure 1 In some embodiments, the controller can distribute memory operations associated with managing the plurality of memory blocks of each respective one of the BGA components to the BGA component controller of the respective BGA component.

[0048] At operation 444, the method 438 can include communicating results of the memory operation performed on the data from the controller included in the memory component to an additional controller operatively coupled with the memory component (e.g., the memory sub-system controller 115 shown in Figure 1 In some embodiments, the results of the memory operation performed on the data stored in each of the BGA components can be communicated from the BGA component controllers to the controller included in the memory component substantially simultaneously. The results of the memory operation performed on the data can be communicated from the BGA components to the controller included in the memory component via a plurality of I / O channels. In some embodiments, the bandwidth of the I / O channels between each respective one of the BGA components and the controller can be adjusted. In some embodiments, the bandwidth of the I / O channels can be adjusted by modifying the number of I / O channels, modifying the type of I / O channels, or both. As stated above, each BGA component interface can have one or two I / O channels, and the type of I / O channels can be at least a PCIe 4 or PCIe 5 interface.

[0049] At operation 446, the results of the memory operation performed on the data can be communicated from the additional controller to the host. The results can be communicated via an interface coupling the additional controller to the host. Communicating the results to the host reduces the duration of the data transfer because the results of the memory operation are communicated to the host instead of the original data. Communicating the results of the memory operation to the host instead of the original data reduces the duration of the data transfer because the results of the memory operation can include less data than the original data. Communicating less data can result in a reduction in the duration of the data transfer. This reduction in the duration of the data transfer can result in a reduction in the length of time it takes to complete the memory operation within the memory sub-system.

[0050] Figure 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure can operate. For example, Figure 5 An example machine of computer system 500 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 500 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to memory components 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a peer machine or a server or a client machine in client-server network environments. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. Figure 1 Figure 1 Figure 1

[0051] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0052] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0053] ​​​Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0054] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0055] In one embodiment, instruction 526 includes instructions for implementing functionality corresponding to controller 536, which may be, for example... Figure 1 The controller 136 of the memory component 113. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more instruction sets. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0056] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0058] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0060] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0061] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: a memory component (113, 213, 313) having a plurality of ball grid array (BGA) components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2,..., 312-N), wherein each respective one of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2,..., 312-N) includes: a plurality of memory blocks (222-1, 222-N) within the respective BGA component; and a BGA component controller (216-1, 216-N) and firmware within the respective BGA component, the firmware being adjacent to the plurality of memory blocks (222-1, 222-N) to manage the plurality of memory blocks (222-1, 222-N); and a controller (136, 236, 336) included in the memory component (113, 213, 313) to perform memory operations on the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2,..., 312-N).

2. The memory device of claim 1, wherein each of the plurality of memory blocks (222-1, 222-N) within the respective BGA component is exchangeable with a memory block (222-1, 222-N) of a different storage capacity.

3. The memory device of claim 1, wherein the memory component (113, 213, 313) includes an interface (232) to couple the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2,..., 312-N) to the controller (136, 236, 336).

4. The memory device of any one of claims 1-3, wherein each respective one of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2,..., 312-N) includes a plurality of channels to couple the plurality of memory blocks (222-1, 222-N) within the respective BGA component to a BGA component interface (214-1, 214-N).

5. The memory device of claim 4, wherein the plurality of channels have a combined bandwidth that is greater than a bandwidth of the interface (232).

6. The memory device of any one of claims 1-3, wherein the interface (232) is a peripheral component interconnect express (PCIe) interface.

7. The memory device of any one of claims 1-3, wherein the BGA component controller (216-1, 216-N) within the respective BGA component is located below the plurality of memory blocks (222-1, 222-N) within the respective BGA component.

8. The memory device of any one of claims 1-3, wherein the plurality of memory blocks (222-1, 222-N) within the respective BGA component comprises a plurality of vertically stacked NAND dies.

9. The memory device of any one of claims 1-3, wherein the memory operation performed on the BGA component (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) comprises a compute operation performed on data stored in the plurality of memory blocks (222-1, 222-N) within the respective BGA component.

10. A method for a memory sub-system, comprising: performing, by a controller (136, 236, 336) included in a memory component (113, 213, 313) of a memory device, a memory operation on data stored in a plurality of ball grid array (BGA) components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) of the memory component (113, 213, 313), wherein each respective one of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) includes: a plurality of memory blocks (222-1, 222-N) within the respective BGA component to store the data; and a BGA component controller (216-1, 216-N) and firmware within the respective BGA component, the firmware adjacent to the plurality of memory blocks (222-1, 222-N) to manage the memory operation performed on the data stored in the plurality of memory blocks (222-1, 222-N); transmitting results of the memory operation performed on the data from the controller (136, 236, 336) included in the memory component (113, 213, 313) to an additional controller operably coupled with the memory component (113, 213, 313); and transmitting the results of the memory operation performed on the data from the additional controller to a host (120).

11. The method of claim 10, further comprising adjusting a bandwidth of an input / output (I / O) channel between each respective one of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) and the controller (136, 236, 336).

12. The method of any one of claims 10-11, further comprising adjusting the bandwidth of the I / O channel by modifying a number of the I / O channels, modifying a type of the I / O channel, or both.

13. The method of any one of claims 10-11, further comprising allocating, by the controller (136, 236, 336), memory operations associated with managing the plurality of memory blocks (222-1, 222-N) within the respective BGA component to the BGA component controller (216-1, 216-N) within the respective BGA component.

14. The method of any one of claims 10-11, further comprising simultaneously transferring the results of the memory operations performed on the data stored in each of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) from a BGA component controller (216-1, 216-N) to the controller (136, 236, 336) included in the memory component (113, 213, 313).

15. A memory device, comprising: a memory component (113, 213, 313) having a plurality of ball grid array (BGA) components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N), wherein each respective one of the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) includes: a plurality of NAND memory blocks (222-1, 222-N) within the respective BGA component; and a BGA component controller (216-1, 216-N) and firmware within the respective BGA component, the firmware adjacent to the plurality of NAND memory blocks (222-1, 222-N) to manage the plurality of NAND memory blocks (222-1, 222-N); a controller (136, 236, 336) included in the memory component (113, 213, 313) to perform memory operations on the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N); a controller operably coupled with the memory component (113, 213, 313) to manage data transferred between a host (120) and the plurality of BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N); and an interface (232) included in the memory component (113, 213, 313) that includes a plurality of input / output, I / O, channels to couple the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) to the controller (136, 236, 336).

16. The memory device of claim 15, wherein the BGA component controllers (216-1, 216-N) within the respective BGA component will independently manage each respective NAND memory block within the respective BGA component.

17. The memory device of any one of claims 15-16, wherein: the controller will perform host (120) request operations corresponding to requests from the host (120); and the host (120) request operations are different from the memory operations performed by the controller (136, 236, 336).

18. The memory device of any one of claims 15-16, wherein: the controller will receive requests from the host (120) to perform memory operations on the BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N); and the controller will transfer results of the operations to the host (120).

19. The memory device of any one of claims 15-16, wherein the controller (136, 236, 336) and the plurality of BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) are located on the same memory chip.

20. The memory device of any one of claims 15-16, wherein the controller (136, 236, 336) and the plurality of BGA components (112-1, 112-N, 212-1, 212-N, 312-1, 312-2, …, 312-N) are located on different memory chips.

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