Peak power management connectivity check in memory devices

Abstract

Embodiments of this disclosure relate to peak power management connectivity checks in memory devices. A memory device includes a plurality of memory dies, each of the plurality of memory dies including a memory array and a power management component operatively coupled to the memory array. The power management component sends test values ​​to and receives one or more other test values ​​from one or more other power management components on one or more other memory dies. The power management component compares the test values ​​and the one or more other test values ​​with a set of expected values, and determines that the signaling connection between the power management component and the one or more other power management components is functional in response to a match between the test values ​​and the one or more other test values ​​and the set of expected values.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to peak power management connectivity checks in memory devices within memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a memory device is provided. The memory device includes a plurality of memory dies. Each of the plurality of memory dies includes a memory array and a power management component. The power management component is operatively coupled to the memory array and performs operations including: sending test values ​​to one or more other power management components on one or more other memory dies; receiving one or more other test values ​​from one or more other power management components; comparing the test values ​​and one or more other test values ​​with a set of expected values; and determining that a signal connection between the power management component and the one or more other power management components is functional in response to a match between the test values ​​and the set of expected values.

[0004] According to another embodiment of this disclosure, a method is provided. The method includes: sending test values ​​to one or more other power management components on one or more other memory dies among the plurality of memory dies; receiving one or more other test values ​​from one or more other power management components; comparing the test values ​​and the one or more other test values ​​with a set of expected values; and determining, in response to the test values ​​and the set of one or more other test values ​​matching the expected values, that a signal connection between the power management components and the one or more other power management components is functional.

[0005] According to another embodiment of this disclosure, a memory device is provided. The memory device includes: a plurality of memory dies and a power management system. The power management system includes a corresponding power management component disposed on each of the plurality of memory dies. A first power management component of a first memory die of the plurality of memory dies is configured to send a first test value to the remaining memory dies of the plurality of memory dies during a first time period when the first power management component holds a token. The first time period is measured using a clock signal shared by the plurality of memory dies. A second power management component of a second memory die of the plurality of memory dies is configured to send a second test value to the remaining memory dies of the plurality of memory dies during a second time period when the second power management component holds a token. The second time period is measured using a clock signal shared by the plurality of memory dies. The first power management component is configured to compare the first test value and the second test value with a set of expected values ​​to verify the operation of the first power management component and the second power management component. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 3 This is a block diagram illustrating a multi-die package having multiple memory dies in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for performing a peak power management connectivity check in a memory device of a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0012] This disclosure relates to peak power management connectivity checks in memory devices within a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of both. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0013] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0014] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and can comprise a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device can include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, the memory device can include multiple access line driver circuits and power circuitry that can be shared by the planes of the memory device to facilitate concurrent access to pages containing different page types on two or more memory planes. For ease of description, these circuits can generally be referred to as independent plane driver circuits. The control logic on a memory device comprises multiple separate processing threads to perform concurrent memory access operations (e.g., read, program, and erase operations). For example, each processing thread corresponds to a specific memory plane and utilizes associated independent plane driver circuitry to perform memory access operations on that specific memory plane. As these processing threads operate independently, the power consumption and requirements associated with each processing thread also change.

[0015] The capacitive load of 3D memory is typically large and can continue to grow as the process scales up. During sensing (e.g., read or verify), programming, and erasing operations, various access lines, data lines, and voltage nodes can be charged or discharged very rapidly, allowing memory array access operations to meet performance specifications typically required to meet data throughput targets, as may be specified by customer requirements or industry standards. For sequential read or programming, multi-plane operations are often used to increase system throughput. Therefore, typical memory devices can have high peak current usage, which can be four to five times the average current amplitude. Thus, given the high average market demands for this total current usage budget, operating more than four memory devices in parallel can become challenging.

[0016] Various techniques have been used to manage the power consumption of memory subsystems containing multiple memory devices, many of which rely on memory subsystem controllers to stagger the activity of the memory devices, thereby avoiding high-power portions of access operations performed in parallel across more than one memory device. For example, in a memory package containing multiple memory devices (e.g., multiple individual dies), a Peak Power Management (PPM) system may exist, where each memory device may include a PPM component configured to perform power budget arbitration for the respective memory device. The PPM system employs a token-based round-robin scheduling protocol, whereby each PPM component rotates with the token holder (e.g., after a number of cycles of setting a shared clock signal) and broadcasts a quantized current budget consumed by its respective memory device during a given time period. Other PPM components on each other memory device receive this broadcast information and can thus determine the available current budget in the memory subsystem during said time period. When holding a token, a PPM component can request a certain amount of current for its respective memory device until the available current budget of the memory package is reached. In most memory subsystems, the PPM components in the memory package communicate with each other in a closed-loop environment (i.e., sharing clock and data signals). The clock and data signals shared between PPM components are not accessible from outside the package, and wire bonding failures cannot be verified when PPM components are connected to signal transmission lines. Therefore, the functionality of the PPM system cannot be tested or verified after package assembly or throughout the lifetime of the memory subsystem. Consequently, faults in the PPM system may go undetected, leading to a reduction in overall performance and quality of service provided by each memory device.

[0017] The aspects of this disclosure address the above and other deficiencies by providing peak power management connectivity checks within the memory devices of the memory subsystem. In one embodiment, the memory subsystem includes multiple memory devices implementing a PPM system, wherein each memory device may contain a PPM component. Utilizing existing signal connections (i.e., clock and data signal connections), the PPM system can perform connectivity checks to verify appropriate physical connectivity between PPM components on each die in the package, as well as appropriate operation of the PPM system itself. In one embodiment, a test sequence is executed, wherein a set of test values ​​is propagated among the PPM components. Each PPM component may broadcast a corresponding value received by other PPM components on each other memory device and stored in a corresponding register. After the test sequence is completed, the values ​​stored in the corresponding registers are compared with an expected set of values ​​to verify appropriate operation. A mismatch between the values ​​stored in the corresponding registers and the expected set of values ​​may indicate a wire connection fault or other connectivity failure in the PPM system.

[0018] The advantages of this approach include, but are not limited to, efficient power management solutions for multi-die memory subsystems. PPM connectivity checks provide the ability to verify the internal connectivity of PPM pads, wires, and other connections without operating the memory package in full test mode. Testing and verification can also be performed faster than other methods because all computations are performed through the PPM components on the memory device itself, without relying on system-level controllers. Furthermore, testing provides verification that the PPM system is functioning properly, ensuring improvements in overall performance and quality of service provided by each memory device.

[0019] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing unit.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0023] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0024] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance by combining with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as MLC, TLC, QLC, or PLC portions. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0028] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0030] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0031] In some embodiments, local memory 119 may include memory registers storing memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0032] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0033] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0034] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] In one embodiment, the memory device 130 includes a peak power management (PPM) component 150. In another embodiment, a local media controller 135 of the memory device 130 includes at least a portion of the PPM component 150. In this embodiment, the PPM component 150 may be implemented as hardware or firmware, stored on the memory device 130, and executed by control logic (e.g., the local media controller 135) to perform operations related to the peak power management connectivity check operations described herein. In other embodiments, the PPM component 150 is implemented within the memory device 130 but separate from the local media controller 135.

[0036] In one embodiment, PPM component 150 may perform a connectivity check to verify appropriate physical connectivity between itself and other PPM components on other memory dies in memory subsystem 110. In one embodiment, PPM component 150 may perform a test sequence by propagating a set of test values ​​among other PPM components. Each PPM component may broadcast a corresponding test value received by other PPM components on each other memory device and stored in a corresponding register. After the test sequence is completed, any PPM component, such as any of PPM component 150, may compare the value stored in the corresponding register with a set of expected values ​​to verify appropriate operation. A match between the value stored in the corresponding register and the set of expected values ​​may indicate that wire connections or other connectivity mechanisms in the PPM system are functional. Further details regarding the operation of PPM component 150 are described below.

[0037] Figure 2 A first device in the form of a presentable memory device 130 according to an embodiment and a presentable memory subsystem (e.g., Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0038] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2(Not shown in the text) can be programmed as one of at least two target data states.

[0039] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 204. The memory device 130 also includes an input / output (I / O) control circuitry 212 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 214 communicates with the I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch the address signal before decoding. A command register 224 communicates with the I / O control circuitry 212 and the local media controller 135 to latch incoming commands.

[0040] A controller (e.g., a local media controller 135 within memory device 130) responds to a command to control access to memory cell array 204 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to an address.

[0041] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 220 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 for output to memory subsystem controller 115; then, new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2(Not shown) to sense the data status of the memory cells in the memory cell array 204, for example, by sensing the status of the data lines connected to the memory cells. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0042] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0043] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 218. The data can then be written to data register 220 for programming memory cell array 204.

[0044] In this embodiment, cache register 218 may be omitted, and data may be written directly to data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0045] In one embodiment, the memory device 130 includes a PPM component 150. In one embodiment, the PPM component 150 includes two signal pads, such as pads 252 and 254. Pads 252 and 254 can be connected to and form a communication interface with individual wires, signal lines, or communication buses. For example, pad 252 can be connected to a clock signal line, such as... Figure 3 The clock signal ICLK is shown, and pad 254 can be connected to a data signal line, for example, as shown. Figure 3 The data signal HC# is shown. In one embodiment, the clock signal line and data signal line are typically shared by each PPM component on each memory die of a multi-die package. As described herein, in response to a command received from a requester, such as the memory subsystem controller 115, PPM component 150 may perform a connectivity check to verify proper physical connectivity between itself and PPM components on other memory dies in the memory subsystem 110. In one embodiment, test values ​​are propagated between PPM components via pad 254 and received test values ​​are stored in a register associated with PPM component 150, such as PPM register 256, for later comparison with a set of expected values.

[0046] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality can exceed that of a single component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0047] Figure 3 This is a block diagram illustrating a multi-die package having multiple memory dies in a memory subsystem according to some embodiments of the present disclosure. As illustrated, the multi-die package 300 includes eight memory dies 330(0) to 330(7), any one of which may be a representation of a memory device 130, such as... Figure 1 and Figure 2As shown in the figure. However, in other embodiments, the multi-die package 300 may include a different number of memory dies, such as additional or fewer memory dies. In one embodiment, memory dies 330(0) to 330(7) share a clock signal ICLK received via a clock signal line. Memory dies 330(0) to 330(7) may be selectively enabled in response to a chip enable signal (e.g., via a control link) and may communicate via a separate I / O bus. Additionally, a peak current indicator signal HC# is typically shared among memory dies 330(0) to 330(7). The peak current indicator signal HC# may typically be pulled to a specific state (e.g., pulled high). In one embodiment, each of memory dies 330(0) to 330(7) includes an example of a PPM component 150, which includes signal pads, such as pads 252 and 254, to receive both the clock signal ICLK and the peak current indicator signal HC#.

[0048] In one embodiment, a token-based protocol is used, wherein a token is circulated through each of the memory dies 330(0) to 330(7) to determine and broadcast the expected peak current value, even if some of the memory dies 330(0) to 330(7) may be disabled in response to their respective chip enable signals. The period during which a given PPM component 150 holds this token (e.g., a certain number of cycles of the clock signal ICLK) may be referred herein as the power management cycle of the associated memory die. At the end of the power management cycle, the token is sequentially passed to the next memory die. Finally, the token is again received by the same PPM component 150, which signals the start of a new power management cycle for the associated memory die and the completion of the PPM token loop (i.e., when the token has been passed to each of the memory dies 330(0) to 330(7) in the multi-die package 300). In one embodiment, the encoded value of the lowest expected peak current is configured such that each of its digits corresponds to a normal logic level of the peak current indicator signal HC#, wherein disabling the die does not change the peak current indicator signal HC#. However, in other embodiments, the memory die may be configured to drive a transition of the peak current indicator signal HC# when disabled in response to its respective chip enable signal, to indicate the encoded value of the lowest expected peak current after specification.

[0049] When a given PPM component 150 holds a token, it can determine the peak current value of a corresponding one of memory dies 330(0) to 330(7), which can be attributed to one or more processing threads on the memory die, and broadcast the indication of the peak current value via the peak current value indicator signal HC#. As described in more detail below, the PPM component 150 can further perform connectivity checks to verify the proper physical connectivity between the PPM components on each die in the package, and the proper operation of the PPM system itself. In one embodiment, a given PPM component of PPM component 150 on memory die 330(0) sends a test value to one or more other PPM components 150 on one or more other memory dies, such as PPM components 150 on memory dies 330(1) to 330(7), and receives one or more other test values ​​from one or more other PPM components. For example, any one of the PPM components of PPM component 150 on memory die 330(0) compares the test value and one or more other test values ​​with a set of expected values. In response to a set of test values ​​and one or more other test values ​​matching the expected values, PPM component 150 determines that the signal connection between PPM component 150 on memory die 330(0) and PPM components 150 on memory dies 330(1) to 330(7) is functional. In response to a set of test values ​​and one or more other test values ​​not matching the expected values, PPM component 150 determines that there is a wire bonding fault or other connectivity fault between PPM component 150 on memory die 330(0) and PPM components 150 on memory dies 330(1) to 330(7).

[0050] Figure 4 This is a flowchart of an example method for performing a peak power management connectivity check in a memory device of a memory subsystem according to some embodiments of the present disclosure. Method 400 may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The PPM component 150 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0051] At operation 405, a command is received. For example, processing logic (e.g., PPM component 150 on each of the memory dies 330(0)-330(7) in the multi-die package 300) may receive a command, such as an NVME Set Feature (SETF) command, from a requester, such as the memory subsystem controller 115 of the memory subsystem. In one embodiment, the command includes feature values ​​indicating a request to initiate a PPM component connectivity check on the memory device. In one embodiment, the command further includes one or more information pages, such as a first page containing fixed values ​​indicating the PPM connectivity check algorithm, a second page containing a seed value and a test value scheme, and a third page indicating a delay time indicator. The command may optionally include one or more additional information pages, which may be empty or contain some other default value. In one embodiment, the same command is received by the PPM component 150 on each of the memory dies 330(0) to 330(7) in the multi-die package 300.

[0052] At operation 410, a test value is sent. In one embodiment, processing logic (e.g., a PPM component 150) may send the test value to one or more other PPM components on one or more other memory dies during a first power management cycle. The first power management cycle may be defined by a number of cycles of a shared clock ICLK during which PPM component 150 holds a power management token. For example, if PPM component 150 on memory die 330(0) holds a power management token during the first power management cycle, then PPM component 150 may broadcast the test value to other PPM components on memory dies 330(1) through 330(7) via a shared data signal HC#. In one embodiment, the test value is based on a seed value and a test value scheme and may contain a three-digit value. For example, the test value may be a seed value received with the command at operation 405, or some variation of the seed value according to the test value scheme (e.g., the reciprocal or increment of the seed value).

[0053] At the end of the first power management cycle, the power management token is passed to the next PPM component (e.g., PPM component 150 on memory die 330(1)). Therefore, during the second power management cycle, PPM component 150 can broadcast the second test value to other PPM components on memory dies 330(0) and 330(2) through 330(7) via the shared data signal HC#. The second test value is received by PPM component 150 on memory die 330(0) through all other PPM components. The power management cycle continues according to the shared clock signal ICLK, where each PPM component takes turns broadcasting its corresponding test value (commonly "other test values") to the other PPM components.

[0054] At operation 415, other test values ​​are received. After each PPM component on each of the memory dies in the multi-package has held a token and broadcast the corresponding test value for the corresponding power management cycle, a power management token loop is completed, and the power management token is returned to the initial PPM component. Therefore, at the end of the power management token loop, each PPM component 150 should have received the corresponding test value from each of the other PPM components.

[0055] At operation 420, the received test values ​​are stored. For example, the processing logic in each PPM component 150 may store these received test values, along with its own test value, in an associated register, such as PPM register 256. The test value scheme may define how the corresponding test values ​​sent by each PPM component 150 are related to each other. In one embodiment, the test value scheme is an even / odd or alternating scheme. In this embodiment, the alternating test values ​​in the corresponding test values ​​contain the reciprocal of the seed value, and the remaining corresponding test values ​​contain the seed value itself. For example, if the PPM component 150 on memory die 330(0) sends the seed value, then the PPM component 150 on memory die 330(1) sends the reciprocal of the seed value (i.e., each of the three bits is inverted), the PPM component 150 on memory die 330(2) sends the seed value, the PPM component 150 on memory die 330(3) sends the reciprocal of the seed value, and so on. In another embodiment, the test value scheme is an incrementing scheme. In this embodiment, each corresponding test value contains a corresponding increment of the seed value. For example, if the PPM component 150 on memory die 330(0) sends a seed value, then the PPM component 150 on memory die 330(1) sends a first incremental seed value (e.g., the seed value plus one), the PPM component 150 on memory die 330(2) sends a second incremental seed value (e.g., the seed value plus two), and so on. In other embodiments, other test value schemes are possible.

[0056] At operation 425, a command is received. For example, the processing logic may receive a command, such as an NVME Set Feature (SETF) command, from a requester, such as the memory subsystem controller 115 of the memory subsystem. In one embodiment, the command includes feature values ​​indicating a request for verification of the connectivity check of the PPM components of the memory device. In one embodiment, the command further includes one or more information pages, such as a first page containing fixed values ​​indicating the request for verification and a second page containing a seed value and a test value scheme. The command may optionally include one or more additional information pages, which may be empty or contain some other default value. In one embodiment, the same command is received by the PPM components 150 on each of the memory dies 330(0) to 330(7) in the multi-die package 300.

[0057] At operation 430, a set of expected values ​​is determined. For example, the processing logic may determine the set of expected values ​​based on the seed value and test value scheme received in the command at operation 425. The set of expected values ​​represents values ​​broadcast by each PPM component 150 and received and stored in an associated register, such as PPM register 256, if all signal connections between PPM components 150 are functional. Therefore, depending on the test value scheme, the set of expected values ​​may represent alternating test values, incremental test values, or some other set of values. In one embodiment, each PPM component 150 on each memory die in a multi-die package may determine a corresponding set of expected values.

[0058] At operation 435, values ​​are compared. For example, the processing logic may compare the test value with a set of expected test values ​​determined at operation 430. In one embodiment, PPM component 150 may read the received test value from PPM register 256 and compare each test value with a corresponding expected test value in the set of expected test values. Test values ​​that are the same are said to match the corresponding expected test value. If at operation 440, the test value matches the set of expected test values, then the signal connection between the PPM components is determined to be functional. If at operation 445, one or more of the test values ​​do not match the set of expected test values, then a signal connection fault (e.g., a wire connection fault) is determined to exist between the PPM components.

[0059] At operation 450, a command is received. For example, the processing logic may receive a command from a requester, such as the memory subsystem controller 115 of the memory subsystem, for example, an NVME Get Characteristics (GETF) command. In one embodiment, the command includes a characteristic value indicating a request to verify the results of a PPM component connectivity check on the memory device. At operation 455, a result is returned. For example, the processing logic may return an indication of the verification result of the PPM component connectivity check to the requester. In one embodiment, the indication includes one or more values ​​indicating whether each of the test values ​​matches a corresponding value in a set of expected values. The requester may decode the one or more values ​​to identify a PPM component (if present) that is suffering from a PPM component connectivity failure.

[0060] Figure 5 This describes an instance machine of computer system 500, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of PPM component 150). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0061] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0062] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518, which communicate with each other via a bus 530.

[0063] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0064] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 526 or software embodying any one or more of the methods or functions described herein. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, the main memory 504 and processing device 502 also constituting machine-readable storage medium. Machine-readable storage medium 524, data storage system 518 and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0065] In one embodiment, instruction 526 includes implementation corresponding to Figure 1 The PPM component 150 contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0066] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this paper, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0067] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to these quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0068] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0070] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0071] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A plurality of memory dies, each of the plurality of memory dies comprising: Memory array; and A peak power management component, operatively coupled to the memory array, wherein the peak power management component performs operations including: During the first power management token loop, the test value is sent to one or more other peak power management components on one or more other memory dies among the plurality of memory dies; During the first power management token loop, one or more other test values ​​are received from one or more other peak power management components, wherein at least one of the one or more other test values ​​is different from the test value, and wherein the test value and the one or more other test values ​​are derived from a seed value according to a defined test value scheme. Compare the test value and the set of one or more other test values ​​with the expected value; and In response to the set of test values ​​and one or more other test values ​​matching the expected values, the signal connection between the peak power management component and the one or more other peak power management components is determined to be functional.

2. The memory device of claim 1, wherein the peak power management component further performs operations including: Receive a first command requesting the initiation of a peak power management component connectivity check of the memory device, wherein the first command includes an indication of the seed value and the test value scheme.

3. The memory device of claim 2, wherein the peak power management component further performs operations including: The test value and the one or more other test values ​​are stored in a register associated with the peak power management component.

4. The memory device of claim 3, wherein the peak power management component further performs operations including: Receive a second command requesting verification of the peak power management component connectivity check of the memory device, wherein the second command includes an indication of the seed value and the test value scheme.

5. The memory device of claim 4, wherein the peak power management component further performs operations including: In response to receiving the second command, the set of expected values ​​is determined based on the seed value and the test value scheme, wherein comparing the test value and the one or more other test values ​​with the set of expected values ​​includes reading the test value and the one or more other test values ​​from the register.

6. The memory device of claim 5, wherein the peak power management component further performs operations including: A third command to receive the result of the requested verification; and In response to receiving the third command, an indication of the verification result is returned, indicating whether the test value and the one or more other test values ​​match the set of expected values.

7. The memory device of claim 1, wherein, according to the test value scheme, the test value includes the seed value, and wherein the alternating test value among the one or more other test values ​​includes the reciprocal of the seed value.

8. The memory device of claim 1, wherein, according to the test value scheme, the test value includes the seed value, and wherein a corresponding test value among the one or more other test values ​​includes an increment of the seed value.

9. A method for memory operations, comprising: During the first power management token loop, the test value is sent to one or more other peak power management components on one or more other memory dies through the peak power management component on the memory die; During the first power management token loop, one or more other test values ​​are received from one or more other peak power management components, wherein at least one of the one or more other test values ​​is different from the test value, and wherein the test value and the one or more other test values ​​are derived from a seed value according to a defined test value scheme. Compare the test value and the set of one or more other test values ​​with the expected value; and In response to the set of test values ​​and one or more other test values ​​matching the expected values, the signal connection between the peak power management component and the one or more other peak power management components is determined to be functional.

10. The method of claim 9, further comprising: A first command is received requesting the initiation of a peak power management component connectivity check on the plurality of memory dies, wherein the first command includes an indication of the seed value and the test value scheme.

11. The method of claim 10, further comprising: The test value and the one or more other test values ​​are stored in a register associated with the peak power management component.

12. The method of claim 11, further comprising: Receive a second command requesting verification of the peak power management component connectivity check of the plurality of memory dies, wherein the second command includes an indication of the seed value and the test value scheme.

13. The method of claim 12, further comprising: In response to receiving the second command, the set of expected values ​​is determined based on the seed value and the test value scheme, wherein comparing the test value and the one or more other test values ​​with the set of expected values ​​includes reading the test value and the one or more other test values ​​from the register.

14. The method of claim 13, further comprising: A third command to receive the result of the verification request; and In response to receiving the third command, an indication of the verification result is returned, indicating whether the test value and the one or more other test values ​​match the set of expected values.

15. The method of claim 9, wherein, according to the test value scheme, the test value includes the seed value, and wherein the alternating test value among the one or more other test values ​​includes the reciprocal of the seed value.

16. The method of claim 9, wherein, according to the test value scheme, the test value includes the seed value, and wherein a corresponding test value among the one or more other test values ​​includes an increment of the seed value.

17. A memory device comprising: Multiple memory dies; and A peak power management system, comprising a corresponding peak power management component disposed on each of the plurality of memory dies. In the plurality of memory dies, a first peak power management component of a first memory die is configured to send a first test value to the remaining memory dies of the plurality of memory dies during a first time period of a first power management token loop while the first peak power management component holds a token, wherein the first time period is measured by a clock signal shared by the plurality of memory dies. The second peak power management component of the second memory die among the plurality of memory dies is configured to send a second test value to the remaining memory dies of the plurality of memory dies during a second time period of the first power management token loop while the second peak power management component holds the token, wherein the second time period is measured by a clock signal shared by the plurality of memory dies, wherein the second test value is different from the first test value, and wherein the first test value and the second test value are based on a seed value and test value scheme received from a controller associated with the memory device. The first peak power management component is configured to compare the first test value and the second test value with a set of expected values ​​to verify the operation of the first peak power management component and the second peak power management component.

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