A three-dimensional fan-out packaging structure and manufacturing method thereof

Abstract

The present invention relates to the field of integrated circuit packaging technology, and specifically discloses a three-dimensional fan-out packaging structure, which includes: a passive carrier board, which is provided with multiple metal-filled blind vias, and a first redistribution metal layer and a first redistribution passivation layer are formed on the front side; the first redistribution passivation layer is connected to a first chip plastic package structure via vertical lead pads and vertical leads, a second redistribution metal layer and a second redistribution passivation layer are formed on the first chip plastic package structure, and a second chip plastic package structure is formed on the second redistribution passivation layer; a back groove is formed on the back side of the passive carrier board, and a back passivation layer is provided on the back side of the passive carrier board except for the bottom wall position of the back groove, a metal bump is formed in a part of the back groove, and another part of the back groove is connected to a third chip structure. The present invention also discloses a method for manufacturing a three-dimensional fan-out packaging structure. The three-dimensional fan-out packaging structure provided by the present invention effectively solves the problems of warping and heat dissipation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a three-dimensional fan-out packaging structure and a method for manufacturing the three-dimensional fan-out packaging structure. Background Art

[0002] Packaging technology emerged alongside the invention of the integrated circuit. Its primary functions are power distribution, signal distribution, heat dissipation, and protection. Along with the advancement of chip technology, packaging technology has continued to innovate. Package interconnect density continues to increase, package thickness continues to decrease, and three-dimensional packaging and system-level packaging methods continue to evolve. As emerging sectors such as the Internet, Internet of Things, automotive electronics, high-performance computing, 5G, and artificial intelligence place higher demands on advanced packaging, packaging technology is rapidly developing and innovative technologies are constantly emerging. Currently, with the slowdown of Moore's Law, the importance of packaging technology has become even more prominent, becoming a key means of miniaturizing and multifunctionalizing electronic products, reducing power consumption, and increasing bandwidth. Advanced packaging is moving towards system-level integration, high speed, high frequency, and three-dimensionality.

[0003] Typically, achieving high-density 3D packaging requires vertical interconnect technologies, including TSV, TGV, and TMV. As chip integration continues to increase, the number and density of pins are rapidly increasing, placing new demands on vertical interconnect density and via size. Furthermore, the increase in chip count and interconnect density inevitably leads to an increase in the number of rewiring layers and increased device power consumption. The resulting warping and heat accumulation are also pressing issues that need to be addressed. Summary of the Invention

[0004] The present invention provides a three-dimensional fan-out packaging structure and a method for manufacturing the three-dimensional fan-out packaging structure, which solve the problems of warping and heat accumulation existing in the related art.

[0005] As a first aspect of the present invention, a three-dimensional fan-out packaging structure is provided, comprising:

[0006] A passive carrier board, wherein a plurality of metal-filled blind vias are provided in the passive carrier board;

[0007] A first rewiring metal layer and a first rewiring passivation layer are formed on the front surface of the passive carrier, wherein the first rewiring metal layer and the first rewiring passivation layer are both in contact with the metal-filled blind via;

[0008] The first redistribution passivation layer is connected to a first chip plastic package structure via a vertical lead pad and a vertical lead, a second redistribution metal layer and a second redistribution passivation layer are formed on the first chip plastic package structure, and a second chip plastic package structure connected to the vertical lead is formed on the second redistribution passivation layer;

[0009] A back groove corresponding to the position of the metal-filled blind hole is formed on the back of the passive carrier. A back passivation layer is provided on the back of the passive carrier except for the bottom wall of the back groove. Metal bumps are formed in a part of the back groove, and another part of the back groove is connected to the third chip structure.

[0010] Furthermore, the first rewiring passivation layers are arranged in intervals within the first rewiring metal layer, and the vertical lead pads are all provided on the upper surfaces of the first rewiring passivation layers.

[0011] Furthermore, the first chip plastic packaging structure includes a first chip and a first plastic packaging layer, the first chip is flip-chip mounted on the vertical lead pad located in the middle area, the first plastic packaging layer is located on the vertical lead pad located in the edge area and surrounds the side wall of the first chip, the vertical lead is arranged on the vertical lead pad located in the edge area, and the vertical lead is encapsulated by the first plastic packaging layer.

[0012] Furthermore, the second redistribution metal layer covers the upper surface of the first chip and the first plastic packaging layer, and the second redistribution passivation layers are arranged at intervals on the upper surface of the first plastic packaging layer and are both connected to the vertical leads.

[0013] Furthermore, the second chip plastic packaging structure includes a second chip and a second plastic packaging layer, the second chip is flip-chip mounted on top of the first plastic packaging layer, and the bumps of the second chip are connected to the second redistribution passivation layer, the second plastic packaging layer is located and covers the second redistribution metal layer, and surrounds the side walls of the first plastic packaging layer and the second chip.

[0014] Furthermore, a second filling layer is provided between the second chip and the second redistribution metal layer.

[0015] Furthermore, a first filling layer is provided between the first chip and the first redistribution metal layer.

[0016] As another aspect of the present invention, a method for manufacturing a three-dimensional fan-out package structure is provided, for manufacturing the three-dimensional fan-out package structure described above, wherein the manufacturing method comprises:

[0017] Providing a passive carrier board, wherein a plurality of metal-filled blind holes are provided in the passive carrier board;

[0018] Performing n-layer rewiring on the front side of the passive carrier to obtain a first rewiring metal layer and a first rewiring passivation layer, wherein both the first rewiring metal layer and the first rewiring passivation layer are in contact with the metal-filled blind via;

[0019] forming vertical lead pads on the first redistribution passivation layer;

[0020] flip-chipping the first chip onto the vertical lead pad located in the middle area;

[0021] Fabricating vertical leads on the vertical lead pads located in the edge area;

[0022] Making a first plastic packaging layer to encapsulate the vertical leads and the first chip;

[0023] Performing n-layer rewiring on the first plastic encapsulation layer to obtain a second rewiring metal layer and a second rewiring passivation layer, wherein the second rewiring passivation layer is located directly above the vertical lead and connected to the vertical lead;

[0024] Flip-chipping a second chip onto the first plastic packaging layer, with the bumps of the second chip connected to the second redistribution passivation layer;

[0025] forming a second plastic encapsulation layer on the second redistribution metal layer, wherein the second plastic encapsulation layer encapsulates the sidewall of the first plastic encapsulation layer and the second chip;

[0026] forming a back groove on the back side of the passive carrier corresponding to the position of the metal-filled blind hole and exposing the filling metal in the metal-filled blind hole;

[0027] forming a back passivation layer on the back side of the passive carrier at a position where the bottom wall of the back groove is removed;

[0028] Metal bumps are formed in a portion of the back surface grooves, and a third chip structure is flip-chip mounted in another portion of the back surface grooves.

[0029] Furthermore, the method further includes the following steps after the step of flip-chipping the first chip onto the vertical lead pad located in the middle area:

[0030] A gap is filled between the first chip and the first rewiring metal layer using a filling technology to form a first filling layer.

[0031] Furthermore, the method further includes the following steps after the step of flip-chipping the second chip on top of the first plastic packaging layer:

[0032] A gap is filled between the second chip and the second redistribution metal layer using a filling technology to form a second filling layer.

[0033] The three-dimensional fan-out packaging structure provided by the present invention, by providing a passive carrier board as a support, can effectively improve the support strength and provide a heat dissipation channel compared with the existing technology, greatly improving the warping and heat dissipation problems caused by multi-layer rewiring and plastic packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0035] Figure 1 This is a schematic structural diagram of the three-dimensional fan-out packaging structure provided by the present invention.

[0036] Figure 2 It is a structural schematic diagram of the passive carrier provided by the present invention.

[0037] Figure 3 Schematic diagram of preparing front grooves on a passive carrier.

[0038] Figure 4 Schematic diagram of preparing an insulating layer on a passive carrier.

[0039] Figure 5 It is a schematic diagram of the structure of filling metal blind vias on a passive carrier board.

[0040] Figure 6 Schematic diagram of preparing n-layer rewiring on the front side of a passive carrier.

[0041] Figure 7 Schematic diagram of a passive carrier board with vertical lead pads prepared on the front side.

[0042] Figure 8 Schematic diagram of chip flip-chip and bottom filling on the front side of the passive carrier.

[0043] Figure 9 This is a schematic diagram for making vertical leads.

[0044] Figure 10 This is a schematic diagram of the first plastic sealing.

[0045] Figure 11 This is a schematic diagram of rewiring on the surface of the first plastic layer.

[0046] Figure 12 It is a schematic diagram of chip flipping and bottom filling on the surface of the first plastic packaging layer.

[0047] Figure 13 This is a schematic diagram of the second plastic sealing.

[0048] Figure 14 This is a schematic diagram of making a back groove on the back side of a passive carrier board.

[0049] Figure 15 Schematic diagram of forming a back passivation layer on the back side of a passive carrier. DETAILED DESCRIPTION

[0050] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0053] In this embodiment, a three-dimensional fan-out packaging structure is provided. Figure 1 is a schematic structural diagram of a three-dimensional fan-out packaging structure provided according to an embodiment of the present invention. Figure 1 Shown, including:

[0054] A passive carrier 101, wherein a plurality of metal-filled blind vias 102 are provided in the passive carrier 101;

[0055] In the embodiment of the present invention, the passive carrier board 101 specifically refers to a carrier board without any form of internal power supply during operation.

[0056] A first rewiring metal layer 104 and a first rewiring passivation layer 103 are formed on the front surface of the passive carrier 101, and both the first rewiring metal layer 104 and the first rewiring passivation layer 103 are in contact with the metal-filled blind via 102;

[0057] The first redistribution passivation layer 103 is connected to the first chip plastic package structure via the vertical lead pad 105 and the vertical lead 108. The first chip plastic package structure is formed with a second redistribution metal layer 202 and a second redistribution passivation layer 201. The second redistribution passivation layer 201 is formed with a second chip plastic package structure connected to the vertical lead 108.

[0058] A back groove 301 corresponding to the position of the metal-filled blind hole 102 is formed on the back side of the passive carrier 101. A back passivation layer 302 is provided on the back side of the passive carrier 101 except for the bottom wall of the back groove 301. Metal bumps 303 are formed in a portion of the back groove 301, and another portion of the back groove 301 is connected to the third chip structure.

[0059] It should be noted that Figure 1 Taking the direction shown as an example, the upper surface of the passive carrier is the front surface, and the lower surface of the passive carrier is the back surface.

[0060] Specifically, the passive carrier 101 can be made of silicon, glass or ceramic.

[0061] The three-dimensional fan-out packaging structure provided by the embodiment of the present invention, by providing a passive carrier as a support, can effectively improve the support strength and provide a heat dissipation channel compared to the existing technology, thereby greatly improving the warping and heat dissipation problems caused by multi-layer rewiring and plastic packaging.

[0062] It should be noted that the metal filled in the metal-filled blind hole 102 may be any one or more combinations of Ti, V, TiW, Ni, Cu, Al and Au.

[0063] Specifically, the first rewiring passivation layers 103 are arranged in intervals within the first rewiring metal layer 104 , and the vertical lead pads 105 are disposed on the upper surfaces of the first rewiring passivation layers 103 .

[0064] In an embodiment of the present invention, the vertical lead pad 105 may be made of any one or more of Al, Cu, Ti, TiW, V, Ni and Au.

[0065] Specifically, if Figure 1 As shown, the first chip molding structure includes a first chip 106 and a first molding layer 109. The first chip 106 is flipped on the vertical lead pad 105 located in the middle area. The first molding layer 109 is located on the vertical lead pad 105 in the edge area and surrounds the side wall of the first chip 106. The vertical lead 108 is arranged on the vertical lead pad 105 located in the edge area, and the vertical lead 108 is encapsulated by the first molding layer 109.

[0066] To achieve sealing, a first filling layer 107 is provided between the first chip 106 and the first rewiring metal layer 104 .

[0067] It should be understood that the gap is filled using a bottom filling technology to ensure bottom sealing, and the filled material forms the first filling layer 107 .

[0068] In the embodiment of the present invention, the material filled in the first filling layer 107 may be a composite material formed by resin and inorganic matter (SiO 2 or Al 2 O 3 ).

[0069] Specifically, the second rewiring metal layer 202 covers the upper surface of the first chip 106 and the first plastic layer 109 , and the second rewiring passivation layer 201 is spaced apart on the upper surface of the first plastic layer 109 and both are connected to the vertical lead 108 .

[0070] Specifically, the second chip plastic packaging structure includes a second chip 203 and a second plastic packaging layer 204. The second chip 203 is flip-chip mounted on top of the first plastic packaging layer 109, and the bumps of the second chip 203 are connected to the second redistribution passivation layer 201. The second plastic packaging layer 204 is located on and covers the second redistribution metal layer 202, and surrounds the side walls of the first plastic packaging layer 109 and the second chip 203.

[0071] To achieve sealing, a second filling layer 205 is provided between the second chip 203 and the second rewiring metal layer 202 .

[0072] It should be understood that the gap is filled using a bottom filling technology to ensure bottom sealing, and the filled material forms the second filling layer 205 .

[0073] In an embodiment of the present invention, the material filled in the second filling layer 205 may specifically be a composite material formed by resin and inorganic matter (SiO 2 or Al 2 O 3 ).

[0074] It should be noted that, in the embodiment of the present invention, the vertical lead 108 can be made of any one of Al, Cu and Au, and the height of the vertical lead 108 is usually greater than 25 μm.

[0075] In the embodiment of the present invention, the molding height of the first molding layer 109 is generally not greater than 294 μm, and the packaging thickness of the second molding layer 204 is greater than 50 μm.

[0076] As another embodiment of the present invention, a method for manufacturing a three-dimensional fan-out package structure is provided, for manufacturing the three-dimensional fan-out package structure described above, wherein the manufacturing method includes:

[0077] S1, such as Figures 2 to 5 As shown, a passive carrier 101 is provided, and a plurality of metal-filled blind vias 102 are arranged in the passive carrier 101 .

[0078] It should be noted that, in the embodiment of the present invention, the specific manufacturing method of the passive carrier 101 may include:

[0079] like Figure 2 As shown, a passive carrier 101 is provided, and the material can be silicon, glass or ceramic;

[0080] like Figure 3 As shown, a front groove 110 is formed on the front surface of the carrier by an etching process;

[0081] like Figure 4 As shown, the insulating layer 111 is prepared by photolithography, deposition and etching techniques, and the insulating layer material can be selected from any one of silicon oxide, silicon nitride, polyimide film and SMF;

[0082] like Figure 5 As shown, metal is filled in the carrier groove by deposition, electroplating or chemical plating technology to form a metal-filled blind hole 102. The metal material can be selected from Ti, V, TiW, Ni, Cu, Al, Au or a combination of several.

[0083] S2, performing n-layer rewiring on the front surface of the passive carrier to obtain a first rewiring metal layer 104 and a first rewiring passivation layer 103, wherein both the first rewiring metal layer 104 and the first rewiring passivation layer 103 are in contact with the metal-filled blind via 102;

[0084] It should be understood that if Figure 6 As shown, n-layer rewiring is performed using photolithography, physical vapor deposition, and electroplating techniques to form a first rewiring metal layer 104 and a first rewiring passivation layer 103 .

[0085] S3, forming a vertical lead pad 105 on the first redistribution passivation layer 103;

[0086] Specifically, in the embodiment of the present invention, Figure 7 As shown, the vertical lead pad 105 is prepared by photolithography, electroplating or chemical plating technology, and the pad material can be any one or more combinations of Al, Cu, Ti, TiW, V, Ni and Au.

[0087] S4, flip-chipping the first chip onto the vertical lead pad located in the middle area;

[0088] In the embodiment of the present invention, Figure 8 As shown, the chip 106 with bumps is flip-chip mounted onto the vertical lead pads 105 using flip-chip bonding technology.

[0089] In order to ensure bottom sealing, a gap is filled between the first chip 106 and the first redistribution metal layer 104 using a filling technology to form a first filling layer 107 .

[0090] S5, making vertical leads on the vertical lead pads located in the edge area;

[0091] In the embodiment of the present invention, Figure 9 As shown, the vertical lead 108 is prepared by vertical wire bonding technology. The material of the vertical lead can be Al, Cu, Au, etc. The height of the vertical lead 108 is greater than 25μm.

[0092] S6, making a first plastic packaging layer 109 to encapsulate the vertical leads 108 and the first chip 106;

[0093] In the embodiment of the present invention, Figure 10 As shown, the leads and chip are encapsulated using a plastic encapsulation technique to form a first plastic encapsulation layer 109, with a plastic encapsulation size no greater than 294 μm. The vertical lead metal and the back of the chip are then exposed by grinding, ensuring that the final resin encapsulation thickness is greater than 50 μm.

[0094] S7, performing n-layer rewiring on the first plastic encapsulation layer 109 to obtain a second rewiring metal layer 202 and a second rewiring passivation layer 201, wherein the second rewiring passivation layer 201 is located directly above the vertical lead 108 and connected to the vertical lead 108;

[0095] In the embodiment of the present invention, Figure 11 As shown, an n-layer rewiring is prepared on the first plastic packaging layer 109 by using photolithography, physical vapor deposition, and electroplating techniques to obtain a second rewiring metal layer 202 and a second rewiring passivation layer 201 .

[0096] S8, flip-chipping the second chip 203 on top of the first plastic packaging layer 109, and connecting the bumps of the second chip 203 to the second redistribution passivation layer 201;

[0097] In the embodiment of the present invention, Figure 12 As shown, the second chip 203 with bumps is flip-chip mounted on the vertical lead pads using flip-chip technology, and the gap is filled using bottom filling technology to ensure the bottom is sealed. The chip thickness is no more than 300 μm.

[0098] In order to ensure sealing, a gap is filled between the second chip 203 and the second redistribution metal layer 202 using a filling technology to form a second filling layer 205 .

[0099] S9, forming a second plastic encapsulation layer 204 on the second redistribution metal layer 202, wherein the second plastic encapsulation layer 204 encapsulates the sidewalls of the first plastic encapsulation layer 109 and the second chip 203;

[0100] Specifically, if Figure 13 As shown, the first plastic layer 109 is completely encapsulated by secondary plastic encapsulation technology to form a second plastic encapsulation layer 204, with a plastic encapsulation size of not less than 297 μm. The distance between the surface of the second chip 203 and the surface of the second plastic encapsulation layer 204 is not more than 200 μm.

[0101] S10, forming a back groove 301 on the back side of the passive carrier 101 corresponding to the position of the metal-filled blind hole 102, and exposing the filling metal in the metal-filled blind hole 102;

[0102] In the embodiment of the present invention, Figure 14 As shown, the back surface of the passive carrier 101 is etched using an etching technique to form a back surface groove 301 , exposing the filling metal in the metal-filled blind hole 102 of the passive carrier 101 .

[0103] S11, forming a back passivation layer 302 on the back side of the passive carrier 101 at a position where the bottom wall of the back groove 301 is removed;

[0104] Specifically, if Figure 15 As shown, the back passivation layer 302 is prepared by photolithography, deposition, and etching techniques. The material of the back passivation layer 302 can be silicon oxide, silicon nitride, polyimide film, SMF, etc.

[0105] S12 , forming metal bumps 303 in a portion of the back surface groove 301 , and flip-chipping a third chip structure in another portion of the back surface groove 301 .

[0106] Specifically, if Figure 1 As shown, the metal bumps 303 are prepared by ball planting, and the diameter of the metal bumps 303 is not less than 300 μm.

[0107] In the embodiment of the present invention, the third chip structure may specifically include a third chip 304 and a third filling layer 305 located between the third chip 304 and the back passivation layer 302 .

[0108] Specifically, the third chip 304 is flipped by flip-chip technology, and the space between the third chip 304 and the back passivation layer 302 is filled by bottom filling technology to form the third filling layer 305, wherein the thickness of the third chip is not more than 200 μm.

[0109] In summary, the manufacturing method of the three-dimensional fan-out packaging structure provided by the embodiment of the present invention increases the vertical interconnection density and effectively constructs the three-dimensional structure through vertical leads and two-time plastic packaging technology, thereby reducing the package size; at the same time, silicon-based, glass-based or ceramic-based is used as a passive carrier to provide support strength and heat dissipation channels, greatly improving the warping and heat dissipation problems caused by multi-layer rewiring and plastic packaging. In addition, the manufacturing method of the present invention is simple and suitable for large-scale mass production.

[0110] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional fan-out packaging structure, comprising a three-dimensional fan-out packaging structure, characterized in that: The three-dimensional fan-out packaging structure includes: A passive carrier board, wherein a plurality of metal-filled blind vias are provided in the passive carrier board; A first rewiring metal layer and a first rewiring passivation layer are formed on the front surface of the passive carrier, wherein the first rewiring metal layer and the first rewiring passivation layer are both in contact with the metal-filled blind via; The first redistribution passivation layer is connected to a first chip plastic package structure via a vertical lead pad and a vertical lead, a second redistribution metal layer and a second redistribution passivation layer are formed on the first chip plastic package structure, and a second chip plastic package structure connected to the vertical lead is formed on the second redistribution passivation layer; A back groove corresponding to the position of the metal-filled blind via is formed on the back of the passive carrier. A back passivation layer is provided on the back of the passive carrier except for the bottom wall of the back groove. Metal bumps are formed in a portion of the back groove, and another portion of the back groove is connected to the third chip structure. The method for manufacturing a three-dimensional fan-out packaging structure comprises the following steps: Providing a passive carrier board, wherein a plurality of metal-filled blind holes are provided in the passive carrier board; Performing n-layer rewiring on the front side of the passive carrier to obtain a first rewiring metal layer and a first rewiring passivation layer, wherein both the first rewiring metal layer and the first rewiring passivation layer are in contact with the metal-filled blind via; forming vertical lead pads on the first redistribution passivation layer; flip-chipping the first chip onto the vertical lead pad located in the middle area; Fabricating vertical leads on the vertical lead pads located in the edge area; Making a first plastic packaging layer to encapsulate the vertical leads and the first chip; Performing n-layer rewiring on the first plastic encapsulation layer to obtain a second rewiring metal layer and a second rewiring passivation layer, wherein the second rewiring passivation layer is located directly above the vertical lead and connected to the vertical lead; Flip-chipping a second chip onto the first plastic packaging layer, with the bumps of the second chip connected to the second redistribution passivation layer; forming a second plastic encapsulation layer on the second redistribution metal layer, wherein the second plastic encapsulation layer encapsulates the sidewall of the first plastic encapsulation layer and the second chip; forming a back groove on the back side of the passive carrier corresponding to the position of the metal-filled blind hole and exposing the filling metal in the metal-filled blind hole; forming a back passivation layer on the back side of the passive carrier at a position where the bottom wall of the back groove is removed; Metal bumps are formed in a portion of the back surface grooves, and a third chip structure is flip-chip mounted in another portion of the back surface grooves.

2. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, wherein: The first rewiring passivation layers are arranged in intervals within the first rewiring metal layer, and the upper surfaces of the first rewiring passivation layers are all provided with the vertical lead pads.

3. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1 or 2, characterized in that: The first chip plastic packaging structure includes a first chip and a first plastic packaging layer. The first chip is flip-chip mounted on the vertical lead pad located in the middle area. The first plastic packaging layer is located on the vertical lead pad in the edge area and surrounds the side wall of the first chip. The vertical lead is arranged on the vertical lead pad located in the edge area, and the vertical lead is encapsulated by the first plastic packaging layer.

4. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 3, wherein: The second redistribution metal layer covers the upper surface of the first chip and the first plastic packaging layer. The second redistribution passivation layers are arranged at intervals on the upper surface of the first plastic packaging layer and are both connected to the vertical leads.

5. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 4, wherein: The second chip plastic packaging structure includes a second chip and a second plastic packaging layer. The second chip is flip-chip mounted on top of the first plastic packaging layer, and the bumps of the second chip are connected to the second redistribution passivation layer. The second plastic packaging layer is located on and covers the second redistribution metal layer, and surrounds the side walls of the first plastic packaging layer and the second chip.

6. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 5, wherein: A second filling layer is provided between the second chip and the second redistribution metal layer.

7. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 3, wherein: A first filling layer is provided between the first chip and the first redistribution metal layer.

8. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, wherein: The method further includes the following steps after the step of flip-chipping the first chip onto the vertical lead pad located in the middle area: A gap is filled between the first chip and the first rewiring metal layer using a filling technology to form a first filling layer.

9. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, wherein: The method further includes the following steps after the step of flip-chipping the second chip on top of the first plastic packaging layer: A gap is filled between the second chip and the second redistribution metal layer using a filling technology to form a second filling layer.

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