Threshold adjustable comparator, threshold adjustment method and parallel analog-to-digital converter

Abstract

The invention discloses a comparator with adjustable threshold, a threshold adjustment method and a parallel analog-to-digital converter, which can realize the threshold adjustment of the comparator, avoid the influence of kickback noise on the next signal conversion, improve the conversion accuracy and reduce the power consumption. The comparator with adjustable threshold comprises a differential pair tube, a latch unit with a cross structure, a first switch, a second switch and a logic NAND gate circuit. The gates of the differential pair tube are respectively the in-phase input terminal and the inverting input terminal of the comparator. The voltage of the in-phase input terminal is the input voltage Vin, and the voltage of the inverting input terminal is the reference voltage Vip. The control terminals of the first switch and the second switch input the clock signal CLK. The width-to-length ratio of the differential pair tube is N:N-N:1. In the threshold adjustment method of the comparator, the flip voltage threshold of the comparator is controlled by an N-bit binary number. The parallel analog-to-digital converter comprises the above-mentioned comparator with adjustable threshold.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a threshold-adjustable comparator and a threshold-adjusting method thereof. The threshold-adjustable comparator and the threshold-adjusting method thereof are particularly suitable for high-speed and low-power parallel analog-to-digital converters (ADCs). Background Art

[0002] Analog-to-digital converter, abbreviated as ADC, is an electronic component that converts analog signals into digital signals. Several analog-to-digital converters are connected in parallel to form an analog CMOS integrated circuit structure. Traditional parallel analog-to-digital converters include modules such as resistor divider networks, comparator arrays, and encoders. However, the structure of traditional parallel comparators is relatively complex. Figure 1 , which mainly divides the reference power supply Vref into equally spaced voltages through a resistor divider network and sequentially serves as the threshold voltage of the comparator array. The comparators in the array simultaneously compare the input voltage Vin with the corresponding threshold voltage. The encoder obtains the binary code corresponding to the input voltage Vin and the reference voltage source Vref based on the results of the parallel comparison, thus completing the analog-to-digital conversion. However, the above traditional parallel architecture is easily affected by the kickback noise from the comparator. If the voltage divider resistor network cannot attenuate the interference of the kickback noise in time, it will affect the accuracy of the next conversion.

[0003] At present, the commonly used method to solve the kickback noise is to use a resistor with a smaller resistance value in the resistor network. While dividing the voltage, the current passes quickly, so that the threshold voltage generated by the resistor network is stable in a short time, that is, the time constant of the voltage division node is reduced. This method avoids the interference caused by the kickback noise affecting the accuracy of the next conversion. However, the use of multiple resistors in the resistor network increases the power consumption of the entire integrated circuit, and the comparator threshold voltage cannot be adjusted, which has poor flexibility in use. Summary of the invention

[0004] In view of the above problems existing in the prior art, the present invention provides a threshold adjustable comparator, a threshold adjustment method and a parallel analog-to-digital converter, which have a simple and reasonable structural design, can realize the threshold adjustment of the comparator, can avoid the interference caused by the kick-back noise affecting the accuracy of the next conversion, and can reduce power consumption.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A threshold adjustable comparator, comprising a differential pair of transistors, a latch unit of a cross structure, a first switch, a second switch, and a logic NAND gate circuit, characterized in that the source of the differential pair of transistors is connected to the drain of the latch unit, the gate, the drain of the second switch, and the input end of the logic NAND gate circuit; the source of the latch unit and the second switch is connected to a voltage source VDD, the drain of the differential pair of transistors is connected to the source of the first switch, the gates of the first switch and the second switch are connected to an external input clock signal, and the output of the logic NAND gate circuit is the output of the comparator;

[0007] The gates of the differential pair tubes are respectively the non-inverting input terminal and the inverting input terminal of the comparator, the voltage of the non-inverting input terminal is the input voltage Vin, and the voltage of the inverting input terminal is the reference voltage Vip; the control terminals of the first switch and the second switch input the clock signal CLK; the width-to-length ratio of the differential pair tubes is adjustable within the range of N:N to N:1, where N is an integer.

[0008] Its further characteristic is that

[0009] The differential pair transistors include a first NMOS transistor M5, a width-length adjustable NMOS transistor group M6 to M7. N+5 , switches connected one-to-one with the NMOS tubes in the NMOS tube group, the gates of the NMOS tubes in the NMOS tube group are connected to the input voltage Vin, the sources of the NMOS tubes in the NMOS tube group and the source of the first NMOS tube are connected to the drain of the second switch, the drains of the NMOS tubes in the NMOS tube group are respectively connected to one of the switches, the switches are controlled by an external register or an external calibration program, and the width and length of the NMOS tube group are adjusted by the switches;

[0010] The switches are NMOS tubes S1, S2, ..., SN, the drains of which are connected to the drain of the first switch, the gate and the drain of the latch unit, and the sources of which are connected to the first NMOS tubes M6 to M7. N+5 The drains of the first NMOS tubes M6 to M N+5 The source of is connected to the drain of the second switch, and the control ends of the NMOS tubes S1, S2, ..., SN are connected to a register or controlled by an external calibration program;

[0011] The reference voltage Vip is a fixed reference voltage Vref, and the fixed reference voltage Vref is generated by a reference voltage chip or a reference voltage generating circuit, and the reference voltage generating circuit is a bandgap reference circuit;

[0012] The cross-structure latch unit includes PMOS tubes M2 and M3, the first switch includes PMOS tubes M1 and M4, and the second switch includes PMOS tube M N+6 The logic NAND gate circuit includes a first NAND gate ND1 and a second NAND gate ND2. The gate of the PMOS tube M2 is respectively connected to the drain of the PMOS tube M3, the input ends of the first NAND gates ND1 and ND2, the drains of the NMOS tubes S1, S2...SN, and the drain of the first NMOS tube M5. The sources of the PMOS tubes M1, M2, M3, and M4 are all connected to the voltage source VDD.

[0013] A comparator threshold adjustment method is characterized in that an input voltage Vin is input to the same-direction input terminal of the comparator, and a reference voltage Vip is input to the reverse input terminal. The comparator flip voltage threshold is controlled by a set of N-bit binary numbers. The N-bit binary number control is achieved by adjusting the width-to-length ratio of the differential pair tubes in the comparator within the range of N:N to N:1, where N is an integer.

[0014] Its further characteristic is that

[0015] The specific method for controlling the comparator flip voltage threshold through an N-bit binary number includes: inputting a clock signal to the control end of the first switch and the second switch, and controlling the NMOS tubes S1, S2, ... SN of the switch through an external register or an external calibration program, and adjusting the width and length of the NMOS group in the differential pair tube. The specific adjustment method is: inputting control signals C[0], C[1] ~ C[N-1] to the NMOS tubes S1, S2 ~ SN through an external register or an external calibration program, setting N to n, that is, controlling the NMOS tubes S1, S2 ~ Sn to be turned on, so that the NMOS tubes M6, M7 ~ M N+5 At this time, the width-to-length ratio of the first NMOS tube to the NMOS tube group is 1:n, so that the threshold of the comparator is adjusted to Vn.

[0016] A parallel analog-to-digital converter, comprising a plurality of comparators, wherein the comparators are threshold-adjustable comparators as described in claim 1 or 6, wherein the same-direction input terminals of the comparators are all connected to an input voltage Vin, wherein the reverse input terminals of the comparators are all connected to a fixed reference voltage Vref, and the output terminals of the comparators are all connected to an encoder, and the threshold value adjustment method of the comparator as described in claim 6 or 7 is used to adjust the threshold values ​​of the respective comparators in the parallel analog-to-digital converter, so that the threshold values ​​of the respective comparators finally determined are not equal, the comparator compares the input voltage Vin with the threshold value of the corresponding comparator, and outputs a comparison result, and the encoder encodes the comparison result and outputs the encoded conversion signal, wherein the conversion signal is the output signal of the parallel analog-to-digital converter.

[0017] Its further characteristic is that

[0018] The comparison result output by the comparator is represented by digital signals "0" and "1". The specific steps of applying the threshold adjustable comparator described in claim 1 or 6 to a parallel analog-to-digital converter include: A1, using the threshold adjustment method of the comparator described in claim 6 or 7 to adjust the threshold of each comparator in the parallel analog-to-digital converter, so that the threshold of each comparator meets the requirements of the parallel converter and is determined;

[0019] A2. Compare the input voltage Vin of the comparator with the threshold of the corresponding comparator. If the input voltage Vin is less than the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "1". Otherwise, if the input voltage Vin is greater than or equal to the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "0".

[0020] A3. Encode and output the digital signal through the encoder to achieve analog-to-digital conversion by a parallel analog-to-digital converter to obtain a converted digital signal.

[0021] The above structure and method of the present invention can achieve the following beneficial effects: the threshold of the comparator is mainly determined by the width-to-length ratio of the differential pair tubes inside it. Since the threshold adjustable comparator includes a differential pair tube with an adjustable width-to-length ratio, the flip threshold of the comparator can be determined by adjusting the width-to-length ratio N: (1~N) of the differential pair tubes, thereby meeting the threshold adjustment requirements of the comparator.

[0022] The present application applies a threshold adjustable comparator and a threshold adjustment method to a parallel analog-to-digital converter, so that the thresholds of the comparators of the parallel analog-to-digital converter are different. Since the input voltage of the reverse input terminal of the comparator is a fixed reference voltage, and the threshold voltage of the comparator is obtained by adjusting the width-to-length ratio of the differential pair tube, it is not necessary to set a resistor network to adjust the reverse input voltage to obtain the threshold voltage of the comparator, thereby avoiding the problem that the kickback noise interferes with the resistor network and affects the accuracy of the next conversion, and reducing the conversion error caused by the kickback noise of the comparator. In addition, the reduction of the resistor network reduces the power consumption generated by the resistor, thereby reducing the power consumption of the entire integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit structure of a parallel analog-to-digital converter based on a comparator with adjustable voltage threshold that is commonly used at present;

[0024] Figure 2 The circuit structure of the parallel analog-to-digital converter based on the voltage threshold adjustable comparator of the present application;

[0025] Figure 3 This is the circuit schematic diagram of the comparator of this application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above drawings are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0027] The parallel analog-to-digital converter is the main component of the CMOS integrated circuit. The parallel analog-to-digital converter includes a preamplifier, but the width-to-length ratio of the differential pair tube of the traditional preamplifier is 1:1, and the threshold voltage of the parallel comparator cannot be adjusted. Therefore, the resistor network must be set to adjust the reference voltage Vref so that the input voltage Vin at the positive input terminal of the comparator reaches the reference voltage Vref to meet the signal conversion requirements of the parallel analog-to-digital conversion.

[0028] Figure 1 A commonly used parallel analog-to-digital converter structure is provided, which includes a resistor network, a parallel comparator (i.e., a comparator array), a logic circuit, and an encoder. The reference power supply Vref is converted into a threshold voltage of the parallel comparator through the voltage-dividing effect of each resistor R in the resistor network. The comparator compares the input voltage Vin with the threshold voltage, and performs analog-to-digital conversion according to the comparison result, thereby realizing the signal conversion of the parallel analog-to-digital converter. However, when the parallel analog-to-digital converter converts the signal, a kickback effect is easily generated in the comparator, and the kickback noise generated by the kickback effect interferes with the resistor network. The resistor network is disturbed and generates current fluctuations, which affects the next conversion accuracy of the comparator. In addition, in the integrated circuit, the power consumption mainly comes from the resistor, and the resistor network is mainly composed of resistors. Therefore, the use of the resistor network increases the power consumption of the parallel analog-to-digital converter in the entire integrated circuit.

[0029] In view of the problem in the prior art that the kickback effect of the parallel comparator will interfere with the resistor network, thereby affecting the accuracy of the next conversion of the parallel analog-to-digital converter, and the problem that the use of the resistor network increases the power consumption of the entire parallel analog-to-digital converter, the present application provides a parallel analog-to-digital converter based on a voltage threshold adjustable comparator. Among them, the threshold adjustable comparator (reference Figure 2) includes a differential pair tube 1, a cross-structured latch unit 2, a first switch, a second switch, and a logic NAND gate circuit 3. The source of the differential pair tube 1 is connected to the drain of the latch unit, the gate, the drain of the second switch, and the input of the logic NAND gate circuit; the source of the latch unit 2 and the second switch is connected to the voltage source VDD, the drain of the differential pair tube 1 is connected to the source of the first switch, the gates of the first switch and the second switch are connected to the external input clock signal, and the output of the logic NAND gate circuit 3 is the output of the comparator; the gate of the differential pair tube 1 is the in-phase input terminal and the inverting input terminal of the comparator, the voltage of the in-phase input terminal is the input voltage Vin, and the voltage of the inverting input terminal is the reference voltage Vip; the control terminals of the first switch and the second switch input the clock signal CLK; the width-to-length ratio of the differential pair tube 1 is N:(1-N), where N is an integer. In this embodiment, the reference voltage Vip is a fixed reference voltage Vref, which is generated by a reference voltage chip or a reference voltage generating circuit, and the reference voltage generating circuit is a bandgap reference circuit.

[0030] In the comparator, the specific structure of the differential pair tube 1 is as follows: the differential pair tube 1 includes a first NMOS tube M5, an NMOS tube group M6 to M7 with adjustable width and length, N+5 , switches connected one-to-one with the NMOS tubes in the NMOS tube group, the gates of the NMOS tubes in the NMOS tube group are connected to the input voltage Vin, the sources of the NMOS tubes in the NMOS tube group and the source of the first NMOS tube are connected to the drain of the second switch, the drains of the NMOS tubes in the NMOS tube group are respectively connected to a switch, the switches are controlled by an external register or an external calibration program, and the width and length of the NMOS tube group are adjusted by the switches.

[0031] In order to meet the width and length adjustment requirements of the NMOS tube group, the switch of the present application adopts NMOS tubes S1, S2...SN, the drains of the NMOS tubes S1, S2...SN are all connected to the drain of the first switch, the gate and the drain of the latch unit, and the source of the NMOS tubes S1, S2...SN is connected to the drain of the first NMOS tubes M6~MN+5 in a one-to-one correspondence. N+5 The source of is connected to the drain of the second switch, and the control ends of the NMOS tubes S1, S2, ..., SN are connected to a register or controlled by an external calibration program.

[0032] In this embodiment, the cross-structure latch unit includes PMOS tubes M2 and M3, the first switch includes PMOS tubes M1 and M4, and the second switch is a PMOS tube M N+6The logic NAND gate circuit includes a first NAND gate ND1 and a second NAND gate ND2. The gate of the PMOS tube M2 is respectively connected to the drain of the PMOS tube M3, the input ends of the first NAND gates ND1 and ND2, the drains of the NMOS tubes S1, S2...SN, and the drain of the first NMOS tube M5. The sources of the PMOS tubes M1, M2, M3, and M4 are all connected to the voltage source VDD.

[0033] In practical applications, due to the nonlinearity of transistors, the value of N is much larger than the required binary accuracy. The threshold control of each comparator needs to be calibrated to achieve an equivalent binary threshold. The present application uses the above-mentioned differential pair tube structure and switch structure to adjust the threshold of the comparator, and the adjustment method is: input the input voltage Vin to the same-direction input terminal of the comparator, and input the reference voltage Vip to the reverse input terminal. The comparator flip voltage threshold is controlled by a set of N-bit binary numbers. The N-bit binary number control is achieved by adjusting the width-to-length ratio N of the differential pair tube in the comparator: (1~N), where N is an integer.

[0034] The specific steps of controlling the comparator flip voltage threshold through an N-bit binary number include: inputting a clock signal CLK to the control end of the first switch and the second switch, and controlling the NMOS tubes S1, S2, ... SN of the switch through an external register or an external calibration program (controlling the switch through an external register or an external calibration program belongs to conventional technology), adjusting the width and length of the NMOS group in the differential pair tube, specifically, inputting control signals C[0], C[1] to C[N-1] to the NMOS tubes S1, S2 to SN through an external register or an external calibration program, setting N to 1, that is, controlling the NMOS tube S1 to be turned on, so that the NMOS tube M6 is turned on. At this time, the width-to-length ratio of the first NMOS tube to the NMOS tube group is 1:1, so that the threshold of the comparator is adjusted to V1;

[0035] S2, input control signals C[0], C[1]~C[N-1] to NMOS tubes S1, S2~SN through an external register or an external calibration program, set N to 2, that is, control NMOS tubes S1 and S2 to be turned on, and make NMOS tubes M6 and M7 turned on. At this time, the width-to-length ratio of the first NMOS tube and the NMOS tube group is 1:2, so that the threshold of the comparator is adjusted to V2;

[0036] Similarly, control signals C[0], C[1]~C[N-1] are input to NMOS tubes S1, S2~SN through external registers or external calibration programs, and N is set to n, that is, NMOS tubes S1, S2~Sn are controlled to be turned on, so that NMOS tubes M6, M7~M N+5 At this time, the width-to-length ratio of the first NMOS tube and the NMOS tube group is 1:n, thereby adjusting the threshold of the comparator to Vn.

[0037] Compared with the traditional comparator, the width-to-length ratio of the differential pair tube in the comparator is no longer 1:1, but the ratio from the minimum 1:N to the maximum N:N can be programmably controlled automatically or controlled by the switch tube, that is, the width-to-length ratio of the differential pair tube is selected by the N-bit control line.

[0038] The above-mentioned threshold adjustable comparator is applied to a parallel analog-to-digital converter. If the number of bits of the parallel analog-to-digital converter is M, the M-bit parallel analog-to-digital converter includes at least M+1 threshold adjustable comparators working in parallel, the same-direction input ends of the threshold adjustable comparators are all connected to the input voltage Vin, the reverse input ends of the threshold adjustable comparators are all connected to the fixed reference voltage Vref, and the output ends of the threshold adjustable comparators are all connected to the encoder.

[0039] The comparator is used to adjust the threshold of each comparator in the parallel analog-to-digital converter so that the thresholds of each comparator are not equal. The comparator compares the input voltage Vin with the threshold of the corresponding comparator. The encoder encodes the comparison result and outputs the encoded conversion signal, which is the output signal of the parallel analog-to-digital converter. In this embodiment, the comparison result output by the comparator is represented by digital signals (or binary codes) "0" and "1".

[0040] The specific steps of applying the above-mentioned threshold adjustable comparator to a parallel analog-to-digital converter include: A1, using the threshold adjustment method of the comparator of claim 6 or 7 to adjust the threshold of each comparator in the parallel analog-to-digital converter to determine the threshold of each comparator. In this embodiment, the parallel analog-to-digital converter is a 2-bit parallel analog-to-digital converter (i.e., M=2), and is internally provided with 4 comparators working in parallel: a first comparator, a second comparator, a third comparator, and a fourth comparator. The specific steps of using the threshold adjustment method to adjust the threshold of each comparator in the parallel analog-to-digital converter include: A11, inputting control signals C1[0], C1[1]~C1[N-1] to NMOS tubes S1, S2~SN through an external register or an external calibration program, setting N to 1, that is, controlling the NMOS tube S1 to be turned on, so that the NMOS tube M6 is turned on. At this time, the width-to-length ratio of the first NMOS tube to the NMOS tube group is 1:1, thereby adjusting the threshold of the first comparator to V1;

[0041] A12, input control signals C2[0], C2[1]~C2[N-1] to NMOS tubes S1, S2~SN through an external register or an external calibration program, set N to 2, that is, control NMOS tubes S1 and S2 to be turned on, and make NMOS tubes M6 and M7 turned on. At this time, the width-to-length ratio of the first NMOS tube and the NMOS tube group is 1:2, so that the threshold of the second comparator is adjusted to V2;

[0042] Similarly, control signals C3[0], C3[1]~C3[N-1] or C4[0], C4[1]~C4[N-1] are input to NMOS tubes S1, S2~SN through an external register or an external calibration program to adjust the thresholds of the third comparator and the fourth comparator. The thresholds of the third comparator and the fourth comparator are adjusted to V3 and V4 respectively, thereby realizing the determination of the thresholds of each comparator in the parallel analog-to-digital converter. The thresholds of the first comparator, the second comparator, the third comparator and the fourth comparator are ultimately determined to be unequal, thereby ensuring that the parallel analog-to-digital converter can stably convert the value of the input voltage Vin.

[0043] A2. Compare the input voltage Vin of the comparator with the threshold of the corresponding comparator. If the input voltage Vin is less than the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "1". Otherwise, if the input voltage Vin is greater than or equal to the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "0".

[0044] A3. Encode and output the digital signal through an encoder to achieve analog-to-digital conversion of a parallel analog-to-digital converter to obtain a converted digital signal.

[0045] In the present application, it is assumed that when the outputs of the parallel comparators are all digital signals "1", the parallel analog-to-digital converter can achieve stable signal conversion. In the traditional comparator, when the width-to-length ratio of the first PMOS tube M1 and the second PMOS tube M2 is N:N, the input voltage Vin is greater than or equal to the reference voltage, and then the outputs of the parallel comparators can all be "1". The present application provides a method for adjusting the threshold voltage of the parallel comparator based on the above-mentioned adjustable threshold comparator and the above-mentioned adjustment method (i.e., calibrating each relatively strong threshold). After the threshold voltage is adjusted, when the width-to-length ratio of the first PMOS tube M1 and the second PMOS tube M2 is 1:N, a very small input signal can make the comparator array output all "1" to meet the conversion requirements of the parallel analog-to-digital converter. In summary, the parallel analog-to-digital converter based on the voltage threshold adjustable comparator of the present application has the following advantages:

[0046] (1) There is no need to set a resistor network to adjust the reference voltage of the comparator, the circuit structure is simple, and the power consumption is reduced.

[0047] (2) Each comparator controls the equivalent threshold voltage through the N-bit digital signal output by the preamplifier, thereby meeting the conversion requirements of the parallel analog-to-digital converter and realizing low-power parallel analog-to-digital conversion.

[0048] (3) It avoids the problem that the kick-back noise interferes with the resistor network and affects the accuracy of the next conversion.

[0049] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A threshold adjustable comparator, comprising a differential pair of transistors, a latch unit of a cross structure, a first switch, a second switch, and a logic NAND gate circuit, characterized in that: The source of the differential pair is connected to the drain, gate, drain of the second switch, and input of the logic NAND gate circuit of the latch unit; the source of the latch unit and the second switch is connected to the voltage source VDD, the drain of the differential pair is connected to the source of the first switch, the gates of the first switch and the second switch are connected to the external input clock signal, and the output of the logic NAND gate circuit is the output of the comparator; The gates of the differential pair are respectively the in-phase input terminal and the inverting input terminal of the comparator, the voltage of the in-phase input terminal is the input voltage Vin, and the voltage of the inverting input terminal is the reference voltage Vip; the control terminals of the first switch and the second switch input the clock signal CLK; the width-to-length ratio of the differential pair is adjustable between N:N and N:1, where N is an integer; The differential pair transistors include a first NMOS transistor M5, a width-length adjustable NMOS transistor group M6 to M7. N+5 , switches connected one-to-one with the NMOS tubes in the NMOS tube group, the gates of the NMOS tubes in the NMOS tube group are connected to the input voltage Vin, the sources of the NMOS tubes in the NMOS tube group and the source of the first NMOS tube are connected to the drain of the second switch, the drains of the NMOS tubes in the NMOS tube group are respectively connected to one of the switches, the switches are controlled by an external register or an external calibration program, and the width and length of the NMOS tube group are adjusted by the switches.

2. The threshold adjustable comparator according to claim 1, characterized in that: The switches are NMOS tubes S1, S2-SN, the drains of the NMOS tubes S1, S2-SN are connected to the drain of the first switch, the gate and the drain of the latch unit, and the sources of the NMOS tubes S1, S2-SN are connected to the first NMOS tubes M6-M7. N+5 The drains of the first NMOS tubes M6 to M N+5 The source of the transistor is connected to the drain of the second switch, and the control ends of the NMOS transistors S1, S2 to SN are connected to a register or controlled by an external calibration program.

3. The threshold adjustable comparator according to claim 2, characterized in that: The reference voltage Vip is a fixed reference voltage Vref, and the fixed reference voltage Vref is generated by a reference voltage chip or a reference voltage generating circuit, and the reference voltage generating circuit is a bandgap reference circuit.

4. The threshold adjustable comparator according to claim 3, characterized in that: The cross-structure latch unit includes PMOS tubes M2 and M3, the first switch includes PMOS tubes M1 and M4, and the second switch includes PMOS tube M N+6 The logic NAND gate circuit includes a first NAND gate ND1 and a second NAND gate ND2. The gate of the PMOS tube M2 is respectively connected to the drain of the PMOS tube M3, the input ends of the first NAND gates ND1 and ND2, the drains of the NMOS tubes S1, S2...SN, and the drain of the first NMOS tube M5. The sources of the PMOS tubes M1, M2, M3, and M4 are all connected to the voltage source VDD.

5. A comparator threshold adjustment method, using the threshold adjustable comparator according to any one of claims 1 to 4, characterized in that: An input voltage Vin is input to the same-direction input terminal of the comparator, and a reference voltage Vip is input to the reverse input terminal. The comparator flip voltage threshold is controlled by a set of N-bit binary numbers. The N-bit binary number control is achieved by adjusting the width-to-length ratio of the differential pair tubes in the comparator between N:N and N:1, where N is an integer.

6. The comparator threshold adjustment method according to claim 5, characterized in that: The specific steps of controlling the comparator flip voltage threshold by an N-bit binary number include: inputting a clock signal to the control end of the first switch and the second switch, and controlling the NMOS tubes S1, S2, ... SN of the switch by an external register or an external calibration program, and adjusting the width and length of the NMOS group in the differential pair tube. The specific adjustment method is: inputting control signals C[0], C[1] ~ C[N-1] to the NMOS tubes S1, S2 ~ SN by an external register or an external calibration program, setting N to n, that is, controlling the NMOS tubes S1, S2 ~ Sn to be turned on, so that the NMOS tubes M6, M7 ~ M N+5 At this time, the width-to-length ratio of the first NMOS tube to the NMOS tube group is 1:n, thereby adjusting the threshold of the comparator to Vn.

7. A parallel analog-to-digital converter, comprising a plurality of comparators, wherein the comparators are the threshold adjustable comparators according to claim 1 or 5, wherein the same-direction input terminals of the comparators are connected to an input voltage Vin, and wherein: The reverse input terminals of the comparators are all connected to a fixed reference voltage Vref, and the output terminals of the comparators are all connected to an encoder. The threshold value adjustment method of the comparator described in claim 5 or 6 is used to adjust the threshold values ​​of the respective comparators in the parallel analog-to-digital converter, so that the threshold values ​​of the respective comparators finally determined are not equal. The comparator compares the input voltage Vin with the threshold value of the corresponding comparator and outputs a comparison result. The encoder encodes the comparison result and outputs the encoded conversion signal, and the conversion signal is the output signal of the parallel analog-to-digital converter.

8. The parallel analog-to-digital converter according to claim 7, characterized in that: The comparison result output by the comparator is represented by digital signals "0" and "1". The specific steps of applying the threshold adjustable comparator described in claim 1 or 5 to a parallel analog-to-digital converter include: A1, using the threshold adjustment method of the comparator described in claim 5 or 6 to adjust the threshold of each comparator in the parallel analog-to-digital converter, so that the threshold of each comparator meets the requirements of the parallel converter and is determined; A2. Compare the input voltage Vin of the comparator with the threshold of the corresponding comparator. If the input voltage Vin is less than the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "1". Otherwise, if the input voltage Vin is greater than or equal to the threshold of the corresponding comparator, the corresponding comparator outputs a digital signal "0". A3. Encode and output the digital signal through the encoder to achieve analog-to-digital conversion by a parallel analog-to-digital converter to obtain a converted digital signal.

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