Ferroelectric device with multiple polarization states and method of manufacturing the same

Abstract

A ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric between the channel region and the gate electrode and including a plurality of ferroelectric gate dielectric portions having different structural defect densities.

Description

[0001] Related applications

[0002] This patent application claims priority to U.S. Continuation Part Int. (CIP) Patent Application Serial No. 16 / 778,245, filed January 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of semiconductor devices, and more particularly to ferroelectric devices comprising ferroelectric layers having multiple polarization states and methods for manufacturing the same. Background Technology

[0004] Ferroelectric memory devices are memory devices containing ferroelectric material for storing information. The ferroelectric material acts as the memory material in the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed with two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the crystal lattice, such as oxygen and / or metal atom positions) to store information in the ferroelectric material. The different orientations of the dipole moments of the ferroelectric material can be detected by the electric field generated by the dipole moments. For example, the orientation of the dipole moments can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in a proximity field-effect transistor ferroelectric memory device. Summary of the Invention

[0005] According to one aspect of this disclosure, a ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric, the ferroelectric gate dielectric being located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions with different structural defect densities.

[0006] According to another aspect of this disclosure, a ferroelectric device includes a two-dimensional metal dichalcogenide semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric, the ferroelectric gate dielectric being adjacent to the channel region and including a plurality of different ferroelectric gate dielectric portions.

[0007] According to another aspect of this disclosure, a method of forming a ferroelectric device includes: forming a source region and a drain region laterally spaced apart from each other through a channel region; forming a ferroelectric gate dielectric over the channel region; forming different structural defects in the ferroelectric gate dielectric, wherein a plurality of ferroelectric gate dielectric portions have different structural defect densities; and forming a gate electrode over each of the plurality of ferroelectric gate dielectric portions. Attached Figure Description

[0008] Figure 1 It is a perspective view of a metal-ferroelectric semiconductor structure.

[0009] Figure 2A yes Figure 1 Potential diagram of the first polarization state of the metal-ferroelectric semiconductor structure.

[0010] Figure 2B yes Figure 1 Potential diagram of the second polarization state of the metal-ferroelectric semiconductor structure.

[0011] Figure 3 This is a graph showing the electrostatic potential at the interface between the ferroelectric material portion and the metal portion as a function of the ferroelectric thickness of the metal-ferroelectric semiconductor structure with two selected ferroelectric polarization densities.

[0012] Figure 4 It is a graph showing the conductivity as a function of the Fermi level of a two-dimensional general-purpose semiconductor material.

[0013] Figure 5 This is a graph showing the density of per atom per electron volt of pristine graphene and fluorinated graphene calculated within a tight-binding model.

[0014] Figure 6 This is a graph showing how electrical conductivity varies with the Fermi level of pristine graphene and fluorinated graphene calculated within the tight-binding model.

[0015] Figure 7 This is a first exemplary structure according to a first embodiment of the present disclosure.

[0016] Figure 8 This is a second exemplary structure according to a second embodiment of the present disclosure.

[0017] Figure 9 This is a third exemplary structure according to a third embodiment of the present disclosure.

[0018] Figure 10A This is a vertical cross-sectional view of a fourth exemplary structure according to a fourth embodiment of the present disclosure.

[0019] Figure 10B yes Figure 10A A schematic perspective view of the fourth exemplary structure.

[0020] Figure 11 The calculated density per atom per electron volt of hexagonal boron nitride is shown based on density function theory (DFT) and hybridization function.

[0021] Figure 12 The calculated density of molybdenum disulfide per atom per electron volt state is shown based on density function theory (DFT) and hybridization function.

[0022] Figure 13A This is a graph showing how the conductivity of hexagonal boron nitride varies with polarization calculated within the tight-binding model.

[0023] Figure 13B This is a graph showing how the electrical conductivity of fluorinated graphene changes with polarization calculated within the tight-binding model.

[0024] Figure 13C This is a graph showing how the conductivity of molybdenum disulfide varies with polarization calculated within a tight-binding model.

[0025] Figure 13D This is a graph showing how the conductivity of germane changes with polarization calculated within the tight-binding model.

[0026] Figure 14 This is a schematic diagram of a ferroelectric memory device according to an embodiment of the present disclosure.

[0027] Figure 15A This is a top-down view of a fifth exemplary structure after the formation of a shallow trench isolation structure, according to a fifth embodiment of this disclosure.

[0028] Figure 15B It is along Figure 15A A vertical cross-sectional view of the vertical plane B-B'.

[0029] Figure 16A This is a top-down view of a fifth exemplary structure after the formation of the ferroelectric gate dielectric layer, according to a fifth embodiment of the present disclosure.

[0030] Figure 16B It is along Figure 16A A vertical cross-sectional view of the vertical plane B-B'.

[0031] Figure 17A This is a top-down view of a fifth exemplary structure following a first masked ion implantation process, according to a fifth embodiment of this disclosure.

[0032] Figure 17B It is along Figure 17A A vertical cross-sectional view of the vertical plane B-B'.

[0033] Figure 18A This is a top-down view of a fifth exemplary structure following a second masked ion implantation process, according to a fifth embodiment of this disclosure.

[0034] Figure 18B It is along Figure 18A A vertical cross-sectional view of the vertical plane B-B'.

[0035] Figure 19A This is a top-down view of a fifth exemplary structure following a third masked ion implantation process, according to a fifth embodiment of this disclosure.

[0036] Figure 19B It is along Figure 19A A vertical cross-sectional view of the vertical plane B-B'.

[0037] Figures 20A to 20D These are hysteresis curves of various ferroelectric gate dielectric portions of a fifth exemplary structure of a ferroelectric gate dielectric according to a fifth embodiment of the present disclosure.

[0038] Figure 21A This is a top-down view of a fifth exemplary structure after the formation of the gate stack structure and the extension of the active region, according to a fifth embodiment of the present disclosure.

[0039] Figure 21B It is along Figure 21A A vertical cross-sectional view of the vertical plane B-B'.

[0040] Figure 22A This is a top-down view of a fifth exemplary structure after the formation of the gate spacer and deep active region, according to a fifth embodiment of the present disclosure.

[0041] Figure 22B It is along Figure 22A A vertical cross-sectional view of the vertical plane B-B'.

[0042] Figure 23A This is a top-down view of a fifth exemplary structure after the formation of the contact-level dielectric layer and the contact via structure, according to a fifth embodiment of this disclosure.

[0043] Figure 23B It is along Figure 23A A vertical cross-sectional view of the vertical plane B-B'.

[0044] Figure 24 It is the channel conductivity of the field-effect transistor in a fifth exemplary structure that varies with gate voltage according to a fifth embodiment of the present disclosure.

[0045] Figure 25 It is an interconnection network of ferroelectric memory devices connected in a synaptic connection structure according to the fifth embodiment of this disclosure. Detailed Implementation

[0046] As discussed above, embodiments of this disclosure relate to a ferroelectric device comprising a ferroelectric gate dielectric having multiple regions with different polarization states due to varying densities of structural defects in each region. The multiple regions of the ferroelectric gate dielectric are located between a common gate and a common channel, such that the multiple different polarization states provide multiple non-volatile conductive states for the channel. If the device is a memory device, then the ferroelectric gate dielectric is a memory layer having multiple polarization states, providing memory cells with more than one bit per cell (i.e., multi-level data storage). The multiple non-volatile conductive states can be precisely controlled by varying the magnitude of the applied gate voltage (e.g., the magnitude of a voltage pulse applied to the gate). If the device is a logic or sensor device, then the ferroelectric gate dielectric acts as the gate insulating layer of a transistor having multiple conductive states in adjacent regions of the same channel.

[0047] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. The same reference numerals refer to the same or similar elements. Unless otherwise explicitly stated, elements having the same reference numerals are assumed to have the same material composition. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, then the first element is positioned “directly” on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, then the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0048] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the first continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, or may have one or more layers on, above, and / or below it. As used herein, a “layer stack” refers to a stack of layers. As used herein, a “line” or “line structure” refers to a layer having a primary direction of extension, i.e., the direction in which said layer extends the most.

[0049] As used herein, a "field-effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows at a current density modulated by an external electric field. As used herein, an "active region" refers to the source region or drain region of a field-effect transistor. A "top active region" refers to the active region of a field-effect transistor located above another active region of the field-effect transistor. A "bottom active region" refers to the active region of a field-effect transistor located below another active region of the field-effect transistor.

[0050] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -6 S / m to 1.0×10 5 Materials with electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants of 1.0 × 10⁻⁶ S / m. -6 Materials with electrical conductivity ranging from S / m to 1.0 S / m can be produced by appropriate doping with electrodopersive agents, exhibiting conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 5 Doped materials with conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -6 Materials with an electrical conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶ S / m). 5 Semiconductor materials with a conductivity of S / cm. "Doped semiconductor materials" can be heavily doped semiconductor materials, or materials containing a conductivity of 1.0 × 10⁻⁶ S / cm.-6 S / m to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the conductivity range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopant. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material containing at least one metallic element. All conductivity measurements were performed under standard conditions. As used herein, "ferroelectric material" refers to any material exhibiting spontaneous polarization that can be reversed by the application of an external electric field.

[0051] refer to Figure 1 This illustrates a metal-ferroelectric-semiconductor structure according to an embodiment of the present disclosure. In the ferroelectric memory device described below, the metal-ferroelectric-semiconductor structure includes: a metal portion comprising a gate electrode 50, a ferroelectric material portion comprising a gate dielectric / ferroelectric memory element 20, and a semiconductor portion comprising a semiconductor channel 40.

[0052] refer to Figure 2A and Figure 2B , showing Figure 1 Potential diagram of polarization states of a metal-ferroelectric-semiconductor structure. Figure 2A Show Figure 1 The first polarization state of the metal-ferroelectric-semiconductor structure is described, wherein the ferroelectric polarization vector P points in a positive polarization direction from the metal portion (such as gate electrode 50) to the semiconductor portion (such as semiconductor channel 40). In this case, positive ferroelectric charges exist on the side of the ferroelectric material portion (such as gate dielectric 20) at the interface with the semiconductor portion (such as semiconductor channel 40), and negative ferroelectric charges exist on the side of the ferroelectric material portion (such as gate dielectric 20) at the interface with the metal portion (such as gate electrode 50). The ferroelectric charges induce screening charges within the metal portion and the semiconductor portion. Screening charges are mobile charges (such as electrons or holes) that reduce the electric field caused by the ferroelectric charges within the ferroelectric material portion. Positive screening charges accumulate within the metal portion (such as gate electrode 50), and negative screening charges accumulate within the semiconductor portion (such as semiconductor channel 40).

[0053] Figure 2B Show Figure 1The second polarization state of the metal-ferroelectric-semiconductor structure is described, where the ferroelectric polarization vector P points in a direction from the semiconductor portion (such as the semiconductor channel 40) to the metal portion (such as the gate electrode 50). In this case, negative ferroelectric charges exist on the side of the ferroelectric material portion (such as the gate dielectric 20) at the interface with the semiconductor portion (such as the semiconductor channel 40), and positive ferroelectric charges exist on the side of the ferroelectric material portion (such as the gate dielectric 20) at the interface with the metal portion (such as the gate electrode 50). The ferroelectric charges induce screening charges within the metal portion and the semiconductor portion. Negative screening charges accumulate within the metal portion (such as the gate electrode 50), and positive screening charges accumulate within the semiconductor portion (such as the semiconductor channel 40).

[0054] The screening potential at the interface between the ferroelectric material and the metallic part can be controlled by switching the polarization direction of the ferroelectric material part. The electrostatic potential V varies with the distance x from the interface between the metallic and ferroelectric material parts. c (x) decays with a characteristic decay distance, referred to as the Thomas-Fermi sieve length. If the x-axis is chosen such that the x-coordinate is positive within the ferroelectric material portion with thickness d and within the semiconductor material portion, then the electrostatic potential V in the metallic and semiconductor material portions is... c (x) is governed by the following equation:

[0055]

[0056] Where λ is the Thomas-Fermi sieve length within the corresponding material portion.

[0057] When the metal portion (such as the gate electrode 50) is much thicker than the screening length li of the metal portion, and if the semiconductor material portion (such as the semiconductor channel 40) is thinner, then the electrostatic potential V of the semiconductor material portion... c The solution to (x) (i.e., x>d) is given as follows:

[0058]

[0059] Where d is the thickness of the ferroelectric material portion, P is the ferroelectric polarization of the ferroelectric material portion, and therefore the permittivity of vacuum, e is the relative permittivity of the ferroelectric material portion (i.e., the ratio of the permittivity of the ferroelectric material portion to the permittivity of vacuum), and λ l It is the Thomas-Fermi sieve length of the metallic portion, λ r λ' is the Thomas-Fermi sieve length of the semiconductor material portion, / is the thickness of the semiconductor material portion, and λ' l Given from the following:

[0060]

[0061] According to one aspect of this disclosure, the electrostatic potential in the interface region of the semiconductor material portion near the ferroelectric material portion can be controlled by reversing the ferroelectric polarization within the ferroelectric material portion. For Figure 2A The positive polarization direction shown indicates that the selected charge brings the Fermi level into the conduction band of the semiconductor material. For Figure 2B As shown, the negative polarization direction filters the charge, causing the Fermi level to shift toward the band gap. Therefore, by reversing the ferroelectric polarization direction, the Fermi level moves between its position in the semiconductor band gap and its position in one of the bands (e.g., the conduction band or valence band), resulting in a significant difference between the resistive (e.g., resistivity or resistance) states of the device.

[0062] According to one aspect of this disclosure, the semiconductor material portion comprises a two-dimensional semiconductor material that provides high electrical conductivity in a two-dimensional plane parallel to the interface between the semiconductor material portion and the ferroelectric material portion. As used herein, a two-dimensional semiconductor material refers to a semiconductor material with a thickness of 1 to 5 monolayers, such as 2 to 3 monolayers of atoms of a semiconductor material, and / or the semiconductor material comprises a two-dimensional charge carrier gas, such as a two-dimensional electron gas. In one embodiment, the two-dimensional semiconductor material has a lateral extent of quantum mechanical modification of induced band structure along one direction. In one embodiment, the two-dimensional semiconductor material may have a lateral direction of less than 10 nm along one direction, which is referred to herein as the thickness direction of the two-dimensional semiconductor material.

[0063] According to one aspect of this disclosure, the semiconductor material portion includes a two-dimensional semiconductor material layer having a thickness of 1 to 5 monolayers and a band gap of at least 1 eV, such as at least 1.15 eV, for example, a band gap of 1.15 eV to 5.65 eV. Alternatively, the two-dimensional semiconductor material layer may include a two-dimensional charge carrier gas layer (such as a two-dimensional electron gas) and a band gap of at least 1 eV, such as at least 1.15 eV, for example, a band gap of 1.15 eV to 5.65 eV. As used herein, a two-dimensional charge carrier gas refers to a collection of charge carriers in a quantum confinement that provides enhanced conductivity in a direction perpendicular to the direction of the quantum confinement. For example, a two-dimensional electron gas is a two-dimensional charge carrier gas. In one embodiment, the semiconductor material portion comprises a two-dimensional semiconductor material selected from hexagonal boron nitride having a band gap of 5.62 eV, fluorinated graphene having a band gap of 2.93 eV, molybdenum disulfide having a band gap of 2.24 eV, and germane having a band gap of 1.16 eV. The list of possible candidates for the two-dimensional semiconductor material is not limited to the aforementioned materials.

[0064] Figure 3V is the electrostatic potential at the interface between the ferroelectric material part and the metal part. c (0) Calculated within the Thomas-Fermi model Figure 1 The graph shows the variation of the ferroelectric thickness *d* in a metal-ferroelectric-semiconductor structure. Based on this model, the electrostatic potential *V* at the interface between the ferroelectric and semiconductor portions is... c (0) is given by the following:

[0065]

[0066] The first curve 310 corresponds to a ferroelectric polarization of 20 μC / cm. 2 In this case, the relative permittivity of the ferroelectric material portion is 90, the Thomas-Fermi sieve length of the metallic portion is 0.2 nm, and the Thomas-Fermi sieve length of the semiconductor material portion is also 0.2 nm. The second curve 320 corresponds to a ferroelectric polarization of 40 μC / cm. 2 In this case, the relative permittivity of the ferroelectric material portion is 90, the Thomas-Fermi sieve length of the metallic portion is 0.2 nm, and the Thomas-Fermi sieve length of the semiconductor material portion is also 0.2 nm. An electrostatic potential greater than 1.0 V and / or greater than 1.5 V and / or greater than 2.0 V can be generated at the interface between the ferroelectric material portion and the metallic portion through the ferroelectric polarization effect.

[0067] Figure 4 This is a graph showing the conductivity as a function of the Fermi level of a hypothetical two-dimensional semiconductor material (e.g., for a single layer of semiconductor material). Because... Figure 4 The calculations employed a simple model based on a two-dimensional semiconductor material with a tightly bonded dual-band Hamiltonian structure. This two-dimensional semiconductor material was then used in… Figure 1 When the semiconductor material portion of a device is used, it is possible to switch the state of the two-dimensional semiconductor material between a conductive and insulating state by reversing the direction of ferroelectric polarization, such as... Figure 2A and Figure 2B As shown in the diagram. In other words, Figure 1 The shift of the Fermi level in a device can be sufficient to provide two different resistance states, such as a higher resistance state and a lower resistance state, which can be, for example, a conductive state and an insulating state.

[0068] According to the embodiments of this disclosure, conductivity is related to Figure 4 The functional dependence of the Fermi level shown can be physically represented by any suitable two-dimensional semiconductor material, such as hexagonal boron nitride, fluorinated graphene, molybdenum disulfide, germane, etc.

[0069] Table 1 below shows the calculated band gap and conduction band in-situ energy for various materials that can be used in the ferroelectric memory devices of this disclosure. The band gap value is calculated from the first-principles electronic structure based on hybridization functions, and the in-situ energy is fitted tightly to reproduce the calculated band structure.

[0070] Table 1: Bandgap and conduction band in-situ energy of two-dimensional semiconductor materials

[0071] -Two-dimensional semiconductor materials Band gap (eV) Conduction band potential energy (eV) Hexagonal BN 5.62 6.81 <![CDATA[MoS2]]> 2.24 5.12 Fluorinated graphene 2.93 5.465 germane 1.16 4.58

[0072] A list of other suitable highly stable two-dimensional semiconductor materials, taken from the following database (https: / / cmrdb.fysik.dtu.dk / c2db / ?x=29127&limit=200), and their band gaps calculated in the DFT are shown in Table 2. It is known that the DFT underestimates the band gap value, therefore the actual band gap is expected to be larger.

[0073] Table 2: Bandgap of Additional Two-Dimensional Semiconductor Materials

[0074]

[0075]

[0076]

[0077]

[0078] Primitive graphene (i.e., graphene without defects or dopants) is an electrical conductor lacking a band gap, while fluorinated graphene is a semiconductor with a band gap. Figure 5 This is a graph showing the density of states per carbon atom per electron volt for pristine graphene and fluorinated graphene. A close-binding model is used for calculating the density per energy state. Curve 510 represents the density of states per carbon atom per electron volt for pristine graphene. Curve 520 represents the density of states per carbon atom per electron volt for fluorinated graphene. Pristine graphene provides a non-zero density of states at all energies except zero, and therefore does not provide the voltage at which pristine graphene becomes an insulator. Fluorinated graphene provides an energy band with a zero density of states, and therefore provides the voltage range for fluorinated graphene to act as an insulator.

[0079] refer to Figure 6 The calculated electrical conductivity of pristine graphene and fluorinated graphene was plotted as a function of Fermi energy. Curve 610 represents the conductivity of pristine graphene, and curve 620 represents the conductivity of fluorinated graphene. Fluorinated graphene provides an energy range in which conductivity is negligible, and it acts as an insulating material for Fermi levels of 0.5 eV or lower. In contrast, pristine graphene does not provide an energy range in which it can act as an insulating material.

[0080] The atomic percentage of fluorine in fluorinated graphene can range from 0.1% to 60%, such as 0.5% to 50%, including a range of 0.1% to 0%. Therefore, fluorinated graphene can contain, but is not limited to, fluorinated graphene with a carbon-to-fluorine ratio of approximately 1:1. The position and width of the zero-density band in fluorinated graphene vary with the atomic concentration of fluorine atoms within the fluorinated graphene. Therefore, in Figure 1 Switching between insulating and conductive states within the device is possible for fluorinated graphene semiconductor materials, which serve as the semiconductor component. Other semiconductor materials with sufficient band gaps (such as molybdenum disulfide, hexagonal boron nitride, or germane) can be used instead. Figure 1 Fluorinated graphene in devices.

[0081] Figure 7 A first exemplary structure 180 according to a first embodiment of the present disclosure is shown. The first ferroelectric memory device 180 includes a transistor 95 comprising a semiconductor channel 40. The semiconductor channel 40 may be configured to provide a two-dimensional charge carrier layer (such as a 2DEG layer) or a semiconductor material selected from fluorinated graphene, hexagonal boron nitride, molybdenum disulfide, germane, or similar two-dimensional materials having a sufficient band gap. The semiconductor channel 40 may consist only of the two-dimensional charge carrier layer, or the semiconductor channel may also include additional semiconductor material in addition to the two-dimensional charge carrier layer. The two-dimensional charge carrier layer may be located in a two-dimensional Euclidean plane. In one embodiment, the semiconductor channel 40 may have a thickness in the range of 0.3 nm to 10 nm, such as in the range of 0.6 nm to 5 nm. The two-dimensional charge carrier layer serves as a channel within the transistor 95 (e.g., a ferroelectric memory cell) of the first ferroelectric memory device 180.

[0082] Ferroelectric memory element 21 is positioned adjacent to semiconductor channel 40, such as on the surface of semiconductor channel (i.e., on the surface of the two-dimensional charge carrier layer). Ferroelectric memory element 21 serves as the gate dielectric 20 within transistor 95 of the first ferroelectric memory device 180. Ferroelectric memory element 21 is in contact with a first surface of semiconductor channel 40. Ferroelectric memory element 21 comprises and / or is substantially composed of at least one ferroelectric material, such as barium titanate (e.g., BaTiO3; BT), calcium staborite (e.g., Ca2B6O3), etc. 11 ·5H2O), bismuth titanate (such as Bi 12 TiO 20 Bi4Ti3O 12 Or Bi2Ti2O7), barium europium titanate, ferroelectric polymers, germanium telluride, anhydrous potassium magnesium vanadium (such as M2M'2(SO4)3, where M is a monovalent metal and M' is a divalent metal), lead scandium tantalum (such as Pb(Sc)x Ta 1-x) O3), lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN), (LaAlO3)), polyvinylidene fluoride (CH2CF2). n Potassium niobate (such as KNbO3), sodium tartrate (such as KNaC4H4O6·4H2O), potassium oxytitanium phosphate (such as KO5PTi), sodium bismuth titanate (such as Na 0.5 Bi 0.5 TiO3 or Bi 0.5 Na 0.5 TiO3), lithium tantalate (such as LiTaO3(LT)), lead lanthanum titanate (such as (Pb,La)TiO3(PLT)), lead lanthanum zirconium titanate (such as (Pb,La)(Zr,Ti)O3(PLZT)), ammonium dihydrogen phosphate (such as NH4H2PO4(ADP)), or potassium dihydrogen phosphate (such as KH2PO4(KDP)). In one embodiment, the ferroelectric memory element 21 comprises and / or is substantially composed of a ferroelectric dielectric material.

[0083] A front-side conductive gate electrode 51 is located directly on the ferroelectric memory element 21 on the opposite side of the semiconductor channel 40. The front-side conductive gate electrode 51 serves as the gate electrode 50 of the transistor 95 of the first ferroelectric memory device 180. The conductive gate electrode 51 is in contact with the ferroelectric memory element 21. The conductive gate electrode 51 may comprise a metallic material and / or be substantially composed of a metallic material, such as an elemental metal (Ti, Ta, or W), an intermetallic alloy of at least two elemental metals, a metal semiconductor compound (such as a metal silicide), or a conductive metal alloy of at least one elemental metal (such as Ti, Ta, or W) and a nonmetallic element (such as nitrogen and / or oxygen, such as TiN or WN).

[0084] Source contact 42 contacts a first portion of semiconductor channel 40, and drain contact 44 contacts a second portion of semiconductor channel. Ferroelectric memory element 21 is located between source contact 42 and drain contact 44. Source contact 42 and drain contact 44 may comprise and / or be substantially composed of corresponding metal contact materials. The metal contact material may be a metal semiconductor compound, a conductive metal nitride, an elemental metal, or an intermetallic alloy. In one embodiment, the metal material that can be used for the conductive gate electrode 51 may also be used for source contact 42 and drain contact 44.

[0085] In one embodiment, the two-dimensional charge carrier layer is located within 10 nm of the two-dimensional Euclidean plane, which is included at the interface between the semiconductor channel 40 and the ferroelectric memory element 21.

[0086] For example, a transistor 95 of the first exemplary structure 180 can be formed by forming a semiconductor channel 40 above a substrate 10, forming a ferroelectric memory element 21 directly on a first surface of the semiconductor channel 40, forming a conductive gate electrode 51 on the ferroelectric memory element 21, forming a source contact 42 on a first portion of the semiconductor channel 40, and forming a drain contact 44 on a second portion of the semiconductor channel 40. The substrate 10 has a planar top surface 11 that contacts the bottom surface of the semiconductor channel 40. Figure 7 In the embodiment shown, the direction between the semiconductor channel 40 and the conductive gate electrode 51 is perpendicular to the planar top surface 11 of the substrate 10. Alternatively, in Figure 8 In the implementation shown, transistor 95 can be relative to Figure 7 The transistor 95 shown is rotated 90 degrees so that the orientation between the semiconductor channel 40 and the conductive gate electrode 51 is parallel to the plane of the planar top surface 11 of the substrate 10. The substrate 10 may include any suitable support substrate, such as a semiconductor wafer, an insulating substrate, or a conductive substrate having an insulating layer above its planar top surface 11.

[0087] During programming, a variable gate bias voltage V can be applied relative to the semiconductor channel 40. g A polarization of the ferroelectric memory element 21 is programmed by applying a conductive gate electrode 51. During sensing, a source-drain bias voltage is applied between the source contact 42 and the drain contact 44 (e.g., across the source and drain contacts) and by applying a gate sensing bias voltage to the conductive gate electrode 51. The sensing circuitry 584 measures the source-drain current while applying the source-drain bias voltage between the source contact 42 and the drain contact 44 (e.g., across the source and drain contacts).

[0088] refer to Figure 8 According to the second exemplary structure 180 of the second embodiment of this disclosure, it can be provided by Figure 7 The first exemplary structure 180 is derived by providing a back-side ferroelectric memory element 22 in contact with a second surface of the semiconductor channel 40. The back-side ferroelectric memory element 22 is an additional ferroelectric material portion that serves as an additional gate dielectric 20. The back-side ferroelectric memory element 22 is located on the second surface of the semiconductor channel 40, which is parallel to and on the opposite side of the first surface of the semiconductor channel 40. The back-side ferroelectric memory element 22 may have the same thickness as the ferroelectric memory element 21 and may contain any ferroelectric material that can be used in the ferroelectric memory element 21.

[0089] A conductive back-side gate electrode 52 is disposed on the back-side ferroelectric memory element 22. The conductive back-side gate electrode 52 may contact the back-side ferroelectric memory element 22. The conductive back-side gate dielectric 52 may contain any material suitable for use with the conductive gate electrode 51. A conductive path connects the conductive back-side gate electrode and the conductive gate electrode, thereby electrically shorting the conductive back-side gate electrode 52 to the conductive gate electrode 51.

[0090] In one embodiment, the polarization of the ferroelectric memory element 21 and the polarization of the back-side ferroelectric memory element 22 can point in opposite directions. Therefore, the polarization of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 can point towards the semiconductor channel 40 in a first ferroelectric memory state, and the polarization of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 can point away from the semiconductor channel 40 in a second ferroelectric memory state. Thus, positive iron charge exists in the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 near the interface with the semiconductor channel 40 in the first ferroelectric memory state, which includes negative screening charge (moving electrons) in a two-dimensional charge carrier layer near the interface with the ferroelectric memory element 21 and the back-side ferroelectric memory element 22. Alternatively, if a semiconductor layer is used instead of the two-dimensional charge carrier layer, then induced charge will be used to deflect the Fermi energy and change the conductivity state of the semiconductor layer. Similarly, negative ferroelectric charges exist in the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 near the interface with the semiconductor channel 40 in the second ferroelectric memory state, which includes positive screening charges (holes, i.e., the absence of electrons) in a two-dimensional charge carrier layer near the interface with the ferroelectric memory element 21 and the back-side ferroelectric memory element 22. When a voltage is applied to the front-side conductive gate electrode 51, the second exemplary structure 180 can be operated by applying the same voltage (e.g., a voltage pulse of the same polarity) to the conductive back-side gate electrode 52.

[0091] The thickness of the semiconductor channel 40 in the second exemplary structure 180 may be the same as the thickness of the semiconductor channel in the first exemplary structure 180. Alternatively, the thickness of the semiconductor channel 40 in the second exemplary structure 180 may be in the range of 1.0 times to 2.0 times the thickness of the semiconductor channel 40 in the first exemplary structure 180. The increased thickness window of the semiconductor channel 40 in the second exemplary structure 180 is due to the dual-gate construction, in which screening charges are induced in an additive manner by two different ferroelectric polarizations.

[0092] The transistor 95 of the second exemplary structure 180 can be formed by modifying the method used to form the transistor 95 of the first exemplary structure 180. In addition to the processing steps for forming the various components of the first exemplary structure 180, the back-side ferroelectric memory element 22 can also be formed on the second surface of the semiconductor channel 40, and the conductive back-side gate electrode 52 can be formed on the back-side ferroelectric memory element 22.

[0093] In one embodiment, the transistor 95 of the second exemplary structure 180 may be supported by a substrate 10 having a planar top surface 11 that is perpendicular to the plane of the interface between the semiconductor channel 40 and the ferroelectric memory element 21 and parallel to the direction of the current in the semiconductor channel 40 (i.e., the direction between the source contact 42 and the drain contact 44) during sensing operation.

[0094] Alternatively, Figure 8 The transistor 95 shown can be rotated 90 degrees to have the same characteristics as... Figure 7 The structure is similar to that shown in the diagram. In this alternative structure, a conductive back-side gate electrode 52 is formed above the substrate 10, a back-side ferroelectric memory element 22 is formed above the conductive back-side gate electrode 52, a semiconductor channel 40 is formed above the back-side ferroelectric memory element 22, a ferroelectric memory element 21, a source contact 42, and a drain contact 44 are formed above the semiconductor channel 40, and a front-side conductive gate electrode 51 is formed above the ferroelectric memory element 21.

[0095] refer to Figure 9 The image shows a transistor 95 with a third exemplary structure according to an embodiment of the present disclosure, which may be derived from a first exemplary structure 180 by forming a back-side contact electrode 53 directly on the second surface of a semiconductor channel 40. A two-dimensional semiconductor material layer 40G within the semiconductor channel 40 is explicitly shown. The two-dimensional semiconductor material layer 40G described above may include the entire semiconductor channel 40 or only a portion of the semiconductor channel 40. The two-dimensional semiconductor material layer 40G may have a band gap of at least 1.1 eV, may include a thickness of 1 to 5 monolayers of semiconductor material, and / or may include a two-dimensional charge carrier layer. The second surface of the semiconductor channel 40 is located on the opposite side of the first surface of the semiconductor channel 40. Therefore, the back-side contact electrode 53 may contact the second surface of the semiconductor channel 40. The back-side contact electrode 53 may apply a back-side bias voltage to the semiconductor channel 40 during programming of the ferroelectric polarization of the ferroelectric memory element 21. Optionally, the front gate contact 81 and / or the back gate contact 83 may be formed on the conductive gate electrode 51 and the back contact electrode 53, respectively, to facilitate the application of the bias voltage used during operation of the transistor 95 of the third exemplary structure. In an alternative embodiment, Figure 9The layers 51 and / or 53 shown may include a gate insulating layer, and the contacts 81 and / or 83 may respectively include a front conductive gate electrode and a back contact electrode (e.g., a back gate).

[0096] refer to Figure 10A and Figure 10B This illustrates a transistor 95 with a fourth exemplary structure according to a fourth embodiment of the present disclosure. In the transistor 95 of the fourth exemplary structure, the ferroelectric memory element 20 and / or the gate electrode 50 may have a tubular configuration surrounding the semiconductor channel 40. In other words, the gate electrode 50 may be a wound gate electrode 54 wound around the ferroelectric memory element 20, which may be a wound ferroelectric memory element 23. The wound ferroelectric memory element 23 is wound (i.e., surrounds) the semiconductor channel 40.

[0097] In this embodiment, the semiconductor channel 40 can be a vertical pillar or a vertical shell surrounding the vertical pillar, the vertical pillar extending longitudinally perpendicular to the planar top surface 11 of the substrate 10, such as... Figure 10B As shown in the diagram. The wound ferroelectric memory element 23 may be an inner shell wound (i.e., surrounding) the semiconductor channel 40. The wound gate electrode 54 is wound around the middle portion of the wound ferroelectric memory element 23. Source contacts and drain contacts (42, 44) contact opposite ends of the semiconductor channel 40 on opposite sides of the wound gate electrode 54. The source contacts and drain contacts (42, 44) may also be wound around the semiconductor channel 40, or they may contact only a portion of the outer periphery of the semiconductor channel 40.

[0098] Generally, the various ferroelectric memory devices 180 of the embodiments of this disclosure can be operated by programming the polarization direction of the ferroelectric memory element 21, applying a positive or negative bias voltage to the conductive gate electrode 51 relative to the semiconductor channel 40, and sensing the polarization direction of the ferroelectric memory element 21 by sensing the magnitude of the current between the source contact 42 and the drain contact 44 while applying a read voltage (i.e., measuring the bias voltage) between the source contact 42 and the drain contact 44. If a back-side ferroelectric memory element 22 is included, then the ferroelectric polarization direction of the back-side ferroelectric memory element 22 is opposite to the ferroelectric polarization direction of the ferroelectric memory element 21. The thickness and / or material composition of the back-side ferroelectric memory element 22 may be the same as or different from the thickness and / or material composition of the ferroelectric memory element 21. In other words, the polarizations of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 are antiparallel to each other and are flipped simultaneously during programming.

[0099] If a conductive back-side gate electrode 52 is included, the voltage applied to the conductive back-side gate electrode 52 may be the same as the voltage applied to the front-side conductive gate electrode 51. A read voltage may be applied to the conductive gate electrode 51 while sensing the polarization direction of the ferroelectric memory element 21, and optionally sensing the polarization direction of the back-side ferroelectric memory element 22.

[0100] The devices of the embodiments of this disclosure offer advantages over ferroelectric primitive graphene memory elements based on tunneling resistors (TERs), which exhibit poor polarization retention and require a thicker ferroelectric barrier to stabilize polarization. However, the thicker barrier results in a lower tunneling current and thus significantly reduces the signal (e.g., read current) in TER-based devices. In contrast, the read current does not flow through the ferroelectric material in the devices of the embodiments of this disclosure. Therefore, a thicker ferroelectric layer can be used in the devices of the embodiments of this disclosure without reducing the read current, and the polarization retention problem is reduced or overcome in the devices of the embodiments of this disclosure, compared to prior art TER-based devices.

[0101] To avoid being bound by a specific theory and to demonstrate the advantages of the devices according to the embodiments of this disclosure, the inventors calculated the on / off ratio of ferroelectric polarization control over the bandgap of a semiconductor in a finite-size nanostructure at room temperature. The inventors developed a quantum mechanical calculation based on the conductivity of ballistic electron transport via a finite-size semiconductor attached to a ferroelectric material and two metal contacts. The inventors' calculations are based on the green function form within a two-band tightly bound Hamiltonian model. In contrast, first-principles electronic structure calculations are used to obtain the density of states and bandgap of two-dimensional semiconductor materials.

[0102] Specifically, Figure 1 The structure is modeled using a rectangular device size of 10nm × 5nm (i.e., the area of ​​each interface between adjacent layers). The thickness d of the ferroelectric material portion is 5nm, and the distance between the ferroelectric material portion and each metal contact is 1nm. The electrostatic potential in the semiconductor material portion below the ferroelectric material portion is controlled by reversing the ferroelectric polarization.

[0103] The inventor's simulation results Figure 11 , Figure 12 and Figures 13A to 13D As shown in the figure, the accuracy of conductivity simulations is limited by numerical precision. Below 10... -2 (Ohm m) -1 The conductivity values ​​are within a range of reliable numerical accuracy, and therefore, the calculations are limited to the range of ferroelectric polarization, resulting in conductivity values ​​of at least 10. -2 (Ohm m) -1 .

[0104] refer to Figure 11This paper presents the calculated density per atom per electron volt for hexagonal boron nitride. This calculation is based on density function theory (DFT) and hybridization functions.

[0105] refer to Figure 12 This paper presents the calculated density per atom per electron volt for molybdenum disulfide. This calculation is based on density function theory (DFT) and hybridization functions.

[0106] Figures 13A to 13D The transistor 95, illustrating a ferroelectric memory device according to an embodiment of this disclosure, has a calculated conductivity (in 10⁻⁶) at room temperature (20 degrees Celsius). 7 A graph showing how ferroelectric polarization changes (in units of / Ohm m). Figure 13A The calculated conductivity is shown for the case where the ferroelectric memory element is composed of hexagonal boron nitride. Figure 13B The calculated conductivity is shown for the case where the ferroelectric memory element is composed of fluorinated graphene. Figure 13C The calculated conductivity is shown for the case where the ferroelectric memory element is composed of molybdenum disilicide. Figure 13D The calculated conductivity is shown for the case where the ferroelectric memory element is composed of germane.

[0107] Figures 13A to 13D The conductivity of all semiconductor channels in the embodiments of this disclosure increases (or decreases) exponentially with respect to ferroelectric polarization in the positive (or negative) direction. This allows the calculated conductivity σ(P) to be fitted to a fitting function that includes ferroelectric polarization P as a variable. Furthermore, the on / off ratio (i.e., the ratio of conductivity in the on state to conductivity in the off state) can be fitted to a function with another variable P. 最大 Another fitting function is given, where the variable is the maximum value of the ferroelectric polarization required to push the Fermi level of the two-dimensional semiconductor into the conduction band. The functional forms of σ(P) and ON / OFF are given below:

[0108] σ(P)=σ0e aP ,as well as

[0109] ON / OFF = e 2aP maximum,

[0110] Where σ0 = σ(P = 0) is the conductivity of the semiconductor channel for the paraelectric case. Table 3 lists the best-fit values ​​for σ(P) and the ON / OFF fitting parameters.

[0111] Table 3: Parameters of fitted ferroelectric materials

[0112] Ferroelectric materials <![CDATA[Optimal value of α (in cm 2 / μC)]]> <![CDATA[P 最大 (in μC / cm) 2 (as a unit) Hexagonal BN 0.61 75 MoSi2 0.49 30 Fluorinated graphene 0.50 40 germane 0.44 10

[0113] While defect states can limit the practical value of the ON / OFF ratio, various two-dimensional semiconductor materials offer generally high ON / OFF ratios. Simulations show that higher ON / OFF ratios are likely to be achieved with wider-bandgap two-dimensional semiconductor materials, and thicker ferroelectric materials can be used in conjunction with such two-dimensional semiconductor materials. Higher operating voltages are expected to increase the thickness of the ferroelectric material in the ferroelectric memory device 180 of the embodiments of this disclosure.

[0114] According to one aspect of this disclosure, the ferroelectric memory array may include an array of memory cells (e.g., transistors) 95 of embodiments of this disclosure. See also Figure 14 A schematic diagram of a ferroelectric memory array including transistors 95 in an array configuration is shown. The ferroelectric memory array can be configured as a random access memory device 501. As used herein, a "random access memory device" means a memory device that includes memory cells that allow random access, i.e., access to any selected memory cell upon a command to read the contents of a selected memory cell.

[0115] The random access memory device 501 of this disclosure includes a memory array region 550 comprising an array of corresponding ferroelectric memory cells 180 located at the intersection of word lines (which may include a first electrical conductor 30 as shown or a second electrical conductor 90 in an alternative configuration) and bit lines (which may include a second electrical conductor 90 as shown or a first electrical conductor 30 in an alternative configuration). For example, word lines 30 may be electrically connected to and / or may include gate electrodes 50 of transistors 95 in the array, while bit lines 90 may be electrically connected to and / or may include source or drain contacts (42, 44) of transistors 95 in the array.

[0116] Random access memory device 501 may also include a row decoder 560 connected to word lines, a sensing circuitry 570 (e.g., a sensing amplifier and other bit line control circuitry) connected to bit lines, a column decoder 580 connected to bit lines, and a data buffer 590 connected to the sensing circuitry. Multiple instances of ferroelectric memory cells (e.g., ferroelectric memory transistors) 95 are provided to form an array configuration of random access memory device 501. Thus, each ferroelectric memory cell in the ferroelectric memory cell 95 may be a two-terminal device including a corresponding first electrode and a corresponding second electrode. It should be noted that the location and interconnection of components are illustrative, and components may be arranged in different configurations. Furthermore, the ferroelectric memory cell 95 may be manufactured as a discrete device, i.e., a single isolated device.

[0117] Embodiments of this disclosure provide a non-volatile memory element with ferroelectrically controlled conductivity based on a two-dimensional semiconductor material or a two-dimensional charge carrier layer (such as a 2DEG layer 40G). Information can be written and stored by applying an electrical pulse that reverses the ferroelectric polarization and thereby induces surface charges in the semiconductor or the two-dimensional charge carrier layer. Information can be read by measuring the resistance of the semiconductor channel including the two-dimensional charge carrier layer.

[0118] Compared to previously known three-terminal ferroelectric-graphene structures, the devices of the embodiments of this disclosure provide a significant increase in the resistance difference of the two-dimensional semiconductor material layer by replacing the gapless pristine graphene (i.e., zero bandgap) with a two-dimensional semiconductor material layer, which may have a bandgap of at least 1.1 eV. Compared to previously known two-terminal vertical tunnel junction devices, the devices of the embodiments of this disclosure greatly improve the stability of ferroelectric polarization because the thickness of the ferroelectric material portion can be increased without signal loss. The devices of the embodiments of this disclosure are non-volatile memory devices capable of non-volatilely storing information, which is not provided by high electron mobility transistors (HEMTs) or heterojunction field-effect transistors (HFETs) known in the art. Because the in-plane geometry allows for low-current operation during the sensing step, the devices of the embodiments of this disclosure enable low-power sensing.

[0119] refer to Figure 15A and Figure 15B This illustration shows a fifth exemplary structure according to a fifth embodiment of the present disclosure, the fifth exemplary structure including a semiconductor material layer 710. The semiconductor substrate may be a bulk semiconductor substrate, wherein the semiconductor material layer 710 extends from a front surface to a back surface; or it may be a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulating layer (not shown) beneath the semiconductor material layer 710 and a manipulation substrate (not shown) beneath the buried insulating layer. For example, the semiconductor substrate may include a commercially available single-crystal silicon wafer or a commercially available semiconductor-on-insulator substrate.

[0120] Semiconductor material layer 710 may comprise single-crystal or polycrystalline semiconductor material. Semiconductor material layer 710 may comprise a doped well in a silicon wafer, the top portion of a silicon wafer, or a semiconductor film deposited on any suitable substrate. In one embodiment, the entire semiconductor material layer 710 may comprise single-crystal semiconductor material, such as single-crystal silicon. The semiconductor material of semiconductor material layer 710 is doped with a first conductivity type, which may be p-type or n-type. The atomic concentration of the dopant of the first conductivity type in semiconductor material layer 710 may be 1.0 × 10⁻⁶. 14 / cm 3 Up to 3.0×10 17 / cm 3 Within the range, but smaller and larger atomic concentrations can also be used. In one embodiment, the semiconductor material layer 710 may consist essentially of silicon and dopants of a first conductivity type.

[0121] In an alternative embodiment, the semiconductor material layer 710 may comprise the two-dimensional semiconductor material described above with respect to the first to fourth embodiments. For example, the semiconductor material layer may comprise a metal dichalcogenide (e.g., MoS2) material having a thickness of 1 to 5 monolayers (e.g., 0.6 nm to 4 nm). In another alternative embodiment, an organic semiconductor material layer or a wide-bandgap metal oxide semiconductor material layer (e.g., zinc oxide or titanium dioxide) may be used instead.

[0122] A shallow trench isolation structure 720 may be formed in the upper portion of the semiconductor material layer 710. For example, the shallow trench can be formed through the top surface of the semiconductor material layer 710 by applying and patterning a photoresist layer above the top surface of the semiconductor material layer 710, and transferring the pattern in the photoresist layer to the upper portion of the semiconductor material layer 710 using an anisotropic etching process. The photoresist layer can then be removed, for example, by ashing. Dielectric material may be deposited in the shallow trench, and excess portions of the dielectric can be removed from above a horizontal plane including the top surface of the semiconductor material layer 710 using a planarization process such as chemical mechanical polishing (CMP). The remaining portion of the dielectric material filling the shallow trench comprises the shallow trench isolation structure 720. The shallow trench isolation structure 720 may laterally surround a device region 730, one of which is located in… Figure 15A and Figure 15B As shown in the figure. In one embodiment, each device region may be laterally surrounded by a shallow trench isolation structure 720. In one embodiment, at least one device region may have a rectangular horizontal cross-sectional shape having a pair of first edges extending laterally along a first horizontal direction hd1' and a pair of second edges extending laterally along a second horizontal direction hd2'. Although this disclosure is described using a single device region, it should be understood that multiple device regions laterally surrounded by corresponding shallow trench isolation structures 720 may be formed in the first exemplary structure.

[0123] The area of ​​each device region 730 may be defined by the bottom edge of the inner periphery of a shallow trench isolation structure 720 that laterally surrounds a portion of the semiconductor material layer 710. In one embodiment, the device region 730 may have a rectangular horizontal cross-sectional shape and may have a pair of first straight edges parallel to a first horizontal direction hd1' and a pair of second straight edges parallel to a second horizontal direction hd2'.

[0124] refer to Figure 16A and Figure 16B Ferroelectric material can be deposited on the top surface of the semiconductor material layer 710 and above the shallow trench isolation structure 720 to form a ferroelectric gate dielectric layer 750L. The ferroelectric gate dielectric layer 750L may contain any ferroelectric material that can be used in the ferroelectric memory element 21 described above. The ferroelectric gate dielectric layer 750L comprises and / or substantially consists of at least one ferroelectric material, such as hafnium oxide (e.g., hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic crystal phase), zirconium oxide, hafnium zirconium oxide, barium oxide, barium titanate (e.g., BaTiO3; BT), calcium staborite (e.g., Ca2B6O3). 11 ·5H2O), bismuth titanate (such as Bi 12 TiO 20 Bi4Ti3O 12 Or Bi2Ti2O7), barium europium titanate, ferroelectric polymers, germanium telluride, anhydrous potassium magnesium vanadium (such as M2M'2(SO4)3, where M is a monovalent metal and M' is a divalent metal), lead scandium tantalum (such as Pb(Sc) x Ta 1-x) O3), lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN), (LaAlO3)), polyvinylidene fluoride (CH2CF2). n Potassium niobate (such as KNbO3), sodium tartrate (such as KNaC4H4O6·4H2O), potassium oxytitanium phosphate (such as KO5PTi), sodium bismuth titanate (such as Na 0.5 Bi 0.5 TiO3 or Bi 0.5 Na 0.5 TiO3, lithium tantalate (such as LiTaO3(LT)), lead lanthanum titanate (such as (Pb,La)TiO3(PLT)), lead lanthanum zirconium titanate (such as (Pb,La)(Zr,Ti)O3(PLZT)), ammonium dihydrogen phosphate (such as NH4H2PO4(ADP)), or potassium dihydrogen phosphate (such as KH2PO4(KDP)). In one embodiment, the gate dielectric layer 750L comprises and / or is substantially composed of a ferroelectric dielectric material. The ferroelectric gate dielectric layer 750L can be deposited by conformal deposition or non-conformal deposition processes. For example, the ferroelectric gate dielectric layer 750L can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the ferroelectric gate dielectric layer 750L can be in the range of 4 nm to 30 nm, such as in the range of 6 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0125] The ferroelectric gate dielectric layer 750L may include multiple distinct regions, such as two or more regions extending along a first horizontal direction hd1'. (Reference) Figure 17A and Figure 17B In an illustrative example, the ferroelectric gate dielectric layer 750L includes four distinct regions (e.g., segments): a first segment 75A, a second segment 75B, a third segment 75C, and a fourth segment 75D. However, for example, there may be two, three, or more than four segments, such as five to ten segments. Each of the first segment 75A, the second segment 75B, the third segment 75C, and the fourth segment 75D may have a corresponding rectangular area. The sum of the areas of the first segment 75A, the second segment 75B, the third segment 75C, and the fourth segment 75D may be the same as the entire area of ​​the device region 730. In an illustrative example, the first segment 75A, the second segment 75B, the third segment 75C, and the fourth segment 75D may be arranged from one side to the other along a second horizontal direction hd2' and each extend along a first horizontal direction hd1' (i.e., having their longest horizontal dimension along the first horizontal direction).

[0126] In one embodiment, a focused ion beam (FIB) device can be used to scan a focused ion beam in a region (such as a first segment 75A) of a ferroelectric gate dielectric layer 750L along a first horizontal direction hd1'. The focused ion beam has a sufficiently small first diameter at the impact point of the ferroelectric gate dielectric layer 750L such that only the first segment 75A is irradiated with the ion beam. For example, at the impact point, the diameter may be 10 nm to 20 nm wide, and the first segment 75A may have a width of 10 nm to 20 nm in a second horizontal direction hd2'. The first segment 75A has a width substantially the same as the diameter of the focused ion beam at the impact point. As used herein, substantially the same width includes a width that is exactly the same as or within 10% of the diameter of the focused ion beam at the impact point.

[0127] A focused ion beam has a first ion dose, a first beam energy, and a first residence time. The residence time includes the time the beam contacts a given unit region. The beam can be scanned once or multiple times along a first horizontal direction within a first segment. Therefore, the residence time is a function of at least the beam scanning speed and the number of traversals (i.e., scans) within the segment. The energy of a focused ion beam can range from 1 keV to 300 keV, such as from 5 keV to 50 keV, but smaller and larger ion beam energies can also be used. The dose of a focused ion beam can be 1.0 × 10⁻⁶. 12 atoms / cm 2 Up to 1.0×10 15 atoms / cm 2Within the range, but smaller and larger doses can also be used. The atomic species of the ion beam can be any element that can be used in a focused ion beam. For example, the atomic species of ions in a focused ion beam can contain helium or gallium, and / or can be composed primarily of helium or gallium.

[0128] Ions bombarding a segment 75A of the ferroelectric gate dielectric layer 750L induce structural damage therein. Specifically, the focused ion beam irradiation process produces at least one of the following: a first broken bond density in the ferroelectric gate dielectric layer segment, a first displaced atom density in the lattice of the ferroelectric gate dielectric layer segment, and / or implanted (i.e., implanted ion concentration) a first gallium or helium atom density in the ferroelectric gate dielectric layer segment.

[0129] To avoid being bound by a specific theory, it is believed that broken bonds block the magnetic domain walls in the dielectric layer segment of the ferroelectric gate, which requires a higher applied voltage to switch the polarization state of the segment. The percentage shift of the applied voltage (e.g., coercive field) depends on the degree of structural damage (i.e., broken bond density) in the ferroelectric material of the damaged segment.

[0130] Displaced atoms shift from their equilibrium positions to metastable positions within the crystal lattice, effectively delaying changes in the electric dipole moment within the ferroelectric material. In other words, the 750L segment of the ferroelectric gate dielectric layer with displaced atoms does not lose its ferroelectric properties, but the displacement of one or more atoms from their normal positions within the unit cell structure of the crystal lattice delays the switching of the electric dipole moment's direction by requiring more energy accumulation to do so. Therefore, by increasing the amount of applied voltage (e.g., a coercive field) required to switch the polarization direction of the segment, the hysteresis curve of the ferroelectric gate dielectric layer segment is modified from that of the undamaged segment. The percentage shift in the applied voltage (e.g., the coercive field) depends on the degree of structural damage (i.e., the density of displaced atoms) in the damaged segment of the ferroelectric material.

[0131] Similarly, implanting helium or gallium atoms into a segment using a focused ion beam results in damage to the lattice of the segment containing the helium or gallium atoms. This damage causes an increase in the applied voltage (e.g., a coercive field) required to switch the polarization direction of the implanted segment. The percentage shift in the applied voltage (e.g., the coercive field) depends at least in part on the concentration of implanted helium or gallium ions (i.e., the implanted atom density) in the ferroelectric material of the damaged segment.

[0132] refer to Figure 18A and Figure 18B A second focused ion beam is scanned over the second segment 75B of the ferroelectric gate dielectric layer 750L. The second focused ion beam has a second beam diameter, a second ion dose, a second beam energy, and a second beam residence time at the impact point of layer 750L.

[0133] In one embodiment, the diameter of the second focused ion beam at the impact point on layer 750L is substantially the same as the width of the second segment 75B, and scanning is performed only above the second segment 75B. In this embodiment, at least one of the second ion dose, the second beam energy, and / or the second beam residence time is less than the corresponding first ion dose, the first beam energy, and / or the first beam residence time.

[0134] In another embodiment, the diameter of the second focused ion beam at the impact point on layer 750L is substantially the same as the sum of the widths of the first segment 75A and the second segment 75B in the second horizontal direction hd2'. In this embodiment, the second focused ion beam is scanned simultaneously above the first segment 75A and the second segment 75B. In this embodiment, the second ion dose, the second beam energy, and / or the second beam residence time may be the same as the corresponding first ion dose, the second beam energy, and / or the first beam residence time. The first segment 75A is scanned twice (i.e., by the first ion beam and the second ion beam), while the second segment 75B is scanned once (i.e., by the second ion beam only).

[0135] In two of these embodiments, the first segment 75A has a higher structural defect density than the second segment 75B. In other words, compared to the second segment 75B, the first segment 75A has a higher broken bond density in the ferroelectric gate dielectric layer, a higher displaced atom density in the lattice of the ferroelectric gate dielectric layer, and / or a higher gallium or helium atom density.

[0136] refer to Figure 19A and Figure 19B A third focused ion beam is scanned on the third segment 75C of the ferroelectric gate dielectric layer 750L. The third focused ion beam has a third beam diameter, third ion dose, third beam energy, and third beam residence time at the impact point of layer 750L.

[0137] In one embodiment, the diameter of the third focused ion beam at the impact point on layer 750L is substantially the same as the width of the third segment 75C, and scanning is performed only above the third segment 75C. In this embodiment, at least one of the third ion dose, the third beam energy, and / or the third beam residence time is less than the corresponding first or second ion dose, the first or second beam energy, and / or the first or second beam residence time.

[0138] In another embodiment, the diameter of the third focused ion beam at the impact point on layer 750L is substantially the same as the width of the sum of the first segment 75A, the second segment 75B, and the third segment 75C in the second horizontal direction hd2'. In this embodiment, the third focused ion beam scans simultaneously above the first segment 75A, the second segment 75B, and the third segment 75C. In this embodiment, the third ion dose, the third beam energy, and / or the third beam residence time may be the same as the corresponding first ion dose, the second beam energy, and / or the first beam residence time. The first segment 75A is scanned three times (i.e., by the first ion beam, the second ion beam, and the third ion beam), the second segment 75B is scanned twice (i.e., by the second ion beam and the third ion beam), and the third segment 75C is scanned once (i.e., by the third ion beam only).

[0139] In two of these embodiments, the first segment 75A has a higher structural defect density than the second segment 75B, and the second segment 75B has a higher structural defect density than the third segment 75C. In other words, compared to the third segment 75C, the first segment 75A and the second segment 75B have a higher broken bond density in the ferroelectric gate dielectric layer, a higher displaced atom density in the lattice of the ferroelectric gate dielectric layer, and / or a higher gallium or helium atom density.

[0140] The fourth segment 75D remains unscanned by any focused ion beam. Therefore, the fourth segment has the lowest structural defect density of any segment. In other words, the fourth segment 75D has a lower structural defect density than the first, second, or third segments.

[0141] Although four segments (75A, 75B, 75C, 75D) and three ion beams have been described above, any number of two or more segments with different structural defect densities can be used. Furthermore, any suitable number of focused ion beams can be used to form different structural defect densities within the respective segments. Finally, while focused ion beams have been described above, any other suitable method for forming structural defects within segments can be used alternatively.

[0142] The implanted gallium or helium ions can pass through the ferroelectric gate dielectric layer 750L, can remain in the ferroelectric gate dielectric layer 750L, and / or can be volatilized (e.g., in the case of implanted helium atoms). If the various segments (75A, 75B, 75C, 75D) of the ferroelectric gate dielectric layer 750L have the same helium or gallium concentration, then they can have the same material composition; or if they have different helium or gallium concentrations, then they can have different compositions. In one embodiment, the structural defect density (e.g., broken bond density, displaced atom density, and / or implanted atom density) in the various segments (75A, 75B, 75C, 75D) of the ferroelectric gate dielectric layer 750L can be 5.0 × 10⁻⁶. 16 / cm 3 Up to 5.0×10 21 / cm 3 Within the range, such as 1.0 × 10 18 / cm 3 Up to 2.5×10 21 / cm 3 Within the range of 0.01 nm to 0.1 nm, smaller and larger defect densities can also be used. The average displacement distance of the shifted atoms (which provide structural defects) can range from 0.01 nm to 0.1 nm, but smaller and larger average displacement distances can also be used.

[0143] refer to Figures 20A to 20D The hysteresis curves of polarization P of different sections of the ferroelectric gate dielectric layer 750L are schematically shown as functions of the external electric field E (which is a function of the applied voltage). Figure 20A Corresponding to Figure 19A and 19B Hysteresis curve of the first segment 75A of the ferroelectric gate dielectric layer 750L. Figure 20B Corresponding to Figure 19A and 19B Hysteresis curve of the second segment 75B of the ferroelectric gate dielectric layer 750L. Figure 20C Corresponding to Figure 19A and 19B Hysteresis curve of the third segment 75C of the ferroelectric gate dielectric layer 750L. Figure 20D Corresponding to Figure 19A and 19B The hysteresis curve of the fourth segment 75D of the ferroelectric gate dielectric layer 750L in the image, the hysteresis curve being comparable to, as before any focused ion beam scan... Figure 16A and Figure 16B The hysteresis curves of the ferroelectric gate dielectric layer 750L formed at the processing step are the same. Generally speaking, the higher the density of structural defects in the corresponding segment of the ferroelectric gate dielectric layer 750L, the higher the coercive field of the corresponding segment of the ferroelectric gate dielectric layer 750L.

[0144] refer to Figure 21A and Figure 21B , can be Figure 19A and Figure 19B The structure undergoes further processing steps to form the gate electrode. Subsequently, at least one gate electrode material layer may be deposited over the ferroelectric gate dielectric layer 750L. The at least one gate electrode material layer comprises at least one conductive material. For example, the at least one gate electrode material layer may comprise at least one of a metal, an intermetallic alloy, a metal-semiconductor alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a doped semiconductor material, wherein the doped semiconductor material has an average atomic concentration of 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 The range of p-type or n-type dopants is specified. At least one gate electrode material layer may consist of a single conductive material or a stack of multiple conductive materials. The bottommost material within the at least one gate electrode material layer may be selected to provide a suitable operating function for the gate electrode subsequently formed by patterning the at least one gate electrode material layer. The at least one gate electrode material layer may be formed by chemical vapor deposition, physical vapor deposition, vacuum evaporation, and / or atomic layer deposition. The thickness of the at least one gate electrode material layer may range from 50 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0145] The gate cap dielectric layer may optionally be formed over the gate electrode material layer. The gate cap dielectric layer contains a diffusion barrier material, such as silicon nitride. The thickness of the gate cap dielectric layer can range from 20 nm to 60 nm, but smaller and larger thicknesses are also possible.

[0146] A photoresist layer (not shown) may be applied over the gate cap dielectric layer and may be photolithographically patterned to form a line pattern extending over a corresponding device region in the device region. An anisotropic etching process (such as reactive ion etching) may be performed to transfer the pattern onto the photoresist layer through the layer stack of the gate cap dielectric layer and at least one gate electrode material layer, optionally via a ferroelectric gate dielectric layer 750L. The ferroelectric gate dielectric layer 750L or the semiconductor material layer 710 may be used as an etch-stop structure. Each patterned portion of the gate cap dielectric layer includes a gate cap dielectric (e.g., silicon oxide or silicon nitride) 758, and each patterned portion of at least one gate electrode material layer includes a gate electrode (752, 754). In one embodiment, each gate electrode (752, 754) may include a first gate electrode portion 752 comprising a first gate electrode material (e.g., metal) and a second gate electrode portion 754 comprising a second gate electrode material (e.g., polysilicon). In one embodiment, each gate electrode (752, 754) may cover each of the plurality of ferroelectric gate dielectric portions (i.e., segments 75A, 75B, 75C, and 75D) of the ferroelectric gate dielectric layer 750L.

[0147] An extended ion implantation process can be performed to implant a dopant of a second conductivity type into an unmasked surface portion of a semiconductor material layer 710. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The implanted surface portion of the semiconductor material layer 710 is transformed into a doped semiconductor region with dopant of the second conductivity type. Source extension region 731 and drain extension region 733 (also referred to as LDD regions) can be formed in each device region for forming a field-effect transistor by transforming the surface portion of the semiconductor material layer 710 into a doped semiconductor material portion with dopant of the second conductivity type. The average atomic concentration of the dopant of the second conductivity type in the source extension region 731 and drain extension region 733 can be 1.0 × 10⁻⁶. 17 / cm 3 Up to 1.0×10 20 / cm 3The depth of the source extension region 731 and the drain extension region 733 can be in the range of 10 nm to 100 nm, but smaller and larger depths are also possible. Each surface portion of the semiconductor material layer 710 below the gate electrode (752, 754) and located between an adjacent pair of source extension regions 731 and drain extension regions 733 includes a semiconductor channel 35. Each semiconductor channel 35 extends between the source extension region 731 and the drain extension region 733 and has doping of a first conductivity type. Optionally, halogen implantation can be performed to implant a dopant of the first conductivity type into the region below the gate electrode (752, 754).

[0148] refer to Figure 22A and Figure 22B At least one dielectric material (such as silicon nitride and / or silicon oxide) may be conformally deposited over the gate cap dielectric 758, source extension region 731, drain extension region 733, and shallow trench isolation structure 720. The at least one dielectric material may be anisotropically etched (e.g., by a reactive ion sidewall spacer etching process) to remove the horizontal portions. Each remaining vertical portion of the respective stack laterally surrounding the gate electrodes (752, 754) and gate cap dielectric 758 includes a gate spacer (i.e., a sidewall spacer) 756, which contains at least one dielectric material. Although Figure 22A and Figure 22B Only a single gate spacer 756 is shown in the document, but the following embodiments are explicitly covered herein: wherein multiple gate spacers are formed around each stack of the gate electrode (752, 754) and the gate cap dielectric 758 by sequentially depositing and anisotropically etching multiple dielectric material layers.

[0149] Anisotropic etching can also etch unmasked portions of the ferroelectric gate dielectric layer 750L. Each remaining portion of the ferroelectric gate dielectric layer 750L contains a ferroelectric gate dielectric 750. In this case, the sidewall of each ferroelectric gate dielectric 750 may vertically coincide with the outer sidewall of a corresponding gate spacer 756. In one embodiment, the gate spacer 756 may laterally surround the respective stack of gate electrodes (752, 754) and gate cap dielectric 758. The width of each gate spacer 756 at its base portion (i.e., the lateral distance between the inner and outer sidewalls) may range from 20 nm to 100 nm, but smaller and larger widths are also possible. Each successive assembly of the ferroelectric gate dielectric 750, gate electrodes (752, 754), optional gate cap dielectric 758, and optional gate spacer 756 includes a gate stack structure (750, 752, 754, 758, 756).

[0150] A dopant of the second conductivity type can be implanted into the unmasked portion of the source extension region 731, the drain extension region 733, and the region beneath the semiconductor material layer 710. The implanted portions of the source extension region 731, the drain extension region 733, and the semiconductor material layer 710 form a deep source region 732 and a deep drain region 734. The average atomic concentration of the dopant of the second conductivity type in the deep source region 732 and the deep drain region 734 can be 5.0 × 10⁻⁶. 18 / cm 3 Up to 2.0×10 21 / cm 3 The depth of the deep source region 732 and deep drain region 734 can be within the range of 40 nm to 300 nm, but smaller and larger depths are also possible. The depth of the deep source region 732 and deep drain region 734 can be greater than the depth of the remaining portions of the source extension region 731 and drain extension region 733. The deep source region 732 and deep drain region 734 can be formed within each device region 730.

[0151] Each successive combination of source extension region 731 and deep source region 732 constitutes a source region (731, 732). Each successive combination of drain extension region 733 and deep drain region 734 constitutes a drain region (733, 734). Generally, the source regions (731, 732) and drain regions (733, 734) may be formed in the semiconductor material of the semiconductor material layer 710 within each device region laterally surrounded by the shallow trench isolation structure 720. A semiconductor channel 35 extends in a first horizontal direction hd1' between the source regions (731, 732) and drain regions (733, 734) below the stack of gate electrodes (752, 754) and gate cap dielectric 758. Generally, the source regions (731, 732) and drain regions (733, 734) may be formed within or on the semiconductor material layer 710. The source regions (731, 732) and drain regions (733, 734) can be separated from each other by the channel region 35 in the semiconductor material layer 710.

[0152] refer to Figure 23A and Figure 23BDielectric material can be deposited over the gate stack structure (750, 752, 754, 758, 756), source region (731, 732), drain region (733, 734), and shallow trench isolation structure 720. The dielectric material may comprise a planarizable dielectric material, such as undoped or doped silicate glass; or a self-planarizable dielectric material, such as flowable oxide (FOX). The dielectric material can be deposited via chemical vapor deposition (CVD) processes (such as plasma-enhanced CVD) or by spin coating. The top surface of the dielectric material can be planarized during or after the deposition process. A dielectric material layer with a planar (i.e., horizontal) top surface is formed, and contact via structures are subsequently formed through the dielectric material layer. Thus, the dielectric material layer is referred to herein as contact-level dielectric layer 770. The top surface of contact-level dielectric layer 770 can be planar and can be located above the top surface of gate cap dielectric 758. The vertical distance between the top surface of the contact dielectric layer 770 and the top surface of the gate cap dielectric 758 can range from 30 nm to 7400 nm, but smaller and larger thicknesses are also possible.

[0153] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 770 and may be photolithographically patterned to form dispersed openings passing through it. The openings in the photoresist layer may be formed over the source regions (731, 732), drain regions (733, 734), and gate electrodes (752, 754). An anisotropic etching process may be performed to form contact via cavities passing through the contact-level dielectric layer 770. The contact via cavity includes: a source contact via cavity extending from the top surface of the contact-level dielectric layer 770 to the top surface of a corresponding source region in the source regions (731, 732); a drain contact via cavity extending from the top surface of the contact-level dielectric layer 770 to the top surface of a corresponding drain region in the drain regions (733, 734); and a gate contact via cavity extending from the top surface of the contact-level dielectric layer 770 to the top surface of a corresponding gate electrode in the gate electrodes (752, 754).

[0154] A metal capable of forming a metal-semiconductor alloy can be deposited into the contact via cavity using conformal or non-conformal deposition methods. If the semiconductor material layer 710 comprises and / or is substantially composed of doped silicon, then the metal can be a material capable of forming a metal silicide. For example, the metal may comprise nickel, titanium, tungsten, molybdenum, platinum, or another metal capable of forming a metal silicide. An annealing process is performed at a high temperature to induce the formation of the metal silicide material. The high temperature can be in the range of 500 degrees Celsius to 750 degrees Celsius. Unreacted portions of the metal can be removed by a wet etching process that is selective for the metal silicide material. The remaining portion of the metal silicide material includes a source-side metal-semiconductor alloy region 742 that contacts the corresponding source regions (731, 732), a drain-side metal-semiconductor alloy region 744 that contacts the corresponding drain regions (733, 734), and a gate-side metal-semiconductor alloy region 745 that contacts the corresponding gate electrode 754 (in the case where the topmost material of the gate electrode (752, 754) contains silicon prior to the annealing process).

[0155] A metal liner containing a diffusion-barrier material may be deposited on the outer peripheral portion of the remaining volume of the contact via cavity. The metal liner may comprise a favorable metal nitride material (such as TiN, TaN, or WN) and / or a metal carbide material (such as TiC, TaC, or WC). The thickness of the metal liner may range from 3 nm to 15 nm, but smaller and larger thicknesses are also possible.

[0156] Metal filler materials such as Cu, W, Mo, Co, Ru, and / or other elemental metals or intermetallic alloys may be deposited in the remaining volume of the contact via cavity. The portion of the metal filler material and metal liner positioned above a horizontal plane including the top surface of the contact-level dielectric layer 770 can be removed by a planarization process. The remaining portion of the metal filler material, along with each successive combination of the metal liner filling a corresponding contact via cavity in the contact via cavity, constitutes a contact via structure (782, 784, 785). The contact via structures (782, 784, 785) include a source contact via structure 782 contacting a corresponding source-side metal-semiconductor alloy region 742, a drain contact via structure 784 contacting a corresponding drain-side metal-semiconductor alloy region 744, and a gate contact via structure 785 contacting a corresponding gate-side metal-semiconductor alloy region 745 or a corresponding gate electrode 754 (in the case where the gate-side metal-semiconductor alloy region 745 is not formed). Each source contact via structure 782 includes a source-side metal liner 782L and a source-side metal filler portion 782F. Each drain contact via structure 784 includes a drain-side metal liner 784L and a drain-side metal filler portion 784F. Each gate contact via structure 785 includes a gate-side metal liner 785L and a gate-side metal filler portion 785F. A field-effect transistor 800 is provided, the field-effect transistor having multiple on-state voltages for various segments (75A, 75B, 75C, 75D) of a ferroelectric gate dielectric 750.

[0157] refer to Figure 24 This illustrates an exemplary channel conductivity of a field-effect transistor 800 according to a fifth embodiment of the present disclosure. Different coercive fields of segments (75A, 75B, 75C, 75D) of the ferroelectric gate dielectric 750 induce multiple turn-on voltages for different portions of the channel region 35 beneath each of the corresponding segments (75A, 75B, 75C, 75D) of the ferroelectric gate dielectric 750. In other words, each portion of the channel region 35 beneath each corresponding segment (75A, 75B, 75C, 75D) of the ferroelectric gate dielectric 750 has a corresponding turn-on voltage different from the other turn-on voltages. Figure 24 In the example shown, the first conductivity type can be p-type, and the minority charge carriers in the channel region 35 can be electrons.

[0158] If transistor 800 is a ferroelectric memory device (i.e., a memory transistor), then a ferroelectric memory array can be provided, which may include... Figure 23A and Figure 23B The array of ferroelectric memory devices 800 shown is illustrated. The array may include a NOR-type array. Each ferroelectric memory device (i.e., transistor) 800 may include a multi-level memory cell array.

[0159] Each device's ferroelectric gate dielectric 750 (i.e., transistor 800) can be programmed such that the electric dipole moment within the ferroelectric gate dielectric 750 points upward, causing electrons (i.e., minority charge carriers) to repel the channel region 35 before a gate voltage is applied. As the gate voltage increases, the electric dipole moment of the region of the ferroelectric gate dielectric 750 with the lowest coercivity (such as the fourth segment 75D) can flip at a first turn-on voltage, and the channel conductivity can gradually increase with the increase of the source-drain current. As the gate voltage further increases, the electric dipole moment of another region of the ferroelectric gate dielectric 750 with a second lowest coercivity (such as the third segment 75C) can flip at a second turn-on voltage, and the channel conductivity can gradually increase with the accompanying increase of the source-drain current. As the gate voltage increases further, the electric dipole moment of another region of the ferroelectric gate dielectric 750 with a next higher coercivity (such as the second segment 75B) can flip at the third turn-on voltage, and the channel conductivity can gradually increase with the accompanying increase of the source-drain current. When the gate voltage increases even further, the electric dipole moment of the region of the ferroelectric gate dielectric 750 with the highest coercivity (such as the first segment 75A) can flip at the final (such as the fourth) turn-on voltage, and the channel conductivity can gradually increase with the accompanying increase of the source-drain current.

[0160] The threshold voltage of the field-effect transistor 800 can be defined as the lowest of a plurality of turn-on voltages of different portions (i.e., segments) of the channel region 35 below the corresponding portion (i.e., section) of the ferroelectric gate dielectric 750. For example, the threshold voltage of the field-effect transistor 800 can be the turn-on voltage of the portion of the channel region 35 below the fourth segment 75D of the ferroelectric gate dielectric 750. Generally, the conductivity of the channel region 35 at a gate bias voltage greater than the threshold voltage of the field-effect transistor (such as a voltage 0.1V higher than the threshold voltage) can be a function of the hysteresis of the voltage applied to the gate electrodes (752, 754) and can include at least two different conductivity values.

[0161] refer to Figure 25 In another embodiment, an interconnect network of transistors 800 is shown. Each transistor in transistor 800 is... Figure 23A and Figure 23BThe corresponding field-effect transistor 800 is shown. The transistors can be connected via a synaptic connection configuration, where the output nodes of one set of transistors are connected to a corresponding set of multiple input nodes of another set of ferroelectric memory devices. The average number of connections per output node for each transistor can be at least three, and can be four or more. Connections within the synaptic connection configuration can be limited to the physical proximity of each transistor. For example, electrical connections can be limited to at most a second, third, or fourth nearest neighbor transistor or any other predetermined level of physical proximity. Such synaptic connection configurations can be advantageously used to provide computing devices that simultaneously compute multiple possibilities and provide probabilistic answers to a given problem. The conductivity of each path can increase with increasing corresponding control voltage in such a synaptic connection configuration.

[0162] refer to Figures 15A to 25 With reference to the accompanying drawings and according to a fifth embodiment of the present disclosure, the ferroelectric device 800 includes a semiconductor channel region 35, a gate electrode (752, 754), and a ferroelectric gate dielectric 750 located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions (75A to 75D) with different structural defect densities.

[0163] In one embodiment, device 800 is a transistor further comprising source regions (731, 732) and drain regions (733, 734), wherein channel region 35 is located between the source and drain regions. In one embodiment, a plurality of ferroelectric gate dielectric portions (75A to 75D) have the same thickness. In one embodiment, each of the plurality of ferroelectric gate dielectric portions (75A to 75D) comprises a ferroelectric dielectric transition metal oxide material (such as hafnium oxide doped with Zr, Al, or Si, or any of the other ferroelectric materials described above). In one embodiment, channel region 35 comprises a silicon (e.g., polycrystalline silicon or monocrystalline silicon) channel region, a metal oxide (e.g., ZnO) semiconductor channel region, an organic semiconductor channel region, or a two-dimensional metal dichalcogenide (e.g., MoS2) semiconductor channel region.

[0164] In one embodiment, each boundary between adjacent pairs of ferroelectric gate dielectric portions (e.g., the boundary between adjacent segments 75A and 75B, etc.) extends in a first horizontal direction hd1' between the gate electrode (752, 754) and the channel region 35, and is parallel to the straight line connecting the geometric center of the source region (731, 732) and the geometric center of the drain region (733, 734). In one embodiment, the plurality of ferroelectric gate dielectric portions (75A to 75D) includes three or more ferroelectric gate dielectric portions. The structural defect density may differ by at least 10% between different portions (e.g., segments 75A to 75D), such as by 20% to 200%. For example, the defect density in the first segment 75A may be at least 10% higher than the defect density in the second segment 75B, etc. In one embodiment, the structural defect density is 5.0 × 10⁻⁶. 16 / cm 3 Up to 5.0×10 21 / cm 3 Within the range.

[0165] In one embodiment, the different structural defect densities include different broken bond densities in different ferroelectric gate dielectric portions. In another embodiment, the different structural defect densities include different displaced atom densities in the lattice of different ferroelectric gate dielectric portions. In yet another embodiment, the different structural defect densities include different gallium or helium atom densities in different ferroelectric gate dielectric portions. In one embodiment, the ferroelectric gate dielectric 750 contacts the channel region 35, and the channel region 35 contacts different portions of the corresponding different ferroelectric gate dielectric portions 75A to 75D with different conductivity values.

[0166] In one embodiment, the ferroelectric memory array includes a plurality of ferroelectric devices 80 as described above. Figure 25 In another embodiment shown, the interconnection network of the ferroelectric devices described above is connected by a synaptic connection structure, wherein the conductivity of each path increases with the increase of the corresponding control voltage.

[0167] Various embodiments of this disclosure provide a variety of ferroelectric semiconductor devices that can be used as memory, logic, or sensor devices. The configuration of the devices disclosed herein can provide various advantages, including but not limited to multiple on-states and / or multiple memory states (which include different polarization states of multiple segments of the ferroelectric gate dielectric 750).

[0168] While specific preferred embodiments have been mentioned above, it will be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. In cases where embodiments employing specific structures and / or constructions are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or constructions, provided that such substitutions are not expressly prohibited or otherwise known to those skilled in the art as impossible. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A ferroelectric device, comprising: a semiconductor channel region; a gate electrode; and a ferroelectric gate dielectric located between the channel region and the gate electrode and comprising a plurality of ferroelectric gate dielectric portions having different structural defect densities.

2. The ferroelectric device of claim 1, further comprising a source region and a drain region, wherein the channel region is located between the source region and the drain region.

3. The ferroelectric device of claim 2, wherein the plurality of ferroelectric gate dielectric portions have the same thickness.

4. The ferroelectric device of claim 3, wherein each of the plurality of ferroelectric gate dielectric portions comprises a ferroelectric dielectric transition metal oxide material selected from hafnium oxide, zirconium oxide, hafnium zirconium oxide, barium titanate, whitlockite, bismuth titanate, barium europium titanate, a ferroelectric polymer, germanium telluride, noelites, lead scandium tantalate, lead titanate, lead zirconium titanate, lithium niobate, LaAlO3, polyvinylidene fluoride, potassium niobate, potassium sodium tartrate, potassium titanyl phosphate, sodium bismuth titanate, lithium tantalate, lead lanthanum titanate, lead lanthanum zirconium titanate, ammonium dihydrogen phosphate, or potassium dihydrogen phosphate, comprising at least one dopant selected from Al, Zr, and Si, and having a ferroelectric non-centrosymmetric orthorhombic crystal phase.

5. The ferroelectric device of claim 4, wherein the channel region comprises a silicon channel region, a metal-oxide-semiconductor channel region, an organic semiconductor channel region, or a two-dimensional metal dichalcogenide semiconductor channel region.

6. The ferroelectric device of claim 2, wherein each boundary between an adjacent pair of the plurality of ferroelectric gate dielectric portions extends between the gate electrode and the channel region and is parallel to a straight line connecting a geometric center of the source region and a geometric center of the drain region.

7. The ferroelectric device of claim 1, wherein the plurality of ferroelectric gate dielectric portions comprises three or more ferroelectric gate dielectric portions.

8. The ferroelectric device of claim 1, wherein the structural defect density is in a range from 5.0 x 10 16 / cm 3 to 5.0 x 10 21 / cm 3 .

9. The ferroelectric device of claim 1, wherein the different structural defect densities comprise different broken bond densities in different ferroelectric gate dielectric portions.

10. The ferroelectric device of claim 1, wherein the different structural defect densities comprise different displaced atom densities in lattices in different ferroelectric gate dielectric portions.

11. The ferroelectric device of claim 1, wherein the different structural defect densities comprise different gallium or helium atom densities implanted in different ferroelectric gate dielectric portions.

12. The ferroelectric device of claim 1, wherein the ferroelectric gate dielectric contacts the channel region, and wherein different portions of the channel region contacting different portions of the respective different ferroelectric gate dielectric portions have different conductivity values.

13. A ferroelectric memory array comprising a plurality of the ferroelectric devices of claim 1.

14. An interconnect network of ferroelectric devices comprising a plurality of the ferroelectric devices of claim 1 connected in a synapse-connected configuration, wherein a conductivity of each path increases with an increase in a respective control voltage.

15. A method of forming a ferroelectric device, comprising: forming a source region and a drain region laterally spaced apart from one another by a channel region; forming a ferroelectric gate dielectric over the channel region; forming different structural defects in the ferroelectric gate dielectric, wherein a plurality of ferroelectric gate dielectric portions have different structural defect densities; and forming a gate electrode over each of the plurality of ferroelectric gate dielectric portions.

16. The method of claim 15, wherein forming the ferroelectric gate dielectric comprises: forming a ferroelectric gate dielectric layer; and performing different focused ion beam irradiation processes in each of the plurality of ferroelectric gate dielectric portions to provide different structural defect densities in each of the plurality of ferroelectric gate dielectric portions.

17. The method of claim 16, wherein the different focused ion beam irradiation processes produce at least one of: different broken bond densities in different ferroelectric gate dielectric portions, different displaced atom densities in crystal lattices in the different ferroelectric gate dielectric portions, or different gallium or helium atom densities in the different ferroelectric gate dielectric portions.

18. The method of claim 17, wherein the different focused ion beam irradiation processes use at least one of different ion doses, beam energies, or beam dwell times from one another.

19. The method of claim 15, wherein: the channel region is between the source region and the drain region; each boundary between an adjacent pair of ferroelectric gate dielectric portions of the plurality of ferroelectric gate dielectric portions extends between the gate electrode and the channel region and is parallel to a straight line connecting a geometric center of the source region and a geometric center of the drain region; and different focused ion beam irradiation processes include scanning a focused ion beam along the straight line.

Images