Large-scale testing of micro-integrated circuits

Abstract

A large-scale testing system for micro integrated circuits includes: a first test area, including multiple test pads and multiple read pads, arranged on a scribe line; multiple test controllers are arranged row by row on the scribe line; a probe is configured to contact the first test area to test multiple rows of integrated circuit chips; each test controller is configured to test each corresponding row of integrated circuit chips row by row; wherein the probe contacts the first test area only once; and multiple read pads are configured to read the test results of each row of integrated circuit chips row by row.

Description

Technical Field

[0001] The invention relates to a system and method for large-scale testing. Background Art

[0002] Today's fine-pitch testing technology mainly uses probe cards to test the pitch limit of about 30-50μm. For micro-ICs, the pitch of the test pads on the micro-ICs has been reduced to less than 13μm, and the traditional probe card can no longer be used for testing. A micro-electromechanical probe card must be used for testing. However, the manufacturing cost of micro-electromechanical probe cards is high.

[0003] On the other hand, when using a traditional probe card to detect ICs on a wafer, each IC must be touched once, and the probe card index time is 1 second. Taking an 8-inch wafer as an example, there are about 44 frames on an 8-inch wafer, and each frame has about 10,000 integrated circuits (ICs). Since each IC must be touched once, it takes more than 100 hours to complete the inspection of a wafer. Therefore, traditional probe cards cannot meet today's high-efficiency inspection needs. Summary of the invention

[0004] In view of this, in order to solve the problem that the current fine pitch detection technology cannot meet the low-cost and high-efficiency micro-IC detection needs, the present invention proposes a micro-IC large-scale testing system and method thereof, which reduces the cost of detection equipment by setting test pads on the scribe line on the wafer and the integrated circuit testing system, and improves the detection efficiency by a large-scale testing method.

[0005] A large-scale testing system for microintegrated circuits according to an embodiment of the present invention is suitable for detecting multiple integrated circuit chips in multiple frames on a substrate, and the system includes: a first test area, including multiple test pads and multiple read pads, arranged on the scribe line; multiple test controllers, arranged row by row on the scribe line; a probe, configured to contact the first test area to test the multiple rows of integrated circuit chips; each of the multiple test controllers is configured to test a row of integrated circuit chips corresponding to the multiple rows of integrated circuit chips row by row; wherein the probe contacts the first test area only once; and the multiple read pads are configured to read the test results of each of the multiple rows of integrated circuit chips row by row.

[0006] A large-scale testing method for micro integrated circuits according to an embodiment of the present invention is suitable for detecting multiple integrated circuit chips in multiple frames on a substrate, and includes the following steps: forming a first test area on a scribe line, wherein the first test area includes multiple test pads and multiple read pads, forming the multiple test pads on the scribe line, and forming the multiple read pads on the scribe line; using a probe to contact the first test area to test the multiple rows of integrated circuit chips; each of the multiple test controllers tests a row of integrated circuit chips corresponding to the multiple rows of integrated circuit chips row by row; wherein the probe only contacts the first test area once; and the multiple read pads read the test results of each of the multiple rows of integrated circuit chips row by row.

[0007] The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide further explanation of the claims of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A-1B is a configuration diagram of a large-scale test system for micro integrated circuits according to an embodiment of the present invention;

[0009] Figure 1C is a circuit configuration diagram of a large-scale test system for microintegrated circuits according to an embodiment of the present invention;

[0010] Figure 2A-2B is an embodiment of a test pad configuration diagram of a first test area according to the present invention;

[0011] Figure 3A-3B It is a detection control architecture of a test controller according to an embodiment of the present invention;

[0012] Figure 4A It is a built-in self-test architecture of a micro integrated circuit chip according to an embodiment of the present invention;

[0013] Figure 4B It is based on the built-in self-test start control in the embodiment of the present invention;

[0014] Figure 4C It is based on the built-in self-test startup and control sequence of the embodiment of the present invention;

[0015] Figures 5A-5B is an embodiment of a schematic diagram of connecting wires according to the present invention;

[0016] Figures 6A-6B It is a flow chart of a large-scale testing method for micro integrated circuits according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient to enable anyone familiar with the relevant technology to understand the technical content of the present invention and implement it accordingly, and according to the contents disclosed in this specification, claims and drawings, anyone familiar with the relevant technology can easily understand the relevant purposes and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any viewpoint.

[0018] Please refer to Figure 1A-1B , which illustrates a configuration diagram of a large-scale test system for micro integrated circuits according to an embodiment of the present invention; please refer to Figure 1A The large-scale testing system 1 includes an integrated circuit chip testing system 10, which is suitable for detecting multiple integrated circuit chips in multiple frames 21 on a substrate 20; in the embodiment, the substrate 20 is a wafer, and the integrated circuit chip 22 is a micro integrated circuit chip (Micro IC); each frame 21 includes multiple rows of integrated circuit chips 22, and multiple integrated circuit chip testing systems 10, and the multiple integrated circuit chip testing systems 10 are arranged row by row on the scribe line 23; the probe 30 is configured to test the large-scale testing system 1.

[0019] Please refer to Figure 1B , the scribe line 23 includes N scribe lines, further including a first scribe line 231, multiple second scribe lines 232 and a third scribe line 233; the integrated circuit chip testing system 10 includes a first test area 101, the first test area 101 includes multiple test pads 11 and multiple read pads 14, which are arranged on the scribe line 23, and the multiple read pads 14 are arranged on the third scribe line 243. In this embodiment, the test pad 11 is arranged on the first scribe line 231, and the multiple read pads 14 are arranged on the third scribe line 243. Multiple test controllers 13 are arranged on the first scribe line 231 and the multiple second scribe lines 232 row by row.

[0020] Please refer to Figure 1C, which illustrates a circuit configuration diagram of a large-scale test system for micro integrated circuits according to another embodiment of the present invention; in the embodiment, each row has M integrated circuit chips 22, including a first integrated circuit chip 22_1, a second integrated circuit chip 22_2... an Mth integrated circuit chip 22_M in each row, a plurality of test controllers 13 including a first test controller 13_1 in the first row, a second test controller 13_2 in the second row... an N-1th test controller 13_N-1 in the N-1th row; the test pad 11 includes a power pad 111, a signal pad 112, a digital pad 113 and a ground pad 114; the power pad 111 is electrically coupled to each integrated circuit chip in the plurality of rows of integrated circuit chips. The chips 22_1~22_M, the signal pad 112 and the digital pad 113 are electrically coupled to the first test controller 13_1 of the first row, and the ground pad 114 is electrically coupled to each integrated circuit chip 22_1~22_M in the multiple rows of integrated circuit chips; each test controller 13 is electrically coupled to each corresponding row of integrated circuit chips; in the detection of each frame, each test controller 13 is configured to test each corresponding row of integrated circuit chips row by row, the first test controller 13_1 tests the corresponding first row of integrated circuit chips, the second test controller 13_2 tests the corresponding second row of integrated circuit chips...the N-1th test controller 13_N-1 tests the corresponding N-1th row of integrated circuit chips.

[0021] Please refer to Figure 1C In an embodiment, each read pad 14 is coupled to a corresponding integrated circuit chip in each row of integrated circuit chips; the multiple read pads 14 include a first read pad 14_1, a second read pad 14_2, ... an Mth read pad 14_M; the first read pad 14_1 is coupled to the first integrated circuit chip 22_1 in each row, the second read pad 14_2 is coupled to the second integrated circuit chip 22_2 in each row, ... the Mth read pad 14_M is coupled to the Mth integrated circuit chip 22_M in each row; the read pads 14 are configured to read the test results of each row of integrated circuit chips row by row.

[0022] Please refer to Figure 2A-2B , which illustrates an embodiment of the test pad configuration diagram of the first test area of ​​the present invention. In the embodiment, please refer to Figure 2A , the power pad 111, the signal pad 112, the digital pad 113 and the ground pad 114 are divided into two groups and respectively arranged on both sides of the first test controller 13_1; in another embodiment, please refer to Figure 2B The power pad 111 , the signal pad 112 , the digital pad 113 , and the ground pad 114 are disposed on the same side of the first test controller 13_1 .

[0023] In the detection of each frame, the probe 30 contacts the first test area 101 once; the probe 30 is configured to contact the power pad 111, the signal pad 112, the digital pad 113, the ground pad 114 and multiple reading pads 14 at the same time; when the large-scale test system 1 detects each row of integrated circuit chips row by row, the reading pad 14 is configured to read the test results of each row of integrated circuit chips row by row; the large-scale test system 1 can complete the row-by-row detection of multiple rows of integrated circuit chips after the probe 30 contacts the first test area 101 once.

[0024] Please refer to Figure 3A-3B , which illustrates the detection control architecture of the test controller in an embodiment of the present invention. The detection control architecture of the test controller can be used to realize the pipeline-type step-by-step startup of the integrated circuit chip.

[0025] In the embodiment, please refer to Figure 3A Each test controller 13 is configured to test each integrated circuit chip 22 in the corresponding row of integrated circuit chips in sequence. Each test controller 13 includes a logic controller 130 and a plurality of shift registers 131. The logic circuit 130 is coupled to the plurality of shift registers 131. Each shift register 131 is coupled to a corresponding integrated circuit chip. Each test controller 13 includes a logic controller 130 and M shift registers 131. The M shift registers 131 are serially connected in sequence, and each shift register 131 is coupled to a corresponding integrated circuit chip. In this embodiment, please also refer to Figure 1C , the first shift register 131_1 in the first test controller 13_1 is coupled to the first integrated circuit chip 22_1 of the first row of integrated circuit chips, the second shift register 131_2 in the first test controller 13_1 is coupled to the second integrated circuit chip 22_2 of the first row of integrated circuit chips, ... the Mth shift register 131_M in the first test controller 13_1 is coupled to the Mth integrated circuit chip 22_M of the first row of integrated circuit chips, ... the first shift register 131_M in the N-1th test controller 13_N-1 is coupled to the Mth integrated circuit chip 22_M of the first row of integrated circuit chips, ... Connected to the first integrated circuit chip of the N-1th row of integrated circuit chips...The Mth shift register 131 of the N-1th row of integrated circuit chips is coupled to the Mth integrated circuit chip of the N-1th row of integrated circuit chips; the test controller of each row is coupled to the test controller of the next row. In this embodiment, the first test controller 13_1 is coupled to the second test controller 13_2, the second test controller 13_2 is coupled to the third test controller 13_3...The N-2th test controller 13_N-2 is coupled to the N-1th test controller 13_N-1.

[0026] After the first test controller 13_1 receives the test signal, the logic controller 130 sequentially activates the shift register 131 to test the first row of integrated circuit chips 22_1 to 22_M; the logic controller 130 activates the first shift register 131_1 to transmit the test signal to the integrated circuit chip 22_1, and the first read pad 14_1 reads the test result of the integrated circuit chip 22_1; then, the logic controller 130 activates the second shift register 131_2 to transmit the test signal to the integrated circuit chip 22_2, and the second read pad 14_2 reads the test result of the integrated circuit chip 22_2...; the logic controller 130 activates the Mth shift register 131_M to transmit the test signal to the integrated circuit chip 22_M, and the Mth read pad 14_M Read the test results of the integrated circuit chip 22_M; when the first test controller 13_1 has finished testing the integrated circuit chips 22_1 to 22_M in the first row, the first test controller 13_1 transmits the test signal to the second test controller 13_2, the logic controller 130 of the second row starts the shift register 131 in sequence to test the integrated circuit chips 22_1 to 22_M in the second row, and the read pad 14 reads the test results of the integrated circuit chips 22_1 to 22_M in the second row in sequence... The logic controller 130 of the N-1th row starts the shift register 131 in sequence to test the integrated circuit chips 22_1 to 22_M in the N-1th row, and the read pad 14 reads the test results of the integrated circuit chips 22_1 to 22_M in the second row in sequence; the test of the first frame is completed.

[0027] For another example, please refer to Figure 3B Each test controller 13 tests each integrated circuit chip 22 in the corresponding row of integrated circuit chips at the same time. Each test controller 13 includes a logic controller 130, a plurality of drivers 132 and a shift register 131. The logic controller 130 is coupled to the plurality of drivers 132 and the shift register 131. Each driver 132 is coupled to a corresponding integrated circuit chip 22. The shift register of each row is coupled to the test controller of the next row. In this embodiment, please also refer to Figure 1C, each row of the test controller includes a logic controller 130, M drivers 132 and a shift register 131, the M drivers 132 are connected in series in sequence, the logic controller 130 is coupled to the first driver 132, and the Mth driver 132 is coupled to the shift register 131; each driver 132 is coupled to the corresponding integrated circuit chip 22; in this embodiment, the first driver 132_1 in the first test controller 13_1 is coupled to the first integrated circuit chip of the first row of integrated circuit chips, the second driver 132_2 is coupled to the second integrated circuit chip of the first row of integrated circuit chips,... the Mth driver 132_M is coupled to the Mth integrated circuit chip of the first row of integrated circuit chips,... the first driver 132_1 in the N-1th test controller 13_N-1 is coupled to the first integrated circuit chip of the N-1th row of integrated circuit chips. The Mth driver 132_M in the N-1th test controller 13_N-1 is coupled to the Mth integrated circuit chip in the N-1th row of integrated circuit chips; the shift register 131 of each row of test controllers 13 is coupled to the test controller 13 of the next row, for example, the shift register 131 of the first test controller 13_1 is coupled to the second test controller 13_2...the shift register 131 of the N-2th test controller is coupled to the shift register 131 of the N-1th test controller 13_N-1.

[0028] After the first test controller 13_1 receives the test signal, the logic controller 130 simultaneously starts the shift register 131 to test the first row of integrated circuit chips 22_1 to 22_M; the logic controller 130 simultaneously starts the drivers 132_1 to 132_M to transmit the test signal to the integrated circuit chips 22_1 to 22_M, and the read pads 14_1 to 14_M read the test results of the integrated circuit chips 22_1 to 22_M; after the first test controller 13_1 finishes testing the first row of integrated circuit chips 22_1 to 22_M, the shift register 131 of the first row transmits The test signal is sent to the second test controller 13_2, the logic controller 130 in the second row simultaneously starts the drivers 132_1~132_M to transmit the test signal to the integrated circuit chips 22_1~22_M, and the read pad 14 reads the test results of the integrated circuit chips 22_1~22_M... The logic controller 130 in the N-1th row simultaneously starts the drivers 132_1~132_M to transmit the test signal to the integrated circuit chips 22_1~22_M, and the read pad 14 reads the test results of the integrated circuit chips 22_1~22_M; the test of the first frame is completed.

[0029] In some embodiments, the integrated circuit chip further includes a built-in self-test architecture. Figures 4A to 4C , Figure 4A The built-in self-test architecture of the integrated circuit chip in the embodiment of the present invention is shown. Figure 4B The built-in self-test start control in an embodiment of the present invention is shown. Figure 4C The built-in self-test activation and control sequence in the embodiment of the present invention is shown; the built-in self-test architecture is set in each integrated circuit chip; when the test controller tests the integrated circuit chip, the built-in self-test in each micro integrated circuit chip will be activated. In the embodiment, please refer to Figure 4A , the test controller inputs the test signal (T) to the power supply 221 in the integrated circuit chip through the shift register 131 to activate the built-in self-test module 222 to test the driver 223, sensor 224 and digital circuit 225 in the micro integrated circuit chip in sequence, output the test result (R), and the read pad reads the test result (R); please refer to Figure 4B , the BIST startup sequence is driver 223 (signals labeled as red, green, blue (R, G, B)), sensor 224 (signals labeled as sense (SEN)), and digital circuit 225 (signals labeled as digital flag (Digital Flag)); please refer to Figure 4C Please also refer to Figure 3A , Figure 4C Shown is a startup reference Figure 3A In the embodiment of the invention, the control sequence of the built-in self-test of the integrated circuit chip 22 is as follows; the built-in self-test of the integrated circuit chip 22_1 is started, and the other integrated circuit chips 22 in the same row are disabled, and the first read pad 14_1 is in accordance with Figure 4B Next, the built-in self-test of the integrated circuit chip 22_2 is started, and the other integrated circuit chips 22 in the same row are disabled, and the second read pad 14_2 is in accordance with Figure 4B The built-in self-test is started sequentially to read the test results ...; the integrated circuit chips 22 in the same row can complete the test in sequence.

[0030] Please refer to Figures 5A-5B , Figures 5A-5B The embodiment of the connection wire schematic diagram according to the present invention is shown. The material of the connection wire between each test controller and each row of integrated circuit chips is selected from the group of metal, polycrystalline and indium tin oxide. In the embodiment, please refer to Figure 5A The connecting wire 15 can be divided into a first section 151 connected to the integrated circuit chip area and a second section 152 connected to the non-integrated circuit chip area, such as the test control area. The material of the first section 151 and the second section 152 is selected from one of metal, polycrystalline and indium tin oxide; in another embodiment, please refer to Figure 5BThe connecting wire 15 can be divided into a first section 151 connected to the integrated circuit chip area and a second section 152 connected to the non-integrated circuit chip area, such as a test control area. A third section 153 is also included between the first section 151 and the second section 152. The materials of the first section 151 and the second section 152 are selected from metals, and the material of the third section 153 is selected from one of polycrystalline and indium tin oxide.

[0031] Please refer to Figure 6A-6B , which depicts a flow chart of a large-scale testing method for micro integrated circuits in an embodiment of the present invention. Fig. 6A , comprising step S1, forming a first test area 101 on the scribe line 23, in an embodiment, forming the first test area 101 on the first scribe line 231 and the third scribe line 233, wherein the first test area 101 comprises a test pad 11 and a read pad 14, the test pad 11 is formed on the first scribe line 231, and the read pad 14 is formed on the third scribe line 233; step S2, forming a plurality of test controllers 13 on the scribe line 23, in an embodiment, forming a plurality of test controllers 13 on the first scribe line 231 and a plurality of second scribe lines 232; step S3, using a probe 30 to contact the first test area 101 to test a plurality of rows of integrated circuit chips; step S4, each test controller 13 tests each row of corresponding integrated circuit chips row by row; wherein the probe 30 contacts the first test area 101 only once; step S5, a plurality of read pads 14 read the test results of each row of integrated circuit chips row by row; step S6, and please also refer to Figure 6B After the reading pad 14 reads the test result of the first frame 211, the probe 30 leaves the first frame 211 and moves to the second test area 102 of the second frame 212. The probe 30 contacts the second test area 12 to test the multiple integrated circuit chips 22 in the second frame 212; wherein the probe 30 contacts the second test area 102 only once.

[0032] Please refer to step S3. In this step, the probe 30 is used to test multiple rows of integrated circuit chips while contacting the power pad 111, the signal pad 113, the digital pad 113, the ground pad 114 and the read pad 14. After the probe 30 contacts the first test area 101, each test controller 13 starts the internal circuit to be tested of each integrated circuit chip 22 with a built-in self-test.

[0033] Please refer to step S5 . In this step, a plurality of read pads 14 are coupled to each row of integrated circuit chips 22 , and each read point 14 is coupled to a corresponding integrated circuit chip 22 in each row of integrated circuit chips.

[0034] In summary, the present invention proposes a micro-IC large-scale testing system and method, which reduces the cost of testing equipment by setting test pads and an integrated circuit testing system on the scribe line on the wafer, and uses a large-scale testing method. The probe only touches the test area in each frame once to detect all the integrated circuit chips in each frame row by row, without having to touch all the integrated circuit chips in each frame. Therefore, the time for detecting all the integrated circuit chips in each frame can be greatly reduced, thereby improving the efficiency of wafer detection.

[0035] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications are within the scope of patent protection of the present invention. Please refer to the attached claims for the scope of protection defined by the present invention.

[0036]

Explanation of symbols

[0037] 1…Large-Scale Testing System

[0038] 10…IC chip test system

[0039] 101…First test area

[0040] 102…Second test area

[0041] 11…Test pad

[0042] 111...Power Pad

[0043] 112…Signal pad

[0044] 113…Number Pad

[0045] 114…Grounding pad

[0046] 13…Test the controller

[0047] 13_1, 13_2...13_N-1...first test controller, second test controller...N-1th test controller

[0048] 130…Logic controller

[0049] 131…Shift register

[0050] 131_1, 131_2...131_M...first shift register, second shift register...Mth shift register

[0051] 132…Driver

[0052] 132_1, 132_2...132_M...first driver, second driver...Mth driver

[0053] 14…Read Pad

[0054] 14_1, 14_2...14_M...first reading pad, second reading pad...Mth reading pad

[0055] 15…Connecting wires

[0056] 151… first paragraph

[0057] 152…Second paragraph

[0058] 153…Paragraph 3

[0059] 20…Substrate

[0060] 21…Frame

[0061] 211…First frame

[0062] 212…Second frame

[0063] 22, 22_1, 22_2...22_M...integrated circuit chips

[0064] 23…Dash

[0065] 231…First dash

[0066] 232…Second dash

[0067] 233…the third dash

[0068] 30…Probe

[0069] T…test signal

[0070] R…Test results

[0071] S1~S6…Steps

Claims

1. A large-scale testing system for micro-integrated circuits, suitable for testing a plurality of integrated circuit chips in a plurality of frames on a substrate, the system comprising: A first test area, including a plurality of test pads and a plurality of read pads, is disposed on the scribe line; Multiple test controllers are arranged row by row on the marking line; a probe configured to contact the first test area to test a plurality of rows of integrated circuit chips; Each of the plurality of test controllers is configured to test a corresponding row of integrated circuit chips in the plurality of rows of integrated circuit chips row by row; wherein the probe contacts the first test area only once; The plurality of read pads are configured to read the test results of each of the plurality of rows of integrated circuit chips row by row.

2. The large-scale testing system for micro integrated circuits according to claim 1, wherein: The plurality of test pads include a power pad, a signal pad, a digital pad and a ground pad.

3. The large-scale testing system for micro integrated circuits according to claim 1, wherein: The plurality of read pads are coupled to each of the plurality of rows of integrated circuit chips, and each of the plurality of read pads is coupled to a corresponding integrated circuit chip in each of the plurality of rows of integrated circuit chips.

4. The large-scale testing system for micro integrated circuits according to claim 2, wherein: The power pad, the signal pad, the digital pad and the ground pad are divided into two groups and are respectively arranged at two sides of a first test controller of the plurality of test controllers.

5. The large-scale testing system for micro integrated circuits according to claim 2, wherein: The power pad, the signal pad, the digital pad and the ground pad are arranged on the same side of a first test controller of the plurality of test controllers.

6. The large-scale testing system for micro integrated circuits according to claim 1, wherein: Each of the plurality of test controllers tests each integrated circuit chip in the corresponding row of integrated circuit chips simultaneously.

7. The large-scale testing system for micro integrated circuits according to claim 1, wherein: Each of the plurality of test controllers is configured to sequentially test each integrated circuit chip in the corresponding row of integrated circuit chips.

8. The large-scale testing system for micro integrated circuits according to claim 1, wherein after the plurality of read pads read the test results of the first test area of ​​the first frame, the probe is configured to move from the first test area of ​​the first frame to the second test area of ​​the second frame, and the probe contacts the second test area to test the plurality of integrated circuit chips in the second frame; wherein, The probe contacts the second test area only once.

9. The large-scale testing system for micro integrated circuits according to claim 1, wherein: After the probe contacts the first test area, each of the plurality of test controllers is configured to perform a built-in self test to activate an internal circuit to be tested of each integrated circuit chip.

10. The large-scale testing system for micro integrated circuits according to claim 1, wherein: Each of the plurality of test controllers includes a logic controller and a plurality of shift registers. The logic controller is coupled to the plurality of shift registers. Each of the plurality of shift registers is coupled to a corresponding integrated circuit chip.

11. The large-scale testing system for micro integrated circuits according to claim 1, wherein: Each of the plurality of test controllers comprises a logic controller, a plurality of drivers and a shift register. The logic controller is coupled to the plurality of drivers and the shift register. Each of the plurality of drivers is coupled to a corresponding integrated circuit chip. The shift register is coupled to a test controller of a next row.

12. The large-scale testing system for micro integrated circuits according to claim 1, wherein: The material of the connecting wires between each of the plurality of test controllers and each of the plurality of rows of integrated circuit chips is selected from the group consisting of metal, polycrystalline and indium tin oxide.

13. A large-scale testing method for micro integrated circuits, suitable for testing a plurality of integrated circuit chips in a plurality of frames on a substrate, comprising the following steps: A first test area is formed on the scribe line, wherein The first test area includes a plurality of test pads and a plurality of read pads; forming a plurality of test controllers on the scribe line; Using probes to contact the first test area to test multiple rows of integrated circuit chips; Each of the plurality of test controllers tests a corresponding row of integrated circuit chips in the plurality of rows of integrated circuit chips row by row; wherein the probe contacts the first test area only once; The plurality of read pads read the test results of each of the plurality of rows of integrated circuit chips row by row.

14. The large-scale testing method for micro integrated circuits according to claim 13, wherein: The plurality of test pads include a power pad, a signal pad, a digital pad and a ground pad.

15. The large-scale testing method for micro integrated circuits according to claim 13, wherein: The plurality of read pads are coupled to each of the plurality of rows of integrated circuit chips, and each of the plurality of read pads is coupled to a corresponding integrated circuit chip in each of the plurality of rows of integrated circuit chips.

16. The large-scale testing method for micro integrated circuits according to claim 13, wherein: Each of the plurality of test controllers is configured to simultaneously test each integrated circuit chip in the corresponding row of integrated circuit chips.

17. The large-scale testing method for micro integrated circuits according to claim 13, wherein: Each of the plurality of test controllers is configured to sequentially test each integrated circuit chip in the corresponding row of integrated circuit chips.

18. The large-scale testing method for micro integrated circuits according to claim 13, wherein: After the probe contacts the first test area, each of the plurality of test controllers uses a built-in self-test to activate the internal circuit to be tested of each integrated circuit chip.

19. The large-scale testing method for micro integrated circuits according to claim 13, wherein: After the read pad reads the test result of the first test area of ​​the first frame, the probe leaves the first test area of ​​the first frame and moves to the second test area of ​​the second frame. The probe contacts the second test area to test multiple integrated circuit chips in the second frame; wherein the probe contacts the second test area only once.

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