electronic devices

Abstract

The present invention provides an electronic device. The electronic device includes a core circuit and a detection circuit. The core circuit receives a first clock signal and a second clock signal, respectively. The core circuit generates a first operating state and a second operating state based on the first clock signal and the second clock signal, respectively. The detection circuit detects the relationship between the first operating state and the second operating state and generates a reset signal. The reset signal is used to reset the relationship between the first operating state and the second operating state to an initial corresponding relationship and eliminate the effects of electromagnetic interference on the electronic device.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to an electronic device capable of overcoming malfunction caused by electromagnetic interference. Background Art

[0002] In today's integrated circuit designs, multiple internal clock domains are often required. Consequently, numerous cross-clock processing mechanisms are employed, such as asynchronous buffer circuits. When asynchronous buffer circuits receive clock signals from different clock sources but at the same frequency, they can operate using a read-only, write-only approach. If the data stream is continuous (such as video data), the buffer circuit continuously writes and reads data, maintaining a consistent relationship between the read and write points and enabling continuous data output.

[0003] When electrostatic discharge (ESD) or electromagnetic interference (EMI) occurs in an integrated circuit (IC), clock signals from different clock sources may experience variations, such as frequency drift, due to varying tolerances to interference. This clock signal variation can disrupt the relationship between read and write operations in the buffer circuit, potentially causing output data errors. Summary of the Invention

[0004] The present invention is directed to an electronic device that can avoid malfunction caused by electromagnetic interference.

[0005] According to an embodiment of the present invention, an electronic device includes a core circuit and a detection circuit. The core circuit receives a first clock signal and a second clock signal, respectively. The core circuit generates a first operating state and a second operating state based on the first clock signal and the second clock signal, respectively. The detection circuit is coupled to the core circuit. The detection circuit detects a relationship between the first operating state and the second operating state and generates a reset signal, wherein the reset signal is used to reset the relationship between the first operating state and the second operating state to an initial corresponding relationship.

[0006] As described above, the electronic device of the present invention can execute different actions and have different operating states based on different clock signals. Furthermore, when the relationship between the operating states changes due to electromagnetic interference, the electronic device of the present invention can provide a reset signal to restore the relationships between the multiple operating states to their normal initial relationships. This prevents malfunctions of the electronic device caused by electromagnetic interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present invention is shown;

[0009] Figure 2A A schematic diagram showing an electronic device according to another embodiment of the present invention;

[0010] Figure 2B The present invention shown Figure 2A A schematic diagram of the operation of the electronic device according to the embodiment;

[0011] Figure 3 A schematic diagram showing an implementation of a detection circuit according to an embodiment of the present invention;

[0012] Figure 4A A schematic diagram showing an electronic device according to another embodiment of the present invention;

[0013] Figure 4B The present invention shown Figure 4A Schematic diagram of detailed operation of the electronic device of the embodiment;

[0014] Figure 5 A schematic diagram illustrating an electronic device according to another embodiment of the present invention.

[0015] Explanation of Figure Numbers

[0016] 100, 200, 400, 500: electronic devices;

[0017] 110, 510: core circuit;

[0018] 120, 220, 300, 430, 520: detection circuit;

[0019] 210: data buffer;

[0020] 310: recorder;

[0021] 320: processor;

[0022] 410: first state machine circuit;

[0023] 420: second state machine circuit;

[0024] 511~51N: sub-circuit;

[0025] 521, 522: counter;

[0026] 523: judgement;

[0027] CKA, CKB: clock signals;

[0028] DATAA, DATAB, DATAC, DATAD: data;

[0029] RP: data readout point;

[0030] RST: reset signal;

[0031] SI1, SI2: reset status;

[0032] ST1, ST2: working status;

[0033] STATEA, STATEB: working status;

[0034] WP: Data write point. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Please refer to Figure 1 , Figure 1 A schematic diagram of an electronic device according to an embodiment of the present invention is shown. The electronic device 100 includes a core circuit 110 and a detection circuit 120. The core circuit 110 receives different clock signals CKA and CKB. The core circuit 110 generates an operating state ST1 and an operating state ST2 based on the clock signals CKA and CKB, respectively. The detection circuit 120 is coupled to the core circuit 110. The core circuit 110 detects the relationship between the operating state ST1 and the operating state ST2 to generate a reset signal RST. In this embodiment, the core circuit 110 performs two different operations based on the clock signals CKA and CKB, respectively. The two different operations corresponding to the clock signals CKA and CKB can have operating states ST1 and ST2, respectively. Under normal conditions, the operating states ST1 and ST2 in the core circuit 110 have a predetermined initial corresponding relationship. In actual applications, as the electronic device 100 operates, either the clock signal CKA or the clock signal CKB may experience a certain degree of frequency drift due to electromagnetic interference (EMI) such as electrostatic discharge (ESD). This frequency drift may cause an error in at least one of the operating states ST1 and ST2, causing the relationship between the operating states ST1 and ST2 to differ from the initial relationship, thereby causing the core circuit 110 to malfunction.

[0037] In this embodiment, the clock signal CKA and the clock signal CKB may come from different clock sources.

[0038] In this embodiment, when the detection circuit 120 determines that the relationship between the operating states ST1 and ST2 is different from the initial corresponding relationship, a reset signal RST is generated accordingly. The reset signal RST is transmitted to the core circuit 110 and used to reset the relationship between the operating states ST1 and ST2 to the initial corresponding relationship. In this way, the core circuit 110 can resume normal operation and eliminate the possibility of malfunction. Furthermore, when the detection circuit 120 determines that the relationship between the operating states ST1 and ST2 is the same as the initial corresponding relationship, the core circuit 110 maintains normal operation.

[0039] Please refer to the following Figure 2A , Figure 2A A schematic diagram of an electronic device according to another embodiment of the present invention is shown. The electronic device 200 includes a data buffer 210 and a detection circuit 220 as core circuits. The data buffer 210 obtains a data write point WP and a data read point RP according to a clock signal CKA and a clock signal CKB, respectively, wherein the data buffer 210 can perform a data write operation according to the data write point WP, and the data buffer 210 can perform a data read operation according to the data read point RP. The data write point WP can correspond to a first physical address of the data buffer 210, and the data read point RP can correspond to a second physical address of the data buffer 210. The first physical address and the second physical address can be the same or different. The data write operation and the data read operation of the data buffer 210 can be performed simultaneously.

[0040] In this embodiment, the data write point WP and the data read point RP may serve as two working states corresponding to the clock signals CKA and CKB in the data buffer 210 .

[0041] Under normal circumstances, the first physical address and the second physical address corresponding to the data write point WP and the data read point RP, respectively, cannot be the same. This is because, if the data write point WP and the data read point RP correspond to the same physical address, it may be difficult to determine whether the data read during the data read operation is old data or newly written data, and it may even be possible to read a mixture of old and new data.

[0042] In this embodiment, under normal conditions, the data write point WP and the data read point RP have an initial correspondence. During operation, the electronic device 200 can cause the detection circuit 220 to receive information related to the data write point WP and the data read point RP and detect whether the initial correspondence between the data write point WP and the data read point RP is maintained. In this embodiment, the so-called initial correspondence can be the difference between the first physical address and the second physical address corresponding to the data write point WP and the data read point RP, respectively. For example, to ensure stable read and write operations, the first physical address corresponding to the data write point WP can be set to a predetermined standard value, with the address difference between the first physical address corresponding to the data read point RP and the second physical address corresponding to the data read point RP.

[0043] Please refer to the following Figure 2B The present invention shown Figure 2A Schematic diagram of the operation of an electronic device according to an embodiment. When electronic device 200 is affected by electromagnetic interference, the first and second physical addresses corresponding to the data write point WP and the data read point RP become identical. Consequently, detection circuit 220 detects that the address difference between the first and second physical addresses is zero (different from the preset standard value), and determines that the relationship between the data write point WP and the data read point RP is different from the initial correspondence. Simultaneously, detection circuit 220 generates a reset signal RST to reset the data write point WP and the data read point RP, restoring their initial correspondence.

[0044] In this way, the detection circuit 220 can detect whether the address difference has changed and generate a reset signal RST to restore the address difference between the first physical address and the second physical address when the address difference has changed, so as to maintain normal reading and writing operations of the data buffer 210.

[0045] Please refer to the following Figure 3 , Figure 3 FIG. 3 is a schematic diagram showing an embodiment of a detection circuit according to an embodiment of the present invention. The detection circuit 300 can be used to implement Figure 2A 、 2B The detection circuit 300 includes a recorder 310 and a processor 320. The recorder 310 can record a preset standard value. The recorder 310 can also receive a data write point WP and a data read point RP from the core circuit. The processor 320 receives the preset standard value, the data write point WP, and the data read point RP. The processor 320 obtains a first physical address and a second physical address corresponding to the data write point WP and the data read point RP, respectively. The processor 320 determines whether the address difference between the first physical address and the second physical address is equal to the preset standard value to generate a reset signal RST.

[0046] In terms of hardware architecture, recorder 310 can be any form of memory. Processor 320 can be a processor with computing capabilities. Alternatively, processor 320 can be a hardware circuit designed using a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented using a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

[0047] Please refer to the following Figure 4A , Figure 4A A schematic diagram of an electronic device according to another embodiment of the present invention is shown. Electronic device 400 includes a first state machine circuit 410, a second state machine circuit 420, and a detection circuit 430. First state machine circuit 410 and second state machine circuit 420 may be core circuits and receive clock signals CKA and CKB, respectively, to perform operations. First state machine circuit 410 may operate in an operating state STATEA based on clock signal CKA. Meanwhile, second state machine circuit 420 may operate in an operating state STATEB based on clock signal CKB.

[0048] The detection circuit 430 is coupled to the first state machine circuit 410 and the second state machine circuit 420. The detection circuit 430 detects whether the relationship between the operating state STATEA of the first state machine circuit 410 and the operating state STATEB of the second state machine circuit 420 at the same time point meets an initial corresponding relationship, thereby generating a reset signal RST. When the relationship between the operating state STATEA of the first state machine circuit 410 and the operating state STATEB of the second state machine circuit 420 does not meet the initial corresponding relationship, the detection circuit 430 may generate the reset signal RST to reset the first state machine circuit 410 and the second state machine circuit 420 and restore the relationship between the operating state STATEA of the first state machine circuit 410 and the operating state STATEB of the second state machine circuit 420 to the initial corresponding relationship. Conversely, when the relationship between the operating state STATEA of the first state machine circuit 410 and the operating state STATEB of the second state machine circuit 420 remains the same as the initial corresponding relationship, the first state machine circuit 410 and the second state machine circuit 420 maintain normal operation.

[0049] about Figure 4AIn the embodiment, the implementation details of the electronic device 400 can be found in Figure 4B The present invention shown Figure 4A Detailed operational diagram of an electronic device according to an embodiment. First state machine circuit 410 and second state machine circuit 420 are activated from reset states SI1 and SI2 in response to reset signal RST. First state machine circuit 410 cycles sequentially between states A and D in response to clock signal CKA. Second state machine circuit 420 cycles sequentially between states 1 and 4 in response to clock signal CKB.

[0050] In terms of operation details, under normal conditions, based on clock signals CKA and CKB, when the first state machine circuit 410 is in state A, it can write data DATAA to the buffer corresponding to state 3 in the second state machine circuit 420, while the second state machine circuit 420 reads the data stored in the buffer corresponding to state 1 (data read operation) when it is in state 1; when the first state machine circuit 410 is in state B, it can write data DATAB to the buffer corresponding to state 4 in the second state machine circuit 420, while the second state machine circuit 420 reads the data stored in the buffer corresponding to state 2 when it is in state 2. ; when the first state machine circuit 410 is in state C, the data DATAC can be written to the buffer corresponding to state 1 in the second state machine circuit 420, and the second state machine circuit 420 can read the data stored in the buffer corresponding to state 3 when it is in state 3 (data read action); and, when the first state machine circuit 410 is in state D, the data DATAD can be written to the buffer corresponding to state 2 in the second state machine circuit 420, and the second state machine circuit 420 can read the data stored in the buffer corresponding to state 4 when it is in state 4 (data read action).

[0051] According to the above, under normal conditions, the first state machine circuit 410 and the second state machine circuit 420 can maintain executing data read and write operations on different registers respectively, so that read and write conflicts do not occur.

[0052] When electrostatic discharge (ESD) or other external electromagnetic interference (EMI) occurs, the clock signals CKA and CKB may vary, causing the relationship between the operating states of the first state machine circuit 410 and the second state machine circuit 420 to vary. The detection circuit 430 generates a reset signal RST by detecting whether the relationship between the operating states STATEA and STATEB maintains the initial corresponding relationship. Furthermore, if the relationship between the states STATEA and STATEB differs from the initial corresponding relationship, the detection circuit 430 activates the reset signal RST, causing the first state machine circuit 410 and the second state machine circuit 420 to be reset to reset states SI1 and SI2, respectively, and resume normal operation based on the clock signals CKA and CKB, respectively.

[0053] It is worth mentioning that Figure 4B In the embodiment, the first state machine circuit 410 may further include one or more states in addition to state A to state D. Similarly, the second state machine circuit 420 may further include one or more states in addition to state 1 to state 4. Figure 4B The number of states of the first state machine circuit 410 and the second state machine circuit 420 is only for convenience of description and is not intended to limit the scope of the present invention.

[0054] Please refer to the following Figure 5 , Figure 5 A schematic diagram of an electronic device according to another embodiment of the present invention is shown. Electronic device 500 includes a core circuit 510 and a detection circuit 520. Core circuit 510 comprises multiple sub-circuits 511-51N. Each of sub-circuits 511-51N receives clock signals CKA and CKB and operates based on these signals. Detection circuit 520, coupled to core circuit 510, receives clock signals CKA and CKB, and generates a reset signal RST by determining whether the frequency relationship between clock signals CKA and CKB is equal to the initial corresponding relationship.

[0055] The detection circuit 520 can count clock signals CKA and CKB and determine the frequency relationship between clock signals CKA and CKB based on the respective count values ​​obtained. The detection circuit 520 includes counters 521 and 522 and a determiner 523. Counters 521 and 522 receive clock signals CKA and CKB, respectively, and perform counting operations based on the clock signals CKA and CKB to generate a first count value and a second count value, respectively. The frequencies of the clock signals CKA and CKB can have a proportional relationship, which can be greater than 1, equal to 1, or less than 1. The determiner 523 can be a divider in a digital circuit and divide the first count value and the second count value to determine the current frequency relationship between the clock signals CKA and CKB. The determiner 523 generates a reset signal RST by comparing the current frequency relationship with the initial corresponding relationship.

[0056] In this embodiment, the counters 521 and 522 can be implemented by counters of any form of digital circuits without any particular limitation.

[0057] As described above, the electronic device of the present invention detects the different operating states of the core circuitry in response to different clock signals and performs a reset operation by detecting whether the relationship between these operating states conforms to a predetermined correspondence. Thus, if any clock signal distorts due to electromagnetic interference, causing the relationship between the core circuitry's operating states to become abnormal, a reset signal can be used to correct the abnormality in real time. This prevents the electronic device from malfunctioning due to electrostatic discharge or other types of external interference, maintaining normal operation of the electronic device.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device comprising: A core circuit receives a first clock signal and a second clock signal, and generates a first working state and a second working state according to the first clock signal and the second clock signal, respectively; as well as a detection circuit coupled to the core circuit, detecting a relationship between the first working state and the second working state to generate a reset signal, wherein the reset signal is used to reset the relationship between the first working state and the second working state to an initial corresponding relationship; The first working state and the second working state correspond to operations performed on the data buffer according to the first physical address and the second physical address, The initial corresponding relationship between the first physical address and the second physical address is that the address difference between the first physical address and the second physical address is equal to a preset standard value.

2. The electronic device according to claim 1, wherein the core circuit includes the data buffer, the data buffer obtains a data write point and a data read point according to the first clock signal and the second clock signal respectively, performs a data write action according to the data write point, and simultaneously performs a data read action according to the data read point, wherein the data write point and the data read point correspond to the first physical address and the second physical address of the data buffer respectively, the detection circuit compares the data write point and the data read point to generate the reset signal, and the detection circuit provides the reset signal to reset the data write point and the data read point to the initial data write point and the initial data read point respectively. 3 . The electronic device according to claim 2 , wherein at the same time point, the detection circuit determines whether the address difference is equal to the preset standard value to generate the reset signal. 4 . The electronic device according to claim 3 , wherein at the same time point, when the address difference is not equal to the preset standard value, the detection circuit generates the reset signal.

5. The electronic device according to claim 2, wherein the detection circuit comprises: A recorder, used to record the preset standard value; as well as The processor is coupled to the recorder and the data buffer, and determines whether the address difference is equal to the preset standard value to generate the reset signal.

6. The electronic device according to claim 2, wherein the core circuit comprises: a first state machine circuit, operating in the first working state according to the first clock signal; as well as A second state machine circuit operates in the second working state according to the second clock signal, The detection circuit detects whether the relationship between the first working state of the first state machine circuit and the second working state of the second state machine circuit at the same time point conforms to the initial corresponding relationship to generate a reset signal.

7. An electronic device according to claim 6, wherein at the same time point, the first working state of the first state machine circuit performs a data write action on one of the multiple buffers of the second state machine circuit, and the second working state of the second state machine circuit performs a data read action on another one of the multiple buffers of the second state machine circuit. The electronic device according to claim 6 , wherein the detection circuit records the initial corresponding relationship.

9. The electronic device according to claim 1 , wherein the core circuit comprises a plurality of sub-circuits, each of the plurality of sub-circuits receiving the first clock signal and the second clock signal to operate. The detection circuit determines whether the frequency relationship between the first clock signal and the second clock signal is equal to the initial corresponding relationship to generate the reset signal. The detection circuit provides the reset signal to the plurality of sub-circuits to reset the plurality of sub-circuits.

10. The electronic device according to claim 8, wherein the detection circuit comprises: a first counter, performing a counting action according to the first clock signal to generate a first count value; a second counter, performing a counting operation according to the second clock signal to generate a second count value; as well as The determiner is coupled to the first counter and the second counter, obtains the current frequency relationship between the first clock signal and the second clock signal according to the first count value and the second count value, and generates the reset signal by comparing the current frequency relationship with the initial corresponding relationship.

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