A memory chip testing method and apparatus

Abstract

The application discloses a kind of storage chip test method and device, method includes: obtaining host computer instruction, read the type of each storage chip, respectively to each first type storage chip is carried out first test, respectively to each second type storage chip is carried out second test;First test is written to the test data of each address space of storage chip and is verified, after verification, read all the saved data of storage chip and compare with test data, the consistent comparison result is passed in test;Second test first erases target storage chip, then write the test data of each address space of storage chip and verify, after verification, read all the saved data of storage chip and compare with test data, the consistent comparison result is passed in test.The application can automatically complete for the full disk test of storage chip, and using the mechanism of double determination to improve the reliability of test result, test progress and test result can also be reported in real time.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing, and more particularly to a memory chip testing method and apparatus. Background Technology

[0002] Memory chips are used to store important information such as user programs, data, and even keys. Current manufacturing processes cannot guarantee that all produced memory chips will function correctly; some defective chips end up on the market. Using these defective chips in production can lead to serious consequences such as program malfunctions, data corruption, or even system crashes. Therefore, it is necessary to conduct comprehensive testing before using memory chips to ensure they are functioning properly. Summary of the Invention

[0003] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a memory chip testing method and device, which can test various types of memory chips, effectively locate fault points and report them, and provide a reliable basis for subsequent fault resolution.

[0004] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0005] A method for testing memory chips, applied to a memory chip testing device, the memory chip testing device including a host computer and a DSP unit interconnected, the DSP unit being connected to at least two memory chips to be tested, the method including the step of the DSP unit testing the memory chips, specifically including:

[0006] Obtain and parse the host computer instructions. If it is to start a test, read the hardware information of each storage chip to obtain the type of each storage chip.

[0007] If a first type of memory chip exists, a first test is performed for each first type of memory chip. The steps of the first test include: sequentially writing test data into the space of each address of the target memory chip and verifying it; if there is an address that fails verification, generating a test result of test error for the address information and reporting it to the host computer; if each address passes verification, reading all the saved data of the target memory chip and comparing it with the corresponding test data; if the saved data is inconsistent with the corresponding test data, generating a test result of test error for the address corresponding to the saved data and reporting it to the host computer; if all the saved data is consistent with the corresponding test data, reporting a test result of test success to the host computer.

[0008] If a second type of memory chip exists, a second test is performed for each second type of memory chip. The steps of the second test include: erasing the target memory chip, writing test data into the space of each address of the target memory chip in sequence and verifying it; if there is an address that fails verification, generating a test result of test error for the address information and reporting it to the host computer; if each address passes verification, reading all the saved data of the target memory chip and comparing it with the corresponding test data; if the saved data is inconsistent with the corresponding test data, generating a test result of test error for the address corresponding to the saved data and reporting it to the host computer; if all the saved data is consistent with the corresponding test data, reporting a test result of test success to the host computer.

[0009] Furthermore, the steps of writing test data to each address space of the target memory chip sequentially and verifying it specifically include:

[0010] Select the current data as the test data, and use the current address space of the target memory chip as the target address space;

[0011] Write the test data into the space of the target address, read the saved data in the space of the target address within a preset time. If the saved data and the test data are the same, the verification is successful and the next step is executed. If the saved data and the test data are different, the verification is unsuccessful. Record the target address and execute the step of generating a test result of the test error from the information of the address and reporting it to the host computer.

[0012] Use the next data as the test data, and make sure the next data is different from the current data. Use the space of the next address of the target memory chip as the space of the target address, and return to the previous step until the address space of the target memory chip has been traversed.

[0013] Furthermore, before using the next data as test data, the process includes obtaining the next data step, specifically: incrementing the value of the current data by one to obtain the next data.

[0014] Furthermore, if the saved data and the test data are the same, the test data is also saved to the first data set; the step of reading all the saved data from the storage chip and comparing it with the corresponding written data specifically includes:

[0015] Read the corresponding data from all address spaces of the target memory chip and save it to the second data set;

[0016] Select and save data from the second data set, and match the corresponding test data from the first data set according to the address of the saved data;

[0017] Compare the saved data with the corresponding test data. If the saved data and the corresponding test data are the same, execute the step of selecting saved data from the second data set until all saved data in the second data set has been selected. If the saved data and the corresponding test data are not the same, execute the step of generating a test result of the test error from the information of the address corresponding to the saved data and reporting it to the host computer.

[0018] Furthermore, after erasing the target memory chip, the following steps are also included: if the erasure is successful, test data is written to the space of each address of the memory chip in sequence and verified; if the erasure fails, the test result of the erasure failure is reported to the host computer.

[0019] Furthermore, the method also includes a step of interaction between the host computer and the DSP unit, specifically including:

[0020] Generate a host computer instruction to start the test, and send the host computer instruction to the DSP unit;

[0021] Wait for and obtain the test results reported by the DSP unit. If the test is passed, mark the corresponding memory chip as having passed the test; if the test is incorrect, mark the corresponding memory chip as having failed the test, and record the address information in the test results; if the erase failure notification is received, mark the corresponding memory chip as having failed to erase.

[0022] Furthermore, the interaction steps between the host computer and the DSP unit also include: generating a host computer command to stop the test and sending it to the DSP unit;

[0023] The steps for DSP unit testing of memory chips also include: obtaining and parsing instructions from the host computer; if the instruction is to stop the test, ending and exiting.

[0024] This invention also proposes a memory chip testing device, comprising a DSP unit, a bridging unit, a communication unit, and a host computer connected in sequence, wherein the DSP unit is further connected to at least two memory chips to be tested, wherein:

[0025] The host computer is used to generate a host computer instruction to start the test, and send the host computer instruction to the DSP unit through the communication unit. It is also used to wait for and obtain the test results reported by the DSP unit through the communication unit. If the test is passed, the corresponding memory chip is marked as having passed the test; if the test is incorrect, the corresponding memory chip is marked as having failed the test, and the address information in the test results is recorded; if the notification is of erase failure, the corresponding memory chip is marked as having failed to erase.

[0026] The communication unit is used to send the host computer instructions to the DSP unit through the bridging unit, and is also used to obtain the test results reported by the DSP unit through the bridging unit, and report the test results reported by the DSP unit to the host computer.

[0027] The DSP unit is used to obtain and parse instructions from the host computer through the communication unit. If the instruction is to start a test, corresponding tests are performed according to the type of each memory chip. If the memory chip is of type 1, test data is written to and verified for each address space of the memory chip in sequence. If the memory chip is of type 2, after erasing the memory chip, if the erasure is successful, the steps of writing test data to and verifying for each address space of the memory chip in sequence are executed. If the erasure fails, the test result of the erase failure is reported to the host computer in sequence through the bridging unit and the communication unit. After writing test data to and verifying for each address space of the memory chip in sequence, if there are addresses that fail verification, the information of the addresses is used to generate test error results, which are reported to the host computer in sequence through the bridging unit and the communication unit. If each address passes verification, all the saved data of the memory chip is read and compared with the corresponding test data. If the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate test error results, which are reported to the host computer in sequence through the bridging unit and the communication unit. If all the saved data is consistent with the corresponding test data, the test result of the test passing is reported to the host computer in sequence through the bridging unit and the communication unit.

[0028] Furthermore, when writing test data to and verifying each address space of the target memory chip sequentially, the DSP unit is specifically used for:

[0029] Select the current data as the test data, and use the current address space of the memory chip as the target address space;

[0030] The test data is written into the space of the target address. The saved data in the space of the target address is read within a preset time. If the saved data and the test data are the same, the verification is passed. The next data is selected as the test data. If the next data is different from the current data, the space of the next address of the target memory chip is used as the target address space. The step of writing the test data into the space of the target address is executed until the address space of the target memory chip is traversed. If the saved data and the test data are different, the verification is failed. The target address is recorded and the test result of generating the test error information of the address is executed and reported to the host computer.

[0031] Furthermore, the DSP unit is also used to save the test data to a first data set when the saved data and test data are the same, and to read all the saved data from the memory chip and compare it with the corresponding written data. Specifically, the DSP unit is used for:

[0032] Read the corresponding data from all address spaces of the memory chip and save it to the second data set;

[0033] Select and save data from the second data set, and match the corresponding test data from the first data set according to the address of the saved data;

[0034] Compare the saved data with the corresponding test data. If the saved data and the corresponding test data are the same, execute the step of selecting saved data from the second data set until all saved data in the second data set has been selected. If the saved data and the corresponding test data are not the same, execute the step of generating a test result of the test error from the information of the address corresponding to the saved data and reporting it to the host computer.

[0035] Compared with the prior art, the advantages of the present invention are as follows:

[0036] This invention can automatically complete a full-disk test of a memory chip and employs a dual-judgment mechanism. First, data is written to each address space of the target memory chip to verify the write operation's validity. Second, all data on the target memory chip is read and compared with the corresponding written data to determine the read operation's validity, thereby improving the reliability of the test results. Furthermore, this invention can report the test progress and test results for each memory chip in real time, allowing users to easily understand the test progress and accurately identify the cause and location of any failed tests. Attached Figure Description

[0037] Figure 1 This is a functional logic block diagram of the memory chip testing device according to Embodiment 1 of the present invention.

[0038] Figure 2 This is a functional relationship diagram of the DSP unit in Embodiment 1 of the present invention.

[0039] Figure 3 This is an overall flowchart of the DSP unit testing memory chip in Embodiment 1 of the present invention.

[0040] Figure 4 This is a flowchart of the DSP unit testing the EEPROM chip in Embodiment 1 of the present invention.

[0041] Figure 5 This is a flowchart of the DSP unit testing the Flash chip in Embodiment 1 of the present invention.

[0042] Figure 6 This is an overall flowchart of the DSP unit testing memory chip in Embodiment 3 of the present invention. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0044] Example 1

[0045] like Figure 1 As shown, this embodiment proposes a memory chip testing device, including a DSP unit, a bridge unit, a communication unit, and a host computer connected in sequence. The DSP unit is also connected to at least two memory chips to be tested. These memory chips to be tested can be of the same type, such as all EEPROM memory chips or all Flash memory chips, or they can be of different types, such as some being EEPROM memory chips and the other being Flash memory chips. The DSP unit provides a corresponding data read / write interface for each memory chip to be tested. Considering that these memory chips to be tested will be installed on other devices later, this embodiment configures a corresponding chip socket for each memory chip to be tested. Thus, the memory chips to be tested can be installed on the chip socket by a detachable connection such as plug-and-play connection, which facilitates the removal, placement, and replacement of a new batch of memory chips for testing. Each read / write interface of the DSP unit is connected to the corresponding chip socket, and data read / write is performed through each chip socket and the corresponding memory chip.

[0046] In this embodiment, the DSP unit uses an FT-C6416 processor, configured to perform testing functions, driver configuration functions, and serial communication functions. The testing functions mainly include testing the EEPROM and Flash memory chips separately. Figure 2 As shown, the driver configuration function mainly includes configuring the interfaces provided by the EEPROM storage chip and the Flash storage chip, as well as the serial port interface. The serial communication function mainly includes receiving instructions from the host computer and reporting the detection results. The configuration process of the driver configuration function and the serial communication function is not the focus of this embodiment and will not be described in detail here.

[0047] In this embodiment, the bridging unit uses a CPLD, and the communication unit uses an ST16C554QFP64 chip. The CPLD communicates with the DSP unit via the EMIF bus and with the ST16C554QFP64 via a bus defined by the ST16C554QFP64, thus bridging the DSP unit and the ST16C554QFP64. The ST16C554QFP64 communicates with the host computer via an RS232-C interface and with the DSP unit through the CPLD bridging, thereby sending host computer commands to the DSP unit via the CPLD, acquiring test results reported by the DSP unit via the CPLD, and reporting the test results reported by the DSP unit to the host computer.

[0048] In this implementation, the host computer generates a host computer instruction to start the test and sends the host computer instruction to the DSP unit through the communication unit. Then, it waits for and obtains the test results reported by the DSP unit through the communication unit. If the test is passed, the corresponding memory chip is marked as having passed the test; if the test is incorrect, the corresponding memory chip is marked as having failed the test, and the address information in the test results is recorded; if the notification is of erase failure, the corresponding memory chip is marked as having failed to erase.

[0049] In this embodiment, the DSP unit is used to obtain and parse instructions from the host computer through the communication unit. If the instruction is to start a test, corresponding tests are performed according to the type of each memory chip. If the type of memory chip is an EEPROM memory chip (hereinafter referred to as the first type), then an EEPROM memory chip test is performed. If the type of memory chip is a Flash memory chip (hereinafter referred to as the second type), then a Flash memory chip test is performed. After each memory chip is tested, the corresponding test results are reported to the host computer in sequence through the bridging unit and the communication unit, thereby reporting the test progress and the test results of each memory chip in real time, so that the user can know the test progress.

[0050] In this embodiment, the EEPROM storage chip testing scheme is as follows: single-byte data is sequentially written into the designated address space of the EEPROM storage chip, and data is read from these designated address spaces within a specified number of read operations. It is determined whether the read and write data of each address space are the same to determine whether the write operation of the storage chip is normal. If the data read from each address space is the same as the corresponding write data within the specified number of read operations, then all the data in the designated address spaces are read out, and these data are compared one by one with the corresponding write data to determine whether the read operation of the storage chip is normal.

[0051] In this embodiment, the Flash memory chip testing scheme is as follows: erase the Flash memory chip, then write single-byte data into the specified address space of the Flash memory chip in sequence, and read data from these specified address spaces within a specified number of read operations. Determine whether the read and write data of each address space are the same to determine whether the write operation of the memory chip is normal. If the data read from each address space is the same as the corresponding write data within the specified number of read operations, then read the data in all specified address spaces and compare these data one by one with the corresponding write data to determine whether the read operation of the memory chip is normal.

[0052] It can be seen that the testing schemes for EEPROM memory chips and Flash memory chips are basically the same. The difference is that the Flash memory chip test requires erasing the chip first.

[0053] Therefore, in this embodiment, the DSP unit is configured to perform:

[0054] If the storage chip is of type 1, for each address of the storage chip, the step of writing test data to the space of that address and verifying it within a preset number of times is executed sequentially. If the storage chip is of type 2, after erasing the storage chip, if the erasure is successful, for each address of the storage chip, the step of writing test data to the space of that address and verifying it within a preset number of times is executed sequentially. If the erasure fails, the test result of the erasure failure is reported to the host computer through the bridging unit and the communication unit in sequence.

[0055] For each address of the memory chip, after sequentially performing the steps of writing test data to the space of that address and verifying it within a preset number of times, if there is an address that fails verification, the information of the address that fails verification is used to generate a test error result, and then reported to the host computer through the bridging unit and the communication unit in sequence.

[0056] If each address passes verification, all stored data in the memory chip is read and compared with the corresponding test data. If the stored data is inconsistent with the corresponding test data, the information of the address corresponding to the stored data is used to generate a test result of the test error, and the result is reported to the host computer through the bridging unit and the communication unit in sequence.

[0057] If all the saved data is consistent with the corresponding test data, the test result of passing the test is reported to the host computer through the bridging unit and the communication unit in sequence.

[0058] In this embodiment, when performing the step of writing test data to the space of each address of the memory chip and verifying it within a preset number of times, the DSP unit is specifically used for:

[0059] Select the current data as the test data, and use the current address space of the memory chip as the target address space;

[0060] The test data is written into the target address space. The saved data in the target address space is read within a preset time. If the saved data and the test data are the same, the verification is successful. The next data is selected as the test data. If the next data is different from the current data, the space of the next address of the target memory chip is used as the target address space. The step of writing the test data into the target address space is executed until the address space of the target memory chip is traversed. If the saved data and the test data are different, and the number of times the corresponding target address space is read has not reached a preset threshold, the step of reading the saved data in the target address space within a preset time is executed. If the number of times the corresponding target address space is read reaches the preset threshold, the verification fails. The corresponding target address is used as the address of verification failure. The step of generating a test error result for the address of verification failure and reporting it to the host computer is executed.

[0061] In this embodiment, the DSP unit is also used to save the test data to a first data set when the saved data and test data are the same, and to read all the saved data from the memory chip and compare it with the corresponding written data. Specifically, the DSP unit is used for:

[0062] Read the corresponding data from all address spaces of the memory chip and save it to the second data set;

[0063] Select and save data from the second data set, and match the corresponding test data from the first data set according to the address of the saved data;

[0064] Compare the saved data with the corresponding test data. If the saved data and the corresponding test data are the same, execute the step of selecting saved data from the second data set until all saved data in the second data set has been selected. If the saved data and the corresponding test data are not the same, execute the step of generating a test result of the test error from the information of the address corresponding to the saved data and reporting it to the host computer.

[0065] like Figure 3 As shown, based on the memory chip testing apparatus of this embodiment, this embodiment also proposes a memory chip testing method, including the step of testing the memory chip with a DSP unit, specifically including:

[0066] S1) Obtain and parse the host computer instructions. If it is to start the test, read the hardware information of each memory chip to obtain the type of each memory chip.

[0067] S2) If a first type of memory chip exists, perform EEPROM memory chip testing for each first type of memory chip. The EEPROM memory chip testing steps include: for each address of the target memory chip, sequentially write test data into the space of the address and verify it within a preset number of times. If there is an address that fails verification, generate a test error result for the address that fails verification and report it to the host computer. If each address passes verification, read all the saved data of the target memory chip and compare it with the corresponding test data. If the saved data is inconsistent with the corresponding test data, generate a test error result for the address corresponding to the saved data and report it to the host computer. If all the saved data is consistent with the corresponding test data, report the test result that passes the test to the host computer.

[0068] S3) If a second type of memory chip exists, perform Flash memory chip testing for each second type of memory chip. The Flash memory chip testing steps include: erasing the target memory chip; for each address of the target memory chip, sequentially writing test data into the space of the address and verifying it within a preset number of times; if there is an address that fails verification, generating a test error result for the address that fails verification and reporting it to the host computer; if each address passes verification, reading all the saved data of the target memory chip and comparing it with the corresponding test data; if the saved data is inconsistent with the corresponding test data, generating a test error result for the address corresponding to the saved data and reporting it to the host computer; if all the saved data is consistent with the corresponding test data, reporting a test pass result to the host computer.

[0069] Through the above steps, the DSP unit performs unified testing on memory chips of the same type. The memory chip testing employs a dual-judgment mechanism. First, test data is written to each address space of the target memory chip and verified within a preset number of times to determine if the write operation is normal. Second, all stored data of the target memory chip is read and compared with the corresponding test data to determine if the read operation is normal. This embodiment verifies both write and read operations separately, thereby improving the reliability of the test results. Furthermore, by reporting the test progress and the test results for each memory chip in real time, users can easily understand the test progress and accurately identify the cause and location of any failed tests.

[0070] like Figure 4As shown, in this embodiment, the test is conducted using the domestically produced chip JM28LV256, with a capacity of 256Kb, as an example of the target memory chip of the first type, namely the EEPROM memory chip. Before the test, the 8-bit data to be written to the EEPROM needs to be initialized. This data is an integer starting from 0 and incrementing by 1. The DSP unit accesses the corresponding EEPROM through the EMIF bus, and the logical address range allocated to the EEPROM is 0x60000000~0x60040000. First, write the number 0 to address 0x60000000. Then, within a specified number of read operations, read data from address 0x60000000 and check if the result is 0. If none of the data is 0, the write test for address space 0x60000000 is considered an error, and the test result is reported to the host computer. The EEPROM test then ends. If the result is 0, write the number 1 to address 0x60000001, and then perform read and write checks in the same way. This process is repeated until all write tests for addresses 0x60000000 to 0x60040000 pass or a write test error occurs. If all write tests pass, read all data from addresses 0x60000000 to 0x60040000 at once, and check if each read data is equal to the corresponding written data. If they are equal, the EEPROM test is considered passed. Otherwise, the read test for the corresponding address space of the EEPROM is considered an error.

[0071] like Figure 5As shown, in this embodiment, the test is conducted using the domestically produced CX29LV160 chip with a capacity of 16Mb, specifically the second type of target memory chip, i.e., the Flash memory chip. Before testing, the Flash chip needs to be erased, and then the 8-bit data to be written to the Flash is initialized. This data starts from 0 and increments by 1. The DSP unit accesses the corresponding Flash via the EMIF bus, and the logical address range allocated to the Flash is 0x64000000 to 0x65000000. First, write the number 0 to address 0x64000000. Then, within a specified number of read operations, read data from address 0x64000000 and check if the result is 0. If none of the data is 0, a write test error is considered to have occurred at address 0x64000000, and the test result is reported to the host computer. The Flash test then ends. If the result is 0, write the number 1 to address 0x64000001, and repeat the same read / write check. This process continues until all write tests from 0x64000000 to 0x65000000 have passed or a write test error occurs. If all write tests pass, read all data from 0x64000000 to 0x65000000 at once, and check if each read data matches the corresponding written data. If they match, the Flash test is considered passed. Otherwise, a read test error is considered to have occurred at the corresponding address space of the Flash.

[0072] Therefore, the steps in steps S2) and S3) of sequentially writing test data to the space of each address of the target memory chip and verifying it within a preset number of times specifically include:

[0073] Select the current data as the test data, and use the current address space of the target memory chip as the target address space;

[0074] Write the test data into the target address space, and read the saved data in the target address space within a preset time. If the saved data and the test data are the same, the verification is successful, and the following steps are executed:

[0075] The value of the current data is incremented by one to obtain the next data, so that the next data is different from the current data. The next data is selected as the test data, and the space of the next address of the target memory chip is used as the space of the target address. The step of writing the test data into the space of the target address is executed until the address space of the target memory chip is traversed.

[0076] If the saved data and the test data are different, perform the following steps:

[0077] If the number of reads of the space at the corresponding target address does not reach the preset threshold, the step of reading the saved data in the space at the target address within the preset time is executed. If the number of reads of the space at the corresponding target address reaches the preset threshold, the verification fails. The corresponding target address is then used as the address that fails verification. The step of generating a test result for the address that fails verification and reporting it to the host computer is then executed.

[0078] In this embodiment, if the saved data and the test data are the same, the test data is also saved to the first data set; the step of reading all the saved data of the storage chip and comparing it with the corresponding written data specifically includes:

[0079] Read the corresponding data from all address spaces of the target memory chip and save it to the second data set;

[0080] Select and save data from the second data set, and match the corresponding test data from the first data set according to the address of the saved data;

[0081] Compare the saved data with the corresponding test data. If the saved data and the corresponding test data are the same, execute the step of selecting saved data from the second data set until all saved data in the second data set has been selected. If the saved data and the corresponding test data are not the same, execute the step of generating a test result of the test error from the information of the address corresponding to the saved data and reporting it to the host computer.

[0082] In step S3) of this embodiment, after erasing the target memory chip, the following steps are also included: if the erasure is successful, the step of writing test data to the space of each address of the memory chip in sequence and verifying it is executed; if the erasure fails, the test result of the erasure failure is reported to the host computer, because the flash memory chip that fails to be erased must be a defective memory chip, thereby skipping the detection of the flash memory chip that fails to be erased, so as to save test time.

[0083] The memory chip testing method in this embodiment also includes a step of interaction between the host computer and the DSP unit, specifically including:

[0084] 1) Generate the host computer instruction to start the test, and send the host computer instruction to the DSP unit;

[0085] 2) Wait for and obtain the test results reported by the DSP unit. If the test is passed, mark the corresponding memory chip as having passed the test; if the test is incorrect, mark the corresponding memory chip as having failed the test, and record the address information in the test results; if the erase failure notification is received, mark the corresponding memory chip as having failed to erase.

[0086] In this embodiment, in order to control the start and stop of the memory chip test, the interaction between the host computer and the DSP unit further includes: generating a host computer command to stop the test and sending it to the DSP unit;

[0087] The steps for DSP unit testing of memory chips also include: obtaining and parsing instructions from the host computer; if the instruction is to stop the test, ending and exiting.

[0088] Example 2

[0089] This embodiment is basically the same as Embodiment 1, except that in the memory chip testing method of this embodiment, the host computer instructions generated by the host computer can also include the type of each memory chip being tested, input by the operator. This allows the DSP unit to perform unified processing on memory chips of the same type when testing memory chips, given that the type of each memory chip is clearly known, thereby saving testing time. In this case, the specific steps for the DSP unit to test memory chips include:

[0090] A1) Obtain and parse the host computer instructions. If it is to start a test, also obtain the type of each memory chip in the host computer instructions.

[0091] A2) If a first-type memory chip exists, perform EEPROM memory chip testing on all first-type memory chips separately;

[0092] A3) If a second type of memory chip exists, perform Flash memory chip testing on all second type memory chips separately.

[0093] The EEPROM storage chip test in this embodiment is the same as in Embodiment 1. That is, for each address of the target storage chip, test data is written to the space of the address in sequence and verified within a preset number of times. If there is an address that fails verification, the information of the address that fails verification is used to generate a test error result and reported to the host computer. If each address passes verification, all the saved data of the target storage chip is read and compared with the corresponding test data. If the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate a test error result and reported to the host computer. If all the saved data is consistent with the corresponding test data, the test result that passes is reported to the host computer.

[0094] The Flash memory chip test in this embodiment is the same as in Embodiment 1, that is, the target memory chip is erased, and for each address of the target memory chip, test data is written to the space of the address in sequence and verified within a preset number of times. If there is an address that fails verification, the information of the address that fails verification is used to generate a test error result and reported to the host computer. If each address passes verification, all the saved data of the target memory chip is read and compared with the corresponding test data. If the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate a test error result and reported to the host computer. If all the saved data is consistent with the corresponding test data, the test result that passes is reported to the host computer.

[0095] Example 3

[0096] This embodiment is basically the same as Embodiment 1, except that, in order to improve the real-time reporting of test results, the DSP unit's testing steps for the memory chip in this embodiment do not need to determine the order of testing based on the type of the memory chip being tested. Figure 6 As shown, the specific steps include:

[0097] B1) Obtain and parse the host computer instruction. If it is to start the test, proceed to step B2).

[0098] B2) Select the target memory chip from the memory chips, read the hardware parameters of the target memory chip to obtain the type of the target memory chip. If the type of the target memory chip is the first type, execute step B3). If the type of the target memory chip is the second type, erase the target memory chip and then execute step B3).

[0099] B3) For each address of the target memory chip, write test data into the space of the address in sequence and verify it within a preset number of times. If there is an address that fails verification, generate a test error result for the address that fails verification and report it to the host computer and then execute step B4). If each address passes verification, read all the saved data of the target memory chip and compare it with the corresponding test data. If the saved data is inconsistent with the corresponding test data, generate a test error result for the address corresponding to the saved data and report it to the host computer and then execute step B4). If all data passes verification, report the test result that passes the test to the host computer.

[0100] B4) Return to step B2) until all memory chips have been selected.

[0101] The above steps are applicable to situations where the number of memory chips being tested is small and their types are different, such as only one EEPROM memory chip and one Flash memory chip. In this case, by executing the test of each memory chip sequentially and reporting the test results in real time, it is not necessary to determine the test order according to the memory chip type, which improves the real-time performance of the test and simplifies the complexity of the test program.

[0102] In step B2) of this embodiment, after erasing the target memory chip, the following steps are also included: if the erasure is successful, step B3) is executed; if the erasure fails, the test result of the erasure failure is reported to the host computer, and step B4) is executed, thereby skipping the Flash memory chip that failed to be erased and testing the next target memory chip to save test time.

[0103] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A memory chip testing method, characterized by, The application is applied to a storage chip testing device, the storage chip testing device comprises a host computer and a DSP unit connected with each other, the DSP unit is connected with at least two storage chips to be tested, and the method comprises the following steps in detail: The host computer instruction is acquired and parsed, if the host computer instruction is a start test instruction, the hardware information of each storage chip is read to obtain the type of each storage chip; If there is a first type of storage chip, a first test is respectively performed on each first type of storage chip, the first test comprises the following steps: test data is written into the space of each address of the target storage chip in sequence, and then the target storage chip is verified within a preset number of times, if there is an address that fails to pass the verification, the information of the address that fails to pass the verification is used to generate a test error test result, and the test error test result is reported to the host computer, if each address passes the verification, the test data is saved to a first data set, all saved data of the target storage chip is read and compared with the corresponding test data, if the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate a test error test result, and the test error test result is reported to the host computer, if all saved data is consistent with the corresponding test data, a test pass test result is reported to the host computer; If there is a second type of storage chip, a second test is respectively performed on each second type of storage chip, the second test comprises the following steps: the target storage chip is erased, test data is written into the space of each address of the target storage chip in sequence, and then the target storage chip is verified within a preset number of times, if there is an address that fails to pass the verification, the information of the address that fails to pass the verification is used to generate a test error test result, and the test error test result is reported to the host computer, if each address passes the verification, the test data is saved to a first data set, all saved data of the target storage chip is read and compared with the corresponding test data, if the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate a test error test result, and the test error test result is reported to the host computer, if all saved data is consistent with the corresponding test data, a test pass test result is reported to the host computer; The step of reading all saved data of the target storage chip and comparing the saved data with the corresponding test data comprises the following steps: The corresponding saved data is read from the space of all addresses of the target storage chip and saved to a second data set; The saved data is selected from the second data set, and the corresponding test data is matched from the first data set according to the address corresponding to the saved data; The saved data and the corresponding test data are compared, if the saved data and the corresponding test data are the same, the step of selecting the saved data from the second data set is executed until the saved data in the second data set is selected completely, if the saved data and the corresponding test data are not the same, the step of generating a test error test result by using the information of the address corresponding to the saved data and reporting the test error test result to the host computer is executed.

2. The memory chip testing method of claim 1, wherein, The step of writing test data into the space of each address of the target storage chip in sequence and then verifying the target storage chip within a preset number of times comprises the following steps: The current data is selected as the test data, and the space of the current address of the target storage chip is selected as the space of the target address. write the test data into the target address space, read the saved data in the target address space within a preset time, if the saved data is the same as the test data, the verification is passed, and the following steps are executed: the next data is taken as the test data, the next data is different from the current data, the next address space of the target storage chip is taken as the target address space, the step of writing the test data into the target address space is executed until the address space of the target storage chip is traversed; if the saved data is different from the test data, the following steps are executed: if the reading times of the corresponding target address space do not reach a preset threshold, the step of reading the saved data in the target address space within a preset time is executed, if the reading times of the corresponding target address space reach the preset threshold, the verification is failed, the corresponding target address is taken as a verification-failed address, the step of generating a test result of a test error of the verification-failed address and reporting the test result to an upper computer is executed.

3. The memory chip testing method of claim 2, wherein, The step of taking the next data as the test data before includes a step of obtaining the next data, specifically including: obtaining the next data by adding one to the value of the current data.

4. The memory chip testing method of claim 1, wherein, The step of erasing the target storage chip further includes the following steps: if the erasing is successful, the step of writing the test data into the address space of each address of the storage chip in sequence and verifying is executed, if the erasing fails, a test result of the erasing failure is reported to the upper computer.

5. The memory chip testing method of claim 1, wherein, The method further includes the following steps of interaction between the upper computer and the DSP unit: generating an upper computer instruction of starting the test, and sending the upper computer instruction to the DSP unit; waiting for and obtaining the test result reported by the DSP unit, if the test result is test passed, marking that the corresponding storage chip passes the test; if the test result is test error, marking that the corresponding storage chip fails the test and recording the address information in the test result; if the test result is an erasing failure notification, marking that the corresponding storage chip fails the erasing.

6. The memory chip testing method of claim 5, wherein, The step of interaction between the upper computer and the DSP unit further includes: generating an upper computer instruction of stopping the test and sending the upper computer instruction to the DSP unit; The step of the DSP unit testing the storage chip further includes: obtaining the upper computer instruction and analyzing the upper computer instruction, if the upper computer instruction is the instruction of stopping the test, ending and exiting.

7. A memory chip testing apparatus, characterized by comprising: The system includes a DSP unit, a bridge unit, a communication unit and an upper computer connected in sequence, the DSP unit is further connected with at least two storage chips to be tested, and the upper computer is connected with the communication unit. The upper computer is configured to generate an upper computer instruction of starting the test, and send the upper computer instruction to the DSP unit through the communication unit, and is further configured to wait for and obtain the test result reported by the DSP unit through the communication unit, if the test result is test passed, marking that the corresponding storage chip passes the test; if the test result is test error, marking that the corresponding storage chip fails the test and recording the address information in the test result; if the test result is an erasing failure notification, marking that the corresponding storage chip fails the erasing. The communication unit is configured to send the upper computer instruction to the DSP unit through the bridge unit, and is further configured to obtain the test result reported by the DSP unit through the bridge unit and report the test result reported by the DSP unit to the upper computer. The DSP unit is configured to acquire and parse the host computer instruction through the communication unit, and if the instruction is to start the test, corresponding tests are performed according to the types of the memory chips, if the type of the memory chip is a first type, test data is written into the space of each address of the memory chip in sequence, and then the test data is verified within a preset number of times, if the type of the memory chip is a second type, the memory chip is erased, if the erasing is successful, the test data is written into the space of each address of the memory chip in sequence, and then the test data is verified within a preset number of times, if the erasing fails, the test result of the erasing failure is reported to the host computer through the bridge unit and the communication unit in sequence; after the test data is written into the space of each address of the memory chip in sequence and then verified within a preset number of times, if there is an address that fails to pass the verification, the information of the address that fails to pass the verification is used to generate a test error test result, and the test result is reported to the host computer through the bridge unit and the communication unit in sequence; if each address passes the verification, all saved data of the memory chip is read and compared with the corresponding test data, if the saved data is inconsistent with the corresponding test data, the information of the address corresponding to the saved data is used to generate a test error test result, and the test result is reported to the host computer through the bridge unit and the communication unit in sequence; if all saved data is consistent with the corresponding test data, a test pass test result is reported to the host computer through the bridge unit and the communication unit in sequence; The DSP unit is further configured to save the test data into a first data set when the saved data and the test data are the same, and when all saved data of the memory chip is read and compared with the corresponding test data, the DSP unit is specifically configured to: read the corresponding saved data from all addresses of the memory chip and save the saved data into a second data set; select the saved data from the second data set, and match the corresponding test data from the first data set according to the address corresponding to the saved data; compare the saved data and the corresponding test data, if the saved data and the corresponding test data are the same, the step of selecting the saved data from the second data set is performed until the saved data in the second data set is selected completely, if the saved data and the corresponding test data are not the same, the step of generating a test error test result by using the information of the address corresponding to the saved data and reporting the test result to the host computer is performed.

8. The memory chip testing apparatus according to claim 7, wherein When the test data is written into the space of each address of the target memory chip in sequence and then verified within a preset number of times, the DSP unit is specifically configured to: select the current data as the test data, and select the space of the current address of the memory chip as the space of the target address. The test data is written into the space of the target address, the saved data in the space of the target address is read within a preset time, if the saved data and the test data are the same, the verification is passed, the next data is selected as the test data, the next data is different from the current data, the space of the next address of the target storage chip is taken as the space of the target address, the step of writing the test data into the space of the target address is executed until the space of the address of the target storage chip is traversed, if the saved data and the test data are different and the reading times of the corresponding space of the target address do not reach a preset threshold, the step of reading the saved data in the space of the target address within a preset time is executed, if the reading times of the corresponding space of the target address reach the preset threshold, the verification is failed, the corresponding target address is taken as the address of the verification failure, the step of generating the test result of the test error by the information of the address and reporting to the upper computer is executed.

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