Wafer adjustment method, wafer bonding method, and photolithography system

Abstract

The application provides a wafer adjustment method, a wafer bonding method and a photolithography system, wherein the adjustment method comprises the following steps: providing a first wafer and a second wafer, and the first wafer is processed in advance relative to the second wafer before a bonding process; obtaining a first topographic size of the first wafer; and adjusting a topographic size of the second wafer in an unfinished processing process according to the first topographic size, so that a difference between the adjusted topographic size of the second wafer and the first topographic size is within a predetermined range. The application better alleviates the problem of poor alignment accuracy during wafer bonding, so that the quality of wafer bonding is better, thereby improving the production yield and providing a good foundation for subsequent processes.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a wafer shaping method, a wafer bonding method, a computer-readable storage medium, and a photolithography system. Background Technology

[0002] With the continuous development of 3D NAND (3D NAND flash memory) technology, bonding array wafers with CMOS (Complementary Metal Oxide Semiconductor) wafers offers a new approach to continuously increasing storage capacity. However, due to the increasingly complex and significant differences in the manufacturing processes of array wafers and CMOS wafers, the final actual array wafer differs considerably from the actual CMOS wafer, especially in terms of deformation. Therefore, poor alignment accuracy is prone to occur during wafer bonding, ultimately affecting the wafer bonding quality and yield.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a wafer adjustment method, a wafer bonding method, a computer-readable storage medium, and a photolithography system, which can at least solve the above-mentioned problems.

[0005] According to one aspect of the present invention, a wafer adjustment method is provided, comprising: providing a first wafer and a second wafer, wherein the first wafer completes a processing step relative to the second wafer before a bonding step; obtaining a first morphological dimension of the first wafer; and adjusting the morphological dimension of the second wafer in an incomplete processing step based on the first morphological dimension, such that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range.

[0006] Optionally, based on the first topographic dimension, adjusting the topographic dimension of the second wafer in the incomplete processing step includes: obtaining the second topographic dimension of the second wafer located at the input end of the processing step to be executed, wherein the incomplete processing step includes the processing step to be executed; and adjusting the second wafer in the processing step to be executed based on the first topographic dimension and the second topographic dimension to obtain the adjusted second wafer.

[0007] Optionally, the incomplete processing steps include at least the photolithography step.

[0008] Optionally, based on the first topographic dimensions and the second topographic dimensions, the second wafer is adjusted in the processing step to be performed to obtain the adjusted second wafer, including: determining the expansion parameter of the processing step to be performed based on the first topographic dimensions and the second topographic dimensions, wherein the processing step to be performed is a photolithography process; and processing the second wafer according to the expansion parameter in the processing step to be performed to obtain the adjusted second wafer.

[0009] Optionally, determining the expansion parameter of the processing step to be performed based on the first morphology size and the second morphology size includes: determining a first expansion value of the second wafer in a first direction and / or a second expansion value of the second wafer in a second direction based on the first morphology size and the second morphology size, wherein the first direction intersects the second direction and both the first direction and the second direction are perpendicular to the thickness direction of the second wafer; and determining the expansion parameter based on the first expansion value and / or the second expansion value.

[0010] Optionally, the first morphology dimension is the designed dimension of the first wafer, or the first morphology dimension is the actual dimension of the first wafer before entering the bonding process.

[0011] Optionally, the first wafer is a CMOS wafer, and the second wafer is an array wafer.

[0012] According to another aspect of the present invention, a wafer bonding method is also provided, comprising: providing a first wafer and a second wafer, wherein the second wafer is obtained by any of the wafer adjustment methods described herein; and bonding the first wafer and the second wafer.

[0013] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein the program executes any one of the methods described.

[0014] According to another aspect of the present invention, a lithography system is also provided, including a lithography machine and a wafer adjustment device, wherein the wafer adjustment device is communicatively connected to the lithography machine, and the wafer adjustment device is used to perform any of the methods described.

[0015] In the wafer adjustment method of this invention, a first wafer and a second wafer to be bonded are first provided, and before bonding, the second wafer has unfinished processing steps. Then, a first topographic dimension of the first wafer is obtained. Finally, based on the first topographic dimension, the topographic dimension of the second wafer is adjusted in the unfinished processing steps so that the difference between the adjusted topographic dimension of the second wafer and the first topographic dimension is within a predetermined range. The method of this application, before the bonding process, adjusts the topographic dimension of the second wafer based on the topographic dimension of the first wafer so that the difference in size between the two wafers to be bonded is within the predetermined range. This allows for better bonding of the two wafers in subsequent bonding processes, effectively alleviating the problem of poor alignment accuracy during wafer bonding, resulting in better wafer bonding quality, improved production yield, and a good foundation for subsequent processes. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of a wafer to be bonded according to an embodiment is shown;

[0018] Figure 2 A schematic flowchart of a wafer adjustment method according to an embodiment of this application is shown;

[0019] Figure 3 A schematic diagram of a wafer to be bonded, adjusted according to an embodiment of this application, is shown;

[0020] Figure 4 A schematic flowchart of a wafer bonding method according to an embodiment of this application is shown.

[0021] Figure 5 A schematic diagram of a wafer adjustment device according to an embodiment of this application is shown.

[0022] The above figures include the following reference numerals:

[0023] 100. Design array wafer; 101. Actual array wafer; 102. Final array wafer; 200. Design CMOS wafer; 201. Actual CMOS wafer; 202. Final CMOS wafer. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0028] In the production process of array wafers, due to the increasing complexity of the process, such as Figure 1 As shown, this causes deformation of the array wafer, specifically bending and / or expansion deviations. This results in a significant dimensional difference between the actual array wafer 101 and the designed array wafer 100, and even variations in expansion within the same batch of array wafers. However, CMOS wafer manufacturing processes are relatively simple and mature, avoiding these issues. The resulting actual CMOS wafer 201 is essentially the same size as the designed CMOS wafer 200. Therefore, alignment errors can occur during the bonding of the actual array wafer 101 and the actual CMOS wafer 201, ultimately affecting wafer bonding quality and yield.

[0029] To address the aforementioned problems, in a typical embodiment of this application, a wafer adjustment method, a wafer bonding method, a computer-readable storage medium, and a photolithography system are provided.

[0030] In 3D NAND flash memory structures, bonding wafers are obtained by bonding CMOS wafers and array wafers. The CMOS wafer can be the wafer for the peripheral circuitry of the 3D NAND, and the array wafer can be the wafer for the memory cells of the 3D NAND. In practical applications, the fabrication process of the array wafer is relatively complex. The fabricated array wafer will undergo significant deformation due to bending and / or expansion, resulting in a difference between the actual size of the array wafer and the design size. Furthermore, the deformation of each array wafer varies, and even within the same batch, the deformation can differ. In contrast, the CMOS wafer, due to its relatively mature and simple process, exhibits less deformation. This difference in process technology leads to a significant difference in deformation between the fabricated CMOS wafer and the array wafer for the same design size. This results in lower alignment accuracy during bonding of the CMOS wafer and the array wafer, thus affecting the bonding quality.

[0031] To address the above-mentioned problems, an embodiment of this application provides a wafer adjustment method.

[0032] Figure 2 This is a flowchart of a wafer adjustment method according to an embodiment of this application. Figure 2 As shown, the method includes the following steps:

[0033] Step S101: Provide a first wafer and a second wafer, and before the bonding process, the first wafer completes the processing steps ahead of the second wafer, that is, compared with the first wafer, the second wafer still has unfinished processing steps.

[0034] Step S102: Obtain the first morphological dimensions of the first wafer.

[0035] Step S103: Based on the first morphological dimension, in the incomplete processing step, the morphological dimension of the second wafer is adjusted so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range.

[0036] In the aforementioned wafer adjustment method, firstly, a first wafer and a second wafer to be bonded are provided, and before bonding, the second wafer has unfinished processing steps. Then, the first morphological dimension of the first wafer is obtained. Finally, based on the first morphological dimension, the morphological dimension of the second wafer is adjusted during the unfinished processing steps so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range. The method of this application, before the bonding process, adjusts the morphological dimension of the second wafer based on the morphological dimension of the first wafer, ensuring that the difference in size between the two wafers to be bonded is within the predetermined range. This improves the bonding effect of the two wafers in subsequent bonding processes, effectively alleviating the problem of poor alignment accuracy during wafer bonding, resulting in better wafer bonding quality, improved production yield, and a good foundation for subsequent processes.

[0037] Specifically, the aforementioned morphological dimensions may include the diameter of the wafer in different directions, the warp shape of different parts, and the degree of warp in different parts.

[0038] In one specific embodiment of this application, the first wafer is a CMOS wafer, and the second wafer is an array wafer. By employing the adjustment method described above, the size of each array wafer is adjusted accordingly before bonding, so that the adjusted size of the array wafer is substantially consistent with the size of the CMOS wafer. Then, the adjusted array wafer and the CMOS wafer are bonded together, resulting in higher actual alignment accuracy between the array wafer and the CMOS wafer, thus achieving a better bonding effect.

[0039] To further and more simply and efficiently adjust the dimensions of the second wafer, thereby improving the subsequent bonding effect, according to another specific embodiment of this application, based on the first morphology dimension, the morphology dimension of the second wafer is adjusted in the incomplete processing step, including: obtaining the second morphology dimension of the second wafer located at the input end of the processing step to be executed, wherein the incomplete processing step includes the processing step to be executed; and adjusting the second wafer in the processing step to be executed based on the first morphology dimension and the second morphology dimension to obtain the adjusted second wafer.

[0040] Specifically, the wafer adjustment method described above can be applied to a photolithography machine, and the incomplete processing steps mentioned above include at least a photolithography step. In actual production, there are many photolithography steps before the bonding step and during the fabrication of the second wafer. These photolithography steps can all be used as opportunities to adjust the second morphology dimensions of the second wafer. Of course, in order to ensure that the adjusted second morphology dimensions are less affected by other processes before the bonding step, the photolithography step for adjusting the second wafer should be selected as close as possible to the bonding step.

[0041] In another specific embodiment of this application, based on the first morphological dimension and the second morphological dimension, the second wafer is adjusted in the processing step to be performed to obtain the adjusted second wafer. This includes: determining the expansion parameter of the processing step to be performed based on the first morphological dimension and the second morphological dimension, wherein the processing step to be performed is a photolithography process; and processing the second wafer according to the expansion parameter in the processing step to be performed to obtain the adjusted second wafer. By adjusting the expansion parameter of the second wafer in the photolithography process, compensation for the morphological dimension of the second wafer can be achieved, further ensuring that the size of the adjusted second wafer is substantially consistent with the first morphological dimension.

[0042] To further and more accurately adjust the morphology and dimensions of the second wafer, thereby ensuring better alignment accuracy of the subsequent two wafers, according to another specific embodiment of this application, the expansion parameter of the processing step to be performed is determined based on the first morphology and dimensions and the second morphology and dimensions. This includes: determining a first expansion value of the second wafer in a first direction and / or a second expansion value of the second wafer in a second direction based on the first morphology and dimensions and the second morphology and dimensions, wherein the first direction and the second direction intersect, that is, the first direction and the second direction are not parallel, the first expansion value and the second expansion value are two different directions, and both the first direction and the second direction are perpendicular to the thickness direction of the second wafer; and determining the expansion parameter based on the first expansion value and / or the second expansion value.

[0043] In a more specific embodiment, the first direction is perpendicular to the second direction. Additionally, in practical applications, wafers typically have a positioning notch, and one of the first and second directions is aligned with the direction of the notch.

[0044] To further ensure that the adjusted dimensions of the second wafer are substantially consistent with the first dimensions, thereby further ensuring a better bonding effect, according to another specific embodiment of this application, the first dimensions are either the design dimensions of the first wafer or the actual dimensions of the first wafer before entering the bonding process. In practical applications, the first wafer is a CMOS wafer. During the fabrication process before bonding, the dimensions of the first wafer are also affected, and its actual dimensions may deviate from the design dimensions. In this case, to further ensure alignment between the adjusted second wafer and the first wafer, the actual dimensions of the first wafer before entering the bonding process can be used as the first dimensions. However, the fabrication process for CMOS wafers is relatively mature, and the impact of the pre-bonding fabrication process on its dimensions is relatively small, meaning the deviation between the actual dimensions and the design dimensions of the CMOS wafer is small. In this case, to further simplify and expedite the adjustment of the second wafer, the design dimensions of the first wafer can be selected as the first dimensions.

[0045] In a more specific embodiment of this application, the second wafer is an array wafer, and the first wafer is a CMOS wafer. For example... Figure 3 As shown, the dimensions of the designed CMOS wafer 200 are the design dimensions. After some processes before bonding, the designed CMOS wafer 200 undergoes deformation to obtain the actual CMOS wafer 201. The dimensions of the designed array wafer 100 are also the design dimensions. After some processes before bonding, the designed array wafer 100 undergoes deformation to obtain the actual array wafer 101. The dimensions of the actual array wafer 101 are the second morphological dimensions. By adjusting the actual CMOS wafer 201 before the bonding process, the final CMOS wafer 202 is obtained. The morphological dimensions of the final CMOS wafer 202 are the first morphological dimensions. Based on the first morphological dimensions and the second morphological dimensions, the morphological dimensions of the actual array wafer 101 are adjusted before the bonding process to obtain the final array wafer 102. Finally, the final array wafer 102 and the final CMOS wafer 202 are bonded together, which further ensures high alignment accuracy and good bonding effect. Of course, the actual CMOS wafer can be used as the first topographic dimension without adjusting the actual CMOS wafer, or the design CMOS wafer can be used as the first topographic dimension to adjust the topographic dimension of the actual array wafer.

[0046] According to another typical embodiment of this application, a wafer bonding method is also provided, such as... Figure 4 As shown, the above wafer bonding method includes the following steps:

[0047] Step S201: Provide a first wafer and a second wafer, wherein the second wafer is obtained by any of the above-described wafer adjustment methods;

[0048] Step S202: Bond the first wafer and the second wafer together.

[0049] The above-described wafer bonding method involves adjusting the first wafer to obtain the second wafer using the aforementioned wafer adjustment method, and then bonding the first wafer with the second wafer to obtain a bonded wafer. Because the wafer adjustment method adjusts the shape and dimensions of the second wafer based on the shape and dimensions of the first wafer before the bonding process, the size difference between the two wafers to be bonded is within the predetermined range. This results in a better bonding effect between the two wafers, effectively mitigating the problem of poor alignment accuracy during wafer bonding, leading to higher wafer bonding quality, improved production yield, and a solid foundation for subsequent processes.

[0050] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0051] This application also provides a wafer bonding control device. It should be noted that the wafer bonding control device of this application can be used to execute the wafer adjustment method provided in this application. The wafer bonding control device provided in this application is described below.

[0052] Figure 5 This is a schematic diagram of a wafer bonding control device according to an embodiment of this application. Figure 5 As shown, the device includes a providing unit 10, an acquiring unit 20, and an adjusting unit 30. The providing unit 10 provides a first wafer and a second wafer, and before the bonding process, the first wafer has completed processing steps ahead of the second wafer, meaning that the first wafer still has unfinished processing steps compared to the first wafer. The acquiring unit 20 acquires the first morphological dimension of the first wafer. The adjusting unit 30 adjusts the morphological dimension of the second wafer based on the first morphological dimension during the unfinished processing steps, so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range.

[0053] In the aforementioned wafer adjustment apparatus, a first wafer and a second wafer to be bonded are provided by the aforementioned providing unit, and the second wafer has unfinished processing steps before bonding; a first morphological dimension of the first wafer is obtained by the aforementioned obtaining unit; and the morphological dimension of the second wafer is adjusted by the aforementioned adjusting unit based on the aforementioned first morphological dimension during the unfinished processing steps, so that the difference between the adjusted morphological dimension of the second wafer and the aforementioned first morphological dimension is within a predetermined range. The apparatus of this application adjusts the morphological dimension of the second wafer based on the morphological dimension of the first wafer before the bonding process, so that the difference in size between the two wafers to be bonded is within the aforementioned predetermined range. This allows for better bonding of the two wafers in subsequent bonding processes, effectively alleviating the problem of poor alignment accuracy during wafer bonding, resulting in better wafer bonding quality, thereby improving production yield and providing a good foundation for subsequent processes.

[0054] Specifically, the aforementioned morphological dimensions may include the diameter of the wafer in different directions, the warp shape of different parts, and the degree of warp in different parts.

[0055] In one specific embodiment of this application, the first wafer is a CMOS wafer, and the second wafer is an array wafer. By employing the adjustment device described in this application, the size of each array wafer is adjusted accordingly before bonding, so that the adjusted size of the array wafer is substantially consistent with the size of the CMOS wafer. Then, the adjusted array wafer and the CMOS wafer are bonded together, resulting in higher actual alignment accuracy between the array wafer and the CMOS wafer, and thus a better bonding effect.

[0056] To further and more simply and efficiently adjust the dimensions of the second wafer, thereby improving the subsequent bonding effect, according to another specific embodiment of this application, the adjustment unit includes an acquisition module and an adjustment module. The acquisition module is used to acquire the second morphological dimensions of the second wafer located at the input end of the processing step to be executed, and the unfinished processing step includes the processing step to be executed. The adjustment module is used to adjust the second wafer according to the first morphological dimensions and the second morphological dimensions in the processing step to be executed, thereby obtaining the adjusted second wafer.

[0057] Specifically, the aforementioned wafer adjustment device can be applied to a photolithography machine, and the unfinished processing steps include at least a photolithography step. In actual production, there are many photolithography steps before the bonding step and during the fabrication of the second wafer. These photolithography steps can all be used as opportunities to adjust the second morphology dimensions of the second wafer. Of course, in order to ensure that the adjusted second morphology dimensions are less affected by other processes before the bonding step, the photolithography step for adjusting the second wafer should be selected as close as possible to the bonding step.

[0058] In another specific embodiment of this application, the adjustment module includes a determining submodule and a processing submodule. The determining submodule is used to determine the expansion parameter of the processing step to be executed based on the first morphology dimension and the second morphology dimension, wherein the processing step to be executed is a photolithography step. The processing submodule is used to process the second wafer according to the expansion parameter in the processing step to be executed to obtain the adjusted second wafer. By adjusting the expansion parameter of the second wafer in the photolithography step, compensation for the morphology dimension of the second wafer can be achieved, further ensuring that the size of the adjusted second wafer is substantially consistent with the first morphology dimension.

[0059] To further and more accurately adjust the morphology and dimensions of the second wafer, thereby ensuring better alignment accuracy of the subsequent two wafers, according to another specific embodiment of this application, the determining submodule is further configured to determine a first expansion value of the second wafer in a first direction and / or a second expansion value of the second wafer in a second direction based on the first morphology and dimensions and the second morphology. The first direction intersects with the second direction, that is, the first direction is not parallel to the second direction, the first expansion value and the second expansion value are two different directions, and both the first direction and the second direction are perpendicular to the thickness direction of the second wafer. The determining submodule is further configured to determine the expansion amount parameter based on the first expansion value and / or the second expansion value.

[0060] In a more specific embodiment, the first direction is perpendicular to the second direction. Additionally, in practical applications, wafers typically have a positioning notch, and one of the first and second directions is aligned with the direction of the notch.

[0061] To further ensure that the adjusted dimensions of the second wafer are substantially consistent with the first dimensions, thereby further ensuring a better bonding effect, according to another specific embodiment of this application, the first dimensions are either the design dimensions of the first wafer or the actual dimensions of the first wafer before entering the bonding process. In practical applications, the first wafer is a CMOS wafer. During the fabrication process before bonding, the dimensions of the first wafer are also affected, and its actual dimensions may deviate from the design dimensions. In this case, to further ensure alignment between the adjusted second wafer and the first wafer, the actual dimensions of the first wafer before entering the bonding process can be used as the first dimensions. However, the fabrication process for CMOS wafers is relatively mature, and the impact of the pre-bonding fabrication process on its dimensions is relatively small, meaning the deviation between the actual dimensions and the design dimensions of the CMOS wafer is small. In this case, to further simplify and expedite the adjustment of the second wafer, the design dimensions of the first wafer can be selected as the first dimensions.

[0062] In a more specific embodiment of this application, the second wafer is an array wafer, and the first wafer is a CMOS wafer. For example... Figure 3 As shown, the dimensions of the designed CMOS wafer 200 are the design dimensions. After some processes before bonding, the designed CMOS wafer 200 undergoes deformation to obtain the actual CMOS wafer 201. The dimensions of the designed array wafer 100 are also the design dimensions. After some processes before bonding, the designed array wafer 100 undergoes deformation to obtain the actual array wafer 101. The dimensions of the actual array wafer 101 are the second morphological dimensions. By adjusting the actual CMOS wafer 201 before the bonding process, the final CMOS wafer 202 is obtained. The morphological dimensions of the final CMOS wafer 202 are the first morphological dimensions. Based on the first morphological dimensions and the second morphological dimensions, the morphological dimensions of the actual array wafer 101 are adjusted before the bonding process to obtain the final array wafer 102. Finally, the final array wafer 102 and the final CMOS wafer 202 are bonded together, which further ensures high alignment accuracy and good bonding effect. Of course, the actual CMOS wafer can be used as the first topographic dimension without adjusting the actual CMOS wafer, or the design CMOS wafer can be used as the first topographic dimension to adjust the topographic dimension of the actual array wafer.

[0063] The aforementioned wafer bonding control device includes a processor and a memory. The aforementioned providing unit, obtaining unit, and adjusting unit are all stored in the memory as program units, and the processor executes the aforementioned program units stored in the memory to realize the corresponding functions.

[0064] The processor contains a core, which retrieves the corresponding program unit from memory. One or more cores can be configured, and adjusting core parameters can help address issues with poor wafer bonding quality.

[0065] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0066] This invention provides a computer-readable storage medium storing a program that, when executed by a processor, implements the above-described wafer adjustment method.

[0067] This invention provides a processor for running a program, wherein the program executes the wafer adjustment method during runtime.

[0068] This invention provides a device including a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs at least the following steps:

[0069] Step S101: Provide a first wafer and a second wafer, and before the bonding process, the first wafer completes the processing steps ahead of the second wafer, that is, compared with the first wafer, the first wafer still has unfinished processing steps.

[0070] Step S102: Obtain the first morphological dimensions of the first wafer.

[0071] Step S103: Based on the first morphological dimension, in the incomplete processing step, the morphological dimension of the second wafer is adjusted so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range.

[0072] The devices mentioned in this article can be servers, PCs, tablets, mobile phones, etc.

[0073] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program having at least the following method steps:

[0074] Step S101: Provide a first wafer and a second wafer, and before the bonding process, the first wafer completes the processing steps ahead of the second wafer, that is, compared with the first wafer, the first wafer still has unfinished processing steps.

[0075] Step S102: Obtain the first morphological dimensions of the first wafer.

[0076] Step S103: Based on the first morphological dimension, in the incomplete processing step, the morphological dimension of the second wafer is adjusted so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range.

[0077] According to another typical embodiment of this application, a lithography system is also provided, including a lithography machine and a wafer adjustment device, wherein the wafer adjustment device is communicatively connected to the lithography machine and is used to perform any of the methods described above.

[0078] The aforementioned photolithography system includes a photolithography machine with communication connectivity and a wafer adjustment device, wherein the wafer adjustment device is used to perform any of the aforementioned methods. In this application, the photolithography system adjusts the shape and size of a second wafer based on the shape and size of a first wafer before the bonding process, ensuring that the size difference between the two wafers to be bonded is within the predetermined range. This improves the bonding effect between the two wafers during the bonding process, effectively alleviating the problem of poor alignment accuracy during wafer bonding, resulting in better wafer bonding quality, increased production yield, and a good foundation for subsequent processes.

[0079] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units described above can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0081] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0082] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0083] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to related technologies, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0084] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0085] 1) The wafer adjustment method described in this application first provides a first wafer and a second wafer to be bonded, and before bonding, the second wafer has unfinished processing steps; then, the first morphological dimension of the first wafer is obtained; finally, based on the first morphological dimension, the morphological dimension of the second wafer is adjusted in the unfinished processing steps so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range. The method of this application, before the bonding process, adjusts the morphological dimension of the second wafer based on the morphological dimension of the first wafer, so that the difference in size between the two wafers to be bonded is within the predetermined range. This allows for better bonding of the two wafers in subsequent bonding processes, effectively alleviating the problem of poor alignment accuracy during wafer bonding, resulting in better wafer bonding quality, thereby improving production yield and providing a good foundation for subsequent processes.

[0086] 2) In the wafer adjustment apparatus described above in this application, a first wafer and a second wafer to be bonded are provided by the providing unit, and before bonding, the second wafer has unfinished processing steps; a first morphological dimension of the first wafer is obtained by the obtaining unit; and the morphological dimension of the second wafer is adjusted by the adjusting unit based on the first morphological dimension during the unfinished processing steps, so that the difference between the adjusted morphological dimension of the second wafer and the first morphological dimension is within a predetermined range. The apparatus of this application adjusts the morphological dimension of the second wafer based on the morphological dimension of the first wafer before the bonding process, so that the difference in size between the two wafers to be bonded is within the predetermined range. This improves the bonding effect of the two wafers in subsequent bonding processes, effectively alleviates the problem of poor alignment accuracy during wafer bonding, improves the quality of wafer bonding, thereby increasing production yield and providing a good foundation for subsequent processes.

[0087] 3) The lithography system described in this application includes a lithography machine and a wafer adjustment device connected by communication. The wafer adjustment device is used to perform any of the methods described above. Before the bonding process, the lithography system of this application adjusts the shape and size of the second wafer according to the shape and size of the first wafer, so that the difference in size between the two wafers to be bonded is within the predetermined range. This improves the bonding effect of the two wafers during the bonding process, effectively alleviates the problem of poor alignment accuracy during wafer bonding, improves the quality of wafer bonding, thereby increasing production yield and providing a good foundation for subsequent processes.

[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for adjusting a wafer, characterized in that, include: A first wafer and a second wafer are provided, and the first wafer completes the processing steps in advance relative to the second wafer before the bonding process; Obtain the first topographic dimensions of the first wafer; Based on the first topographic dimensions, in the incomplete processing steps, the topographic dimensions of the second wafer are adjusted so that the difference between the adjusted topographic dimensions of the second wafer and the first topographic dimensions is within a predetermined range. Based on the first morphology dimensions, in the incomplete processing steps, the morphology dimensions of the second wafer are adjusted, including: Obtain the second topographic dimensions of the second wafer located at the input end of the processing step to be executed, wherein the incomplete processing step includes the processing step to be executed; Based on the first morphology dimensions and the second morphology dimensions, in the processing step to be performed, the second wafer is adjusted to obtain the adjusted second wafer; The incomplete processing steps include at least a photolithography step; based on the first morphology size and the second morphology size, in the processing step to be performed, the second wafer is adjusted to obtain an adjusted second wafer, including: Based on the first morphological dimension and the second morphological dimension, the expansion parameter of the processing step to be performed is determined, wherein the processing step to be performed is a photolithography step; In the processing step to be performed, the second wafer is processed according to the expansion parameters to obtain the adjusted second wafer.

2. The method according to claim 1, characterized in that, Based on the first morphological dimension and the second morphological dimension, the expansion parameter of the processing step to be performed is determined, including: Based on the first morphology size and the second morphology size, determine the first expansion value of the second wafer in the first direction and / or the second expansion value of the second wafer in the second direction, wherein the first direction intersects the second direction and both the first direction and the second direction are perpendicular to the thickness direction of the second wafer; The expansion amount parameter is determined based on the first expansion value and / or the second expansion value.

3. The method according to claim 1, characterized in that, The first morphological dimension is the designed dimension of the first wafer, or the first morphological dimension is the actual dimension of the first wafer before entering the bonding process.

4. The method according to any one of claims 1 to 3, characterized in that, The first wafer is a CMOS wafer, and the second wafer is an array wafer.

5. A wafer bonding method, characterized in that, include: A first wafer and a second wafer are provided, wherein the second wafer is obtained using the wafer adjustment method according to any one of claims 1 to 3; The first wafer and the second wafer are bonded together.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program performs the method according to any one of claims 1 to 3.

7. A photolithography system, characterized in that, include: Photolithography machine; A wafer adjustment device, communicatively connected to the lithography machine, is used to perform the method according to any one of claims 1 to 3.

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