Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer extending along a first direction and penetrating the pattern definition layer formed in the pattern definition layer; removing a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction, forming an opening extending along the first direction and surrounded by the pattern definition layer, the target layer and the remaining first sacrificial layer; forming a first sidewall layer on the sidewall of the opening; removing a portion of the first sacrificial layer in the second direction, forming a groove in the first sacrificial layer extending along the first direction and surrounded by the opposite sidewalls of the remaining first sacrificial layer and the target layer; forming a second sidewall layer on the sidewall of the groove; removing the remaining first sacrificial layer; etching the target layer using the first sidewall layer and the second sidewall layer as masks to form a target pattern. The present invention further reduces the pitch between target patterns while increasing the process window.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of internal connection structures of each chip) gradually increases, the geometric size (i.e. the minimum component size that can be produced using the process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to break through the current limitations of lithography equipment and meet the process requirements of increasingly smaller metal line widths has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is conducive to further reducing the pitch between target patterns.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer extending along a first direction and penetrating the pattern definition layer formed in the pattern definition layer, and an etching selectivity ratio between the first sacrificial layer and the pattern definition layer; removing a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction, forming an opening extending along the first direction and surrounded by the pattern definition layer, the target layer and the remaining first sacrificial layer; forming a first sidewall layer on the sidewall of the opening; removing a portion of the width of the first sacrificial layer in the second direction, forming a groove in the first sacrificial layer extending along the first direction and surrounded by the opposite sidewalls of the remaining first sacrificial layer and the target layer; forming a second sidewall layer on the sidewall of the groove; after forming the first sidewall layer and the second sidewall layer, removing the remaining first sacrificial layer; after removing the remaining first sacrificial layer, etching the target layer using the first sidewall layer and the second sidewall layer as masks to form a target pattern.

[0007] Optionally, the groove is formed after a first sidewall layer is formed on the sidewall of the opening; or, the opening is formed after a second sidewall layer is formed on the sidewall of the groove; or, the groove is formed after the opening is formed, and after the groove is formed, the first sidewall layer and the second sidewall layer are formed in the same step; or, the opening is formed after the groove is formed, and after the opening is formed, the first sidewall layer and the second sidewall layer are formed in the same step.

[0008] Optionally, after forming the opening, the groove is formed, and before forming the groove, the method further includes: forming a second sacrificial layer in the opening; or, after forming the groove, the opening is formed, and before forming the opening, the method further includes: forming a second sacrificial layer in the groove; before etching the target layer using the first side wall layer and the second side wall layer as masks, the method further includes: removing the second sacrificial layer.

[0009] Optionally, the step of forming the first sacrificial layer and the graphic definition layer includes: forming a graphic material layer on top of the target layer; performing doping treatment on a partial area of ​​the graphic material layer, wherein the graphic material layer doped with ions serves as the graphic definition layer, and the remaining graphic material layer not doped with ions serves as the first sacrificial layer.

[0010] Optionally, the graphic material layer is doped by an ion implantation process.

[0011] Optionally, the material of the graphic material layer is amorphous silicon; in the step of doping the graphic material layer, the doping ions include boron ions, phosphorus ions or argon ions.

[0012] Optionally, an anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction.

[0013] Optionally, an anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer in the second direction.

[0014] Optionally, along the second direction, a size of the first spacer layer is equal to a size of the second spacer layer.

[0015] Optionally, along the second direction, a size of the first spacer layer is 10 nanometers to 20 nanometers, and a size of the second spacer layer is 10 nanometers to 20 nanometers.

[0016] Optionally, after forming the openings, the grooves are formed; in the step of forming the openings, along the second direction, a size of the remaining first sacrificial layer between the openings is larger than a size of the openings.

[0017] Optionally, the size of the remaining first sacrificial layer between the openings is greater than 4 times the size of the openings.

[0018] Optionally, the process of forming the first spacer layer includes an atomic layer deposition process.

[0019] Optionally, the process of forming the second spacer layer includes an atomic layer deposition process.

[0020] Optionally, the process of removing the first sacrificial layer includes one or both of an ashing process and a wet etching process.

[0021] Optionally, the process of removing the second sacrificial layer includes one or both of an ashing process and a wet etching process.

[0022] Optionally, in the step of removing the first sacrificial layer, an etching selection ratio of the first sacrificial layer to the first spacer layer and the second spacer layer is greater than 5:1.

[0023] Optionally, in the step of removing the second sacrificial layer, an etching selectivity ratio of the second sacrificial layer to the first spacer layer and the second spacer layer is greater than 5:1.

[0024] Optionally, the material of the second sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide and tetraethyl orthosilicate.

[0025] Optionally, the target layer is a dielectric layer, and the target pattern is an interconnection groove; the forming method further comprises: after forming the interconnection groove, forming a metal interconnection line in the interconnection groove.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] An embodiment of the present invention provides a method for forming a semiconductor structure, which comprises removing a portion of the width of the first sacrificial layer located at the junction of a pattern definition layer and a first sacrificial layer in a second direction, forming an opening extending along the first direction and surrounded by the pattern definition layer, a target layer and the remaining first sacrificial layer, forming a first sidewall layer on the sidewall of the opening, removing a portion of the width of the first sacrificial layer in the second direction, forming a groove extending along the first direction and surrounded by the opposite sidewalls of the remaining first sacrificial layer and the target layer in the first sacrificial layer, forming a second sidewall layer on the sidewall of the groove, and after forming the first sidewall layer and the second sidewall layer, removing the remaining first sacrificial layer. After removing the remaining first sacrificial layer, etching the target layer using the first sidewall layer and the second sidewall layer as masks to form a target pattern. In the embodiment of the present invention, the first sacrificial layer is divided successively along the second direction in different steps to form openings and grooves respectively. Compared with the scheme of forming the openings and grooves in the same step, this increases the process window of the photolithography process used when forming the openings and grooves. Moreover, after removing the first sacrificial layer, the target layer is etched using the first side wall layer and the second side wall layer as a mask, which reduces the pitch of the target pattern formed. Therefore, the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the photolithography process, and it is beneficial to further reduce the pitch between the target patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] Currently, due to the limitation of lithography equipment, the width of metal lines formed in semiconductor devices is too large and cannot meet the process requirements of smaller and smaller metal line widths, making it difficult to further reduce the pitch between target graphics.

[0030] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer extending along a first direction and penetrating the pattern definition layer formed in the pattern definition layer, and an etching selectivity ratio between the first sacrificial layer and the pattern definition layer; removing a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction, forming an opening extending along the first direction and surrounded by the pattern definition layer, the target layer and the remaining first sacrificial layer; forming a first sidewall layer on the sidewall of the opening; removing a portion of the width of the first sacrificial layer in the second direction, forming a groove in the first sacrificial layer extending along the first direction and surrounded by the opposite sidewalls of the remaining first sacrificial layer and the target layer; forming a second sidewall layer on the sidewall of the groove; after forming the first sidewall layer and the second sidewall layer, removing the remaining first sacrificial layer; after removing the remaining first sacrificial layer, etching the target layer using the first sidewall layer and the second sidewall layer as masks to form a target pattern.

[0031] In the scheme disclosed in the embodiment of the present invention, a portion of the width of the first sacrificial layer located at the junction of the graphic definition layer and the first sacrificial layer in the second direction is removed to form an opening extending along the first direction and surrounded by the graphic definition layer, the target layer and the remaining first sacrificial layer, a first sidewall layer is formed on the sidewall of the opening, a portion of the width of the first sacrificial layer in the second direction is removed, a groove extending along the first direction and surrounded by the relative sidewalls of the remaining first sacrificial layer and the target layer is formed in the first sacrificial layer, a second sidewall layer is formed on the sidewall of the groove, after the first sidewall layer and the second sidewall layer are formed, the remaining first sacrificial layer is removed, and after the remaining first sacrificial layer is removed, the target layer is etched using the first sidewall layer and the second sidewall layer as masks to form a target graphic. In the embodiment of the present invention, the first sacrificial layer is divided successively along the second direction in different steps to form openings and grooves respectively. Compared with the scheme of forming the openings and grooves in the same step, this increases the process window of the photolithography process used when forming the openings and grooves. Moreover, after removing the first sacrificial layer, the target layer is etched using the first side wall layer and the second side wall layer as a mask, which reduces the pitch of the target pattern formed. Therefore, the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the photolithography process, and it is beneficial to further reduce the pitch between the target patterns.

[0032] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figures 1 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0034] refer to Figure 1 to Figure 2 , providing a substrate, including a target layer 100 for forming a target pattern, a pattern definition layer 101 formed on the target layer 100, and a pattern definition layer 101 formed in the pattern definition layer 101 along a first direction (such as Figure 2 The first sacrificial layer 106 extends (as shown in the Y direction) and penetrates the pattern definition layer 101, and an etching selectivity ratio is established between the first sacrificial layer 106 and the pattern definition layer 101.

[0035] The substrate is used to provide a process platform for subsequent process steps.

[0036] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.

[0037] The target layer 100 is used as a material layer that needs to be patterned to form a target pattern.

[0038] Among them, the target graphics can be gate structures, interconnect grooves in the back end of line (BEOL) process, fins in fin field effect transistors (FinFETs), channel stacks in all-around gate (GAA) transistors or forksheet transistors, hard mask (HM) layers and other graphics.

[0039] In this embodiment, the target layer 100 is a dielectric layer, and the target layer 100 is subsequently patterned to form a plurality of interconnection grooves in the target layer 100, and then metal interconnection lines are formed in the interconnection grooves. The target layer 100 is used to achieve electrical isolation between metal interconnection lines in the back-end process.

[0040] To this end, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride, etc.

[0041] In this embodiment, the material of the target layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end interconnects and further reduce the back-end RC delay. Specifically, the material of the target layer 100 can be SiOCH.

[0042] In this embodiment, the substrate further includes a hard mask material layer (not shown) located on the target layer 100 and an etch stop layer (not shown) located on the hard mask material layer.

[0043] The hard mask material layer is used to form a hard mask layer (not shown) after a subsequent patterning process.

[0044] Specifically, the pattern is subsequently transferred to the hard mask material layer to form a hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of patterning.

[0045] In this embodiment, the material of the hard mask material layer is silicon nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride or tungsten nitride.

[0046] The subsequent process includes multiple graphic definition processing. The etch stop layer is used to define the etching stop position in the etching process of the subsequent graphic definition processing, which is beneficial to reduce the loss of the target layer 100 and improve the depth consistency of the etching process, thereby improving the effect of the subsequent graphic process.

[0047] In this embodiment, the material of the etch stop layer is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride or aluminum nitride.

[0048] In this embodiment, the pattern definition layer 101 and the first sacrificial layer 106 are formed on the etch stop layer.

[0049] In this embodiment, a first sacrificial layer 106 extending along a first direction and penetrating the pattern definition layer 101 is formed in the pattern definition layer 101. The first direction refers to the extending direction of the first sacrificial layer 106 in a top view.

[0050] In this embodiment, the direction parallel to the substrate surface and perpendicular to the first direction is the second direction (eg Figure 2 X direction).

[0051] In this embodiment, there is an etching selectivity ratio between the first sacrificial layer 106 and the pattern definition layer 101 .

[0052] It should be noted that the first sacrificial layer 106 will be removed later, and in the process of etching the target layer 100 using the first side wall layer and the second side wall layer as masks, the target layer 100 will also be etched using the graphic definition layer 101 as a mask. To this end, by having an etching selectivity ratio between the first sacrificial layer 106 and the graphic definition layer 101, the graphic definition layer 101 is retained while the first sacrificial layer 106 is removed, and the probability of damage is low.

[0053] The etching selectivity between the first sacrificial layer 106 and the pattern definition layer 101 means that under the same etching process conditions, the etching rates of the first sacrificial layer 106 and the pattern definition layer 101 are different.

[0054] In this embodiment, the steps of forming the first sacrificial layer 106 and the graphic definition layer 101 include: forming a graphic material layer 200 on the top of the target layer 100; performing doping treatment on a partial area of ​​the graphic material layer 200, and the graphic material layer 200 doped with ions serves as the graphic definition layer 101, and the remaining graphic material layer 200 not doped with ions serves as the first sacrificial layer 106.

[0055] The pattern material layer 200 provides a process basis for forming the pattern definition layer 101 and the first sacrificial layer 106 .

[0056] The material of the pattern material layer 200 is amorphous silicon.

[0057] It should be noted that the lattice structure of amorphous silicon has an unstable characteristic, and it is easy to subsequently dope ions into the graphic material layer 200 by doping the graphic material layer 200 to change the etching rate of the amorphous silicon material, thereby creating an etching selectivity ratio between the first sacrificial layer 106 and the graphic definition layer 101.

[0058] In this embodiment, the pattern material layer 200 is doped by using an ion implantation process.

[0059] It should be noted that the ion implantation process has the characteristics of uniformly implanting ions over a large area, more accurately controlling the ion doping depth and high repeatability.

[0060] Specifically, after the graphic material layer 200 is doped, the graphic material layer 200 doped with ions serves as the graphic definition layer 101, and the graphic material layer 200 not doped with ions serves as the first sacrificial layer 106. There is an etching selectivity ratio between the graphic definition layer 101 and the first sacrificial layer 106, which provides a process basis for the subsequent removal of the first sacrificial layer 106.

[0061] In this embodiment, the doping depth of the doping treatment is the entire thickness of the graphic material layer 200 .

[0062] In this embodiment, in the step of performing doping treatment on the pattern material layer 200, the doping ions include boron ions, phosphorus ions or argon ions.

[0063] refer to Figure 1 Before the graphic material layer 200 is doped, the method for forming the semiconductor structure further includes: forming a first mask layer 105 on the top of the graphic material layer 200 , wherein the first mask layer 105 covers a portion of the top of the graphic material layer 200 .

[0064] The first mask layer 105 is used to shield the region of the pattern material layer 200 that is not desired to be doped.

[0065] In this embodiment, the first mask layer 105 includes a first organic material layer 102 , a first anti-reflection coating layer 103 located on the first organic material layer 102 , and a first photoresist layer 104 located on the first anti-reflection coating layer 103 .

[0066] The material of the first organic material layer 102 includes an organic material. In this embodiment, the material of the organic material layer 102 is spin-on carbon (SOC). In other embodiments, the material of the organic material layer can also be other organic materials, such as: one or more of ODL (organic dielectric layer) materials, DUO (Deep UV Light Absorbing Oxide) materials and APF (Advanced Patterning Film) materials.

[0067] The material of the first anti-reflective coating 103 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0068] In this embodiment, during the process of forming the first mask layer 105 , the first anti-reflective coating layer 103 and the organic material layer 102 are sequentially etched using the first photoresist layer 104 as a mask.

[0069] In this embodiment, after the pattern material layer 200 is doped, the process further includes: removing the remaining first mask layer 105

[0070] It should be noted that in other embodiments, during the doping process of the graphic material layer in a partial area, the graphic material layer doped with ions may be used as the first sacrificial layer, and the remaining graphic material layer not doped with ions may be used as the graphic definition layer.

[0071] refer to Figure 3 to Figure 4 , remove the second direction (such as Figure 4 The first sacrificial layer 106 has a width of part of the width located at the junction of the pattern definition layer 101 and the first sacrificial layer 106, forming a first direction (as shown in the X direction) Figure 4 An opening 112 extends (as shown in the Y direction) and is surrounded by the pattern definition layer 101, the target layer 100 and the remaining first sacrificial layer 106.

[0072] The opening 112 provides a space for subsequently forming the first spacer layer and the second sacrificial layer.

[0073] In this embodiment, the step of forming the opening 112 includes: forming a second mask layer 110 having a first mask opening 210 on the top of the first sacrificial layer 106 and the graphic definition layer 101, the first mask opening 210 extending along the first direction and exposing the top of the first sacrificial layer 106 with a partial width at the junction of the graphic definition layer 101 and the first sacrificial layer 106 in the second direction; using the second mask layer 110 as a mask, removing the exposed first sacrificial layer 106 along the first mask opening 210 to form an opening 112.

[0074] In this embodiment, an anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer 106 located at the junction of the pattern definition layer 101 and the first sacrificial layer 106 in the second direction.

[0075] The anisotropic dry etching process has the characteristic of anisotropic etching, so its longitudinal etching rate is much greater than the lateral etching rate, and can obtain quite accurate pattern transfer, thereby improving the sidewall morphology quality of the opening 112 .

[0076] In this embodiment, the sidewall of the first mask opening 210 close to the pattern definition layer 101 is flush with the sidewall of the first sacrificial layer 106 .

[0077] It should be noted that, since there is an etching selectivity ratio between the first sacrificial layer 106 and the pattern definition layer 101, the process window of the photolithography process is increased during the process of forming the first mask opening 210. For example, in other embodiments, the first mask opening may also expose a portion of the width of the pattern definition layer at the junction of the pattern definition layer and the first sacrificial layer.

[0078] In this embodiment, in the step of forming the openings 112 , along the second direction, the size of the remaining first sacrificial layer 106 between the openings 112 is larger than the size of the openings 112 .

[0079] It should be noted that a groove will be formed in the remaining first sacrificial layer 106 later, and the remaining first sacrificial layer 106 between the openings 112 provides a spatial position for the groove. For this reason, in this embodiment, the size of the remaining first sacrificial layer 106 between the openings 112 is larger than the size of the openings 112, thereby increasing the process window for the subsequent formation of the groove.

[0080] In this embodiment, the size of the remaining first sacrificial layer 106 between the openings 112 is greater than four times the size of the openings 112 .

[0081] It should be noted that the ratio between the size of the remaining first sacrificial layer 106 and the size of the opening 112 should not be too small. If the ratio is too small, when the size of the opening 112 meets the process requirements, it is easy to cause the size of the remaining first sacrificial layer 106 between the openings 112 to be too small. After the groove is subsequently formed in the remaining first sacrificial layer 106, the target pattern formed in the target layer below the groove is affected, resulting in the target pattern failing to meet the process requirements, thereby affecting the performance of the semiconductor. For this reason, in this embodiment, the size of the remaining first sacrificial layer 106 between the openings 112 is greater than 4 times the size of the opening 112.

[0082] In this embodiment, after the opening 112 is formed, the method further includes: removing the remaining second mask layer 110 .

[0083] In this embodiment, the second mask layer 110 includes a second organic material layer 107 , a second anti-reflection coating layer 108 located on the second organic material layer 107 , and a second photoresist layer 109 located on the second anti-reflection coating layer 108 .

[0084] The specific description of the second mask layer 110 can be combined with reference to the corresponding description of the first mask layer 105, which will not be repeated here.

[0085] refer to Figure 5 , a first spacer layer 113 is formed on the sidewall of the opening 112 .

[0086] In the subsequent process of forming a target pattern in the target layer 100 , the first spacer layer 113 is used as an etching mask.

[0087] It should be noted that by forming the first spacer layer 113 on the sidewall of the opening 112 , the size of the opening 112 along the second direction is reduced, thereby meeting the requirement of continuously reducing the line width of the target pattern while increasing the process window of the photolithography process.

[0088] In this embodiment, along the second direction (such as Figure 5 (shown in the X direction), the size of the first spacer layer 113 is equal to the size of the second spacer layer to be formed subsequently.

[0089] It should be noted that the size of the first spacer layer 113 is equal to the size of the second spacer layer to be formed subsequently, so that the intervals between the subsequent adjacent target patterns are equal.

[0090] In this embodiment, along the second direction, the size of the first spacer layer 113 is 10 nanometers to 20 nanometers.

[0091] It should be noted that the size of the first sidewall layer 113 should not be too large or too small. If the size of the first sidewall layer 113 is too large, it is easy to occupy too much space of the opening 112, which may cause the size of the target pattern to be formed later to be too small, which may result in the target pattern not being able to meet the line width requirement, or the interval between the target patterns not being able to reach the minimum design interval, thereby affecting the performance of the metal interconnection line; if the size of the first sidewall layer 113 is too small, it may cause the remaining space of the opening 112 to be too large, which may cause the target pattern formed by etching the target layer 100 using the first sidewall layer 113 as a mask to be too large, which may result in the target pattern not being able to meet the requirement of the continuously shrinking line width of the target pattern, thereby affecting the performance of the metal interconnection line, or, in order to make the line width of the target pattern meet the process requirements, it is necessary to reduce the size of the opening 112 accordingly, thereby easily reducing the process window for forming the opening 112. To this end, in this embodiment, along the second direction, the size of the first sidewall layer 113 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the first spacer layer 113 is 13 nanometers, 15 nanometers or 17 nanometers.

[0092] It should be noted that, in the present embodiment, the size of the first spacer layer 113 along the second direction is small, so that a smaller interval is achieved between subsequent adjacent target patterns.

[0093] In this embodiment, the process of forming the first spacer layer 113 includes an atomic layer deposition process.

[0094] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the first spacer layer 113, so that the first spacer layer 113 can cover the sidewalls of the pattern definition layer 101 and the first sacrificial layer 106. In other embodiments, the first spacer layer can also be formed by a chemical vapor deposition process (CVD).

[0095] It should be noted that the first spacer layer 113 is used as an etching mask for subsequently etching the target layer 100 .

[0096] In this embodiment, the material of the first spacer layer 113 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride or aluminum oxide. In this embodiment, the material of the first spacer layer 113 is titanium oxide. The etching selectivity of titanium oxide material and amorphous silicon or spin-on glass is relatively large, and the first spacer layer 113 can be retained in the subsequent process of removing the first sacrificial layer 106 and the second sacrificial layer to form a target pattern, and the target layer 100 can be etched using the first spacer layer 113 as a mask.

[0097] In this embodiment, the step of forming the first side wall layer 113 includes: forming a first side wall material layer (not shown) on the top and side walls of the graphic definition layer 101 and the first sacrificial layer 106, and at the bottom of the opening 112, removing the first side wall material layer at the top of the graphic definition layer 101, the top of the first sacrificial layer 106 and the bottom of the opening 112, and the remaining first side wall material layer serves as the first side wall layer 113.

[0098] refer to Figures 6 to 8 , remove the second direction (such as Figure 8 The first sacrificial layer 106 has a partial width along the first direction (as shown in the X direction), and a first sacrificial layer 106 is formed along the first direction (as shown in the X direction). Figure 8 A groove 121 is formed by the opposite side walls of the remaining first sacrificial layer 106 and the target layer 100 and extends in the Y direction.

[0099] The groove 121 provides a space for subsequently forming the second spacer layer.

[0100] It should be noted that, in this embodiment, the first sacrificial layer 106 is divided along the second direction in different steps to form the opening 112 and the groove 121 respectively. Compared with the scheme of forming the opening 112 and the groove 121 in the same step, this increases the process window of the photolithography process used when forming the opening 112 and the groove 121. Moreover, after removing the first sacrificial layer 106, the target layer 100 is etched using the first sidewall layer 113 and the second sidewall layer as a mask, which reduces the pitch of the target pattern formed. Therefore, the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the photolithography process, and it is beneficial to further reduce the pitch between the target patterns.

[0101] In this embodiment, the first spacer layer 113 is first formed on the sidewall of the opening 112 , and then the groove 121 is formed.

[0102] In this embodiment, the step of forming the groove 121 includes: forming a third mask layer 120 having a second mask opening 310 on the top of the first sacrificial layer 106, the graphic definition layer 101 and the first sidewall layer 113, the second mask opening 310 exposing a partial width of the top of the first sacrificial layer 106 in the second direction; using the third mask layer 120 as a mask, removing a portion of the remaining first sacrificial layer 106 along the second mask opening 310 to form a groove 121 that penetrates the first sacrificial layer 106.

[0103] In this embodiment, an anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer 106 in the second direction.

[0104] The anisotropic dry etching process has the characteristic of anisotropic etching, so its longitudinal etching rate is much greater than the lateral etching rate, and can obtain quite accurate pattern transfer, thereby improving the sidewall morphology quality of the groove 121.

[0105] In this embodiment, after the groove 121 is formed, the method further includes: removing the remaining third mask layer 120 .

[0106] In this embodiment, the third mask layer 120 includes a third organic material layer 116 , a second anti-reflective coating layer 117 located on the third organic material layer 116 , and a second photoresist layer 118 located on the second anti-reflective coating layer 117 .

[0107] The specific description of the third mask layer 120 can be combined with reference to the corresponding description of the first mask layer 105, which will not be repeated here.

[0108] Combined with reference Figure 6After forming the opening 112 and before forming the groove 121 , the method further includes: forming a second sacrificial layer 115 in the opening 112 .

[0109] The second sacrificial layer 115 occupies a space for subsequently forming a target pattern.

[0110] In addition, the second sacrificial layer 115 fills the opening 112. During the process of forming the groove 121, the second sacrificial layer 115 provides a flat surface for the formation of the third mask layer 120, which is beneficial to improve the flatness of the top surface of the third mask layer 120, thereby improving the accuracy of the position, size and morphology of the second mask opening 310.

[0111] The second sacrificial layer 115 is made of organic material.

[0112] It should be noted that the etching selectivity between the organic material and the materials of the first spacer layer 113 and the subsequently formed second spacer layer is relatively large, which is conducive to the subsequent removal of the second sacrificial layer 115 and reduces damage to the first spacer layer 113 and the second spacer layer.

[0113] In this embodiment, the material of the second sacrificial layer 115 includes one or more of spin-on glass, ion-enhanced silicon oxide and tetraethyl orthosilicate.

[0114] refer to Fig. 9 A second spacer layer 123 is formed on the sidewall of the groove 121 .

[0115] It should be noted that, by forming a second sidewall layer 123 on the exposed sidewall of the groove 121 and reducing the size of the groove 121 along the second direction, it is possible to meet the requirement of continuously reducing the line width of the target pattern while increasing the process window of the lithography process. At the same time, in the subsequent process of forming the target pattern in the target layer 100, the second sidewall layer 123 will also be used as an etching mask, that is, the second sidewall layer 123 and the first sidewall layer 113 will jointly serve as masks for the subsequent etching of the target layer 100.

[0116] In this embodiment, along the second direction, the size of the second spacer layer 123 is 10 nanometers to 20 nanometers.

[0117] It should be noted that the size of the second spacer layer 123 should not be too large or too small. If the size of the second spacer layer 123 is too large, it is easy to occupy too much space of the groove 121, which may cause the size of the target pattern to be formed later to be too small, which may result in the target pattern not being able to meet the line width requirement, or the spacing between the target patterns not being able to reach the minimum design spacing, thereby affecting the performance of the metal interconnection line; if the size of the second spacer layer 123 is too small, it is easy to cause the remaining space of the groove 121 to be too large, which may cause the target pattern formed by etching the target layer 100 using the second spacer layer 123 as a mask to be too large, which may result in the target pattern not being able to meet the requirement of the continuously shrinking line width of the target pattern, thereby affecting the performance of the metal interconnection line, or, in order to make the line width of the target pattern meet the process requirements, it is necessary to reduce the size of the groove 121 accordingly, thereby easily reducing the process window for forming the groove 121. To this end, in this embodiment, along the second direction, the size of the second spacer layer 123 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the second spacer layer 123 is 13 nanometers, 15 nanometers or 17 nanometers.

[0118] It should be noted that, in this embodiment, the size of the second spacer layer 123 along the second direction is small, so that a smaller interval is achieved between subsequent adjacent target patterns.

[0119] In this embodiment, the process of forming the second spacer layer 123 includes an atomic layer deposition process.

[0120] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the second spacer layer 123, so that the second spacer layer 123 can cover the sidewall of the first sacrificial layer 106. In other embodiments, the first spacer layer can also be formed by a chemical vapor deposition process (CVD).

[0121] In this embodiment, the material of the second spacer layer 123 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride or aluminum oxide. In this embodiment, the material of the second spacer layer 123 is titanium oxide. The etching selectivity of titanium oxide material and amorphous silicon or spin-on glass is relatively large, and the second spacer layer 123 can be retained in the process of subsequently removing the first sacrificial layer 106 and the second sacrificial layer 115 to form the target pattern, and the target layer 100 can be etched using the second spacer layer 123 as a mask.

[0122] In this embodiment, the step of forming the second side wall layer 123 includes: forming a second side wall material layer (not shown) on the top of the graphic definition layer 101, the second sacrificial layer 115, the first sacrificial layer 106 and the first side wall layer 113, and on the bottom and side wall of the groove 121, removing the second side wall material layer on the top of the graphic definition layer 101, the first sacrificial layer 106, the first side wall layer 113 and the second sacrificial layer 115 and on the bottom of the groove 121, and the remaining second side wall material layer serves as the second side wall layer 123.

[0123] refer to Fig.10 After forming the first spacer layer 113 and the second spacer layer 123 , the remaining first sacrificial layer 106 is removed.

[0124] It should be noted that the remaining first sacrificial layer 106 is removed to expose the area to be etched.

[0125] In this embodiment, the process of removing the first sacrificial layer 106 includes one or both of an ashing process and a wet etching process.

[0126] The ashing process and wet etching process have the characteristics of high efficiency and low cost in the process of removing organic materials, and can reduce damage to the underlying film layer.

[0127] In this embodiment, in the step of removing the first sacrificial layer 106 , the etching selectivity ratio of the first sacrificial layer 106 to the first spacer layer 113 and the second spacer layer 123 is greater than 5:1.

[0128] It should be noted that the etching selectivity ratio of the first sacrificial layer 106 to the first spacer layer 113 and the second spacer layer 123 should not be too small. If the etching selectivity ratio of the first sacrificial layer 106 to the first spacer layer 113 and the second spacer layer 123 is too small, it is easy to cause a portion of the first sacrificial layer 106 to remain, affecting the subsequent process of forming the target pattern in the target layer 100, thereby affecting the performance of the semiconductor. For this reason, in the present embodiment, in the step of removing the first sacrificial layer 106, the etching selectivity ratio of the first sacrificial layer 106 to the first spacer layer 113 and the second spacer layer 123 is greater than 5:1.

[0129] Continue to refer Fig.10 In this embodiment, before the target layer 100 is subsequently etched using the first spacer layer 113 and the second spacer layer 123 as masks, the process further includes: removing the second sacrificial layer 115 .

[0130] It should be noted that the second sacrificial layer 115 is removed to expose the area to be etched.

[0131] In this embodiment, the process of removing the second sacrificial layer 115 includes one or both of an ashing process and a wet etching process.

[0132] The ashing process and wet etching process have the characteristics of high efficiency and low cost in the process of removing organic materials, and can reduce damage to the underlying film layer.

[0133] It should be noted that the etching selectivity ratio of the second sacrificial layer 115 to the first spacer layer 113 and the second spacer layer 123 should not be too small. If the etching selectivity ratio of the second sacrificial layer 115 to the first spacer layer 113 and the second spacer layer 123 is too small, it is easy to cause a portion of the second sacrificial layer 115 to remain, affecting the subsequent process of forming the target pattern in the target layer 100, thereby affecting the performance of the semiconductor. For this reason, in the present embodiment, in the step of removing the second sacrificial layer 115, the etching selectivity ratio of the second sacrificial layer 115 to the first spacer layer 113 and the second spacer layer 123 is greater than 5:1.

[0134] refer to Fig.11 After removing the remaining first sacrificial layer 106 , the target layer 100 is etched using the first spacer layer 113 and the second spacer layer 123 as masks to form a target pattern 126 .

[0135] It can be seen from the above records that this embodiment can meet the requirement of continuously reducing the line width of the target graphic 126 while increasing the process window of the lithography process, and is conducive to further reducing the pitch between the target graphics 126, which correspondingly improves the graphic accuracy and graphic quality of the target graphic 126.

[0136] It should be noted that the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the first spacer layer 113 and the second spacer layer 123 as masks, the target pattern 126 is an interconnection groove.

[0137] In this embodiment, a hard mask material layer (not shown) and an etch stop layer (not shown) are further formed on the target layer 100 , and the bottoms of the opening 112 and the groove 121 expose the etch stop layer.

[0138] Therefore, using the first side wall layer 113 and the second side wall layer 123 as masks, the etching stop layer and the hard mask material layer at the bottom of the opening 112 and the groove 121 are etched in sequence, and after the remaining hard mask material layer is used as a hard mask layer (not shown), the target layer 100 is etched using the hard mask layer as a mask.

[0139] By first transferring the patterns of the opening 112 and the groove 121 to the hard mask material layer to form a hard mask layer, it is beneficial to improve the process stability and process effect of etching the target layer 100 and improve the accuracy of pattern transfer.

[0140] refer to Fig.12 The forming method further includes: after forming the interconnection groove, forming a metal interconnection line 128 in the interconnection groove.

[0141] The metal interconnection line 128 is used to realize electrical connection between the semiconductor structure and external circuits or other interconnection structures.

[0142] It can be seen from the above records that the present embodiment can meet the requirement of continuously reducing the line width of the interconnection grooves while increasing the process window of the photolithography process, and the spacing between adjacent interconnection grooves is easy to meet the designed minimum spacing, which is correspondingly conducive to making the spacing of the metal interconnection lines 128 meet the designed minimum spacing, which is conducive to further reducing the pitch between the metal interconnection lines 128, and is also conducive to improving the graphic accuracy of the metal interconnection lines 128, and further conducive to improving the electrical connection performance of the metal interconnection lines 128.

[0143] In this embodiment, the material of the metal interconnection line 128 is copper. In other embodiments, the material of the metal interconnection line can also be a conductive material such as aluminum.

[0144] In this embodiment, the metal interconnection line 128 is formed in the interconnection groove by using copper electroplating.

[0145] Accordingly, the process of forming the metal interconnection line 128 includes a step of filling with a conductive material and a step of planarizing the conductive material to remove the conductive material above the top of the dielectric layer.

[0146] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0147] The chemical mechanical polishing process enables the metal interconnection line 128 formed in the interconnection groove to have a flat surface, thereby improving the electrical connection effect of the metal interconnection line 128 .

[0148] In this embodiment, during the process of forming the metal interconnection line 128, the remaining graphic definition layer 101, the first sidewall layer 113, the second sidewall layer 123, the etch stop layer and the hard mask layer are also removed to expose the top surface of the target layer 100 in preparation for subsequent processes.

[0149] The detailed description of the metal interconnection line 128 is omitted here.

[0150] It should be noted that, in this embodiment, the groove 121 is formed after the first spacer layer 113 is formed on the sidewall of the opening 112. Accordingly, the process window of the photolithography process used when forming the opening 112 and the groove 121 is increased, and the requirement of continuously reducing the line width of the target pattern to be formed subsequently is also met.

[0151] In other embodiments, the opening may be formed after the second spacer layer is formed on the sidewall of the groove, thereby increasing the process window of the photolithography process used to form the opening and the groove, and also meeting the requirement of continuously reducing the line width of the target pattern to be formed subsequently.

[0152] In some other embodiments, the groove is formed after the opening is formed, and after the groove is formed, the first spacer layer and the second spacer layer are formed in the same step. Accordingly, the process window of the photolithography process used to form the opening and the groove is increased, and the requirement of continuously reducing the line width of the target pattern formed subsequently is also met.

[0153] In other embodiments, after forming the groove, the opening is formed, and after forming the opening, the first spacer layer and the second spacer layer are formed in the same step. Accordingly, the process window of the photolithography process used to form the opening and the groove is increased, and the requirement of continuously reducing the line width of the target pattern formed subsequently is also met.

[0154] Correspondingly, when the opening is formed after the groove is formed, before the opening is formed, the method further includes: forming a second sacrificial layer in the groove.

[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer extending along a first direction and penetrating the pattern definition layer formed in the pattern definition layer, and an etching selectivity ratio between the first sacrificial layer and the pattern definition layer; removing a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction to form an opening extending along the first direction and surrounded by the pattern definition layer, the target layer and the remaining first sacrificial layer; forming a first spacer layer on the sidewall of the opening; removing a portion of the width of the first sacrificial layer in the second direction, and forming a groove in the first sacrificial layer extending along the first direction and surrounded by opposite side walls of the remaining first sacrificial layer and the target layer; forming a second spacer layer on the sidewall of the groove; After forming the first spacer layer and the second spacer layer, removing the remaining first sacrificial layer; After removing the remaining first sacrificial layer, the target layer is etched using the first sidewall layer and the second sidewall layer as masks to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming a first spacer layer on the sidewall of the opening, forming the groove; Alternatively, the opening is formed after a second spacer layer is formed on the sidewall of the groove; Alternatively, after forming the opening, the groove is formed, and after forming the groove, the first spacer layer and the second spacer layer are formed in the same step; Alternatively, after forming the groove, the opening is formed, and after forming the opening, the first spacer layer and the second spacer layer are formed in the same step.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein: After forming the opening, the groove is formed, and before forming the groove, the method further includes: forming a second sacrificial layer in the opening; or after forming the groove, the opening is formed, and before forming the opening, the method further includes: forming a second sacrificial layer in the groove; Before etching the target layer using the first spacer layer and the second spacer layer as masks, the method further includes: removing the second sacrificial layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first sacrificial layer and the pattern definition layer includes: forming a pattern material layer on top of the target layer; Doping treatment is performed on a partial area of ​​the graphic material layer, the graphic material layer doped with ions is used as a graphic definition layer, and the remaining graphic material layer not doped with ions is used as a first sacrificial layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The graphic material layer is doped by using an ion implantation process.

6. The method for forming a semiconductor structure according to claim 4, wherein: The material of the graphic material layer is amorphous silicon; In the step of doping the pattern material layer, the doping ions include boron ions, phosphorus ions or argon ions.

7. The method for forming a semiconductor structure according to claim 1, wherein: An anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer located at the junction of the pattern definition layer and the first sacrificial layer in the second direction.

8. The method for forming a semiconductor structure according to claim 1, wherein: An anisotropic dry etching process is used to remove a portion of the width of the first sacrificial layer in the second direction.

9. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, a size of the first spacer layer is equal to a size of the second spacer layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, a size of the first spacer layer is 10 nanometers to 20 nanometers, and a size of the second spacer layer is 10 nanometers to 20 nanometers.

11. The method for forming a semiconductor structure according to claim 1, wherein: After forming the opening, forming the groove; In the step of forming the openings, along the second direction, a size of the remaining first sacrificial layer between the openings is larger than a size of the openings.

12. The method for forming a semiconductor structure according to claim 11, wherein: The size of the remaining first sacrificial layer between the openings is greater than four times the size of the openings.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first spacer layer includes an atomic layer deposition process.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the second spacer layer includes an atomic layer deposition process.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first sacrificial layer includes one or both of an ashing process and a wet etching process.

16. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the second sacrificial layer includes one or both of an ashing process and a wet etching process.

17. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the first sacrificial layer, an etching selection ratio of the first sacrificial layer to the first spacer layer and the second spacer layer is greater than 5:

1.

18. The method for forming a semiconductor structure according to claim 3, wherein: In the step of removing the second sacrificial layer, an etching selection ratio of the second sacrificial layer to the first spacer layer and the second spacer layer is greater than 5:

1.

19. The method for forming a semiconductor structure according to claim 3, wherein: The material of the second sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide and tetraethyl orthosilicate.

20. The method for forming a semiconductor structure according to claim 1, wherein: The target layer is a dielectric layer, and the target pattern is an interconnection groove; The forming method further includes: after forming the interconnection groove, forming a metal interconnection line in the interconnection groove.

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