3D Flash Device and Method for Preparing the Same

Abstract

The present invention provides a three-dimensional flash memory device and a manufacturing method thereof, including: a stacked structure layer located on the substrate and including a plurality of first strip structures and second strip structures, the first strip structures extending along the X direction and arranged along the Y direction, the second strip structures extending along the Y direction and arranged along the X direction, and the length of the first strip structures gradually decreasing from bottom to top in a stepped manner; a plurality of gate structures, each gate structure being located between two adjacent first strip structures; a plurality of doped regions located in each polysilicon layer of the first strip structures; a metal interconnect structure including a plurality of electrical connectors, the electrical connectors being electrically connected to the corresponding doped regions, the control gates, and the select gates. The present invention facilitates improving the integration degree of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a three-dimensional flash memory device and a method for manufacturing the same. Background Art

[0002] As a special structure of electrically erasable and programmable read-only memory, flash memory has now occupied most of the market share of non-volatile semiconductor memories and has become the fastest-growing non-volatile semiconductor memory. NAND Flash memory and NOR Flash memory are two main non-volatile flash memory technologies in the market. Due to the different structures of NAND Flash memory and NOR Flash memory, NAND Flash memory is often manufactured by a three-dimensional stacking method, and the channel direction in the flash memory is perpendicular to the surface of the substrate, so that the integration degree of NAND Flash memory is relatively high; while the structure of NOR Flash memory is generally planar, and the planar structure is limited by the process node, resulting in limited density of flash memory cells in the flash memory device, thus reducing the integration degree of the flash memory device and increasing its volume; if a three-dimensional stacking method is used to manufacture NOR Flash memory, the source region, drain region, control gate, and select gate in the NOR Flash memory will be vertically stacked, making the integration process difficult. Summary of the Invention

[0003] The purpose of the present invention is to provide a three-dimensional flash memory device and a method for manufacturing the same, which are convenient for improving the integration degree of the flash memory device.

[0004] To achieve the above purpose, the present invention provides a three-dimensional flash memory device, including:

[0005] A substrate;

[0006] A stacked structure layer, located on the substrate, and including a plurality of first strip-shaped structures and second strip-shaped structures. The first strip-shaped structures extend along the X direction and are arranged along the Y direction, and the second strip-shaped structures extend along the Y direction and are arranged along the X direction. The first strip-shaped structures include a plurality of polysilicon layers, and the second strip-shaped structures include a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is the first oxide layer. The polysilicon layers in the second strip-shaped structures correspond one by one to the polysilicon layers in the first strip-shaped structures, and the corresponding polysilicon layers are arranged on the same layer. The first oxide layer is located between two adjacent first strip-shaped structures, and the length of the polysilicon layers in the first strip-shaped structures gradually decreases from bottom to top in a stepped manner;

[0007] A plurality of gate structures, each gate structure is located between two adjacent first strip-shaped structures, and includes a control gate and a select gate. There is a spacing between the control gate and the select gate, and both span across the second strip-shaped structures;

[0008] A plurality of doped regions, located in each polysilicon layer of the first strip structure;

[0009] A metal interconnect structure, located on the stacked structure layer and the gate structure, which includes a plurality of electrical connectors, and the electrical connectors are electrically connected to the corresponding doped regions, the control gate and the select gate.

[0010] Optionally, it further includes an ONO structure layer, spanning the second strip structure and located between the control gate and the second strip structure.

[0011] Optionally, it further includes a second oxide layer, spanning the second strip structure and located between the select gate and the second strip structure.

[0012] Optionally, it further includes sidewalls, covering the sides of the gate structure.

[0013] Optionally, a plurality of first trenches are formed in the substrate, and a third oxide layer is filled in a part of the depth of the first trenches, and the gate structure extends to cover the sidewalls of the remaining depth of the first trenches.

[0014] The present invention also provides a method for manufacturing a three-dimensional flash memory device, including:

[0015] Providing a substrate;

[0016] Forming a stacked structure layer on the substrate, the stacked structure layer includes a plurality of first strip structures and second strip structures, and forming a plurality of gate structures, each of the gate structures is located between two adjacent first strip structures;

[0017] Forming a plurality of doped regions in each polysilicon layer of the first strip structure; and,

[0018] Forming a metal interconnect structure on the stacked structure layer and the gate structure;

[0019] Wherein, the first strip structure extends along the X direction and is arranged along the Y direction, the second strip structure extends along the Y direction and is arranged along the X direction, the first strip structure includes a plurality of polysilicon layers, the second strip structure includes a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is the first oxide layer, the polysilicon layers in the second strip structure correspond to the polysilicon layers in the first strip structure one by one and the corresponding polysilicon layers are arranged in the same layer, the first oxide layer is located between two adjacent first strip structures, and the length of the polysilicon layers in the first strip structure gradually decreases from bottom to top in a stepped shape;

[0020] The gate structure includes a control gate and a select gate, with a spacing between the control gate and the select gate, and both spanning across the second strip structure;

[0021] The source region and the drain region are located in each polysilicon layer of the corresponding first strip structure;

[0022] The metal interconnect structure includes a number of electrical connectors, which are electrically connected to the corresponding doped regions, the control gate, and the select gate.

[0023] Optionally, the steps of forming the stacked structure layer and the gate structure include:

[0024] Form a number of first oxide layers and polysilicon layers stacked in sequence on the substrate;

[0025] Etch the first oxide layer, the polysilicon layer, and the substrate to form a number of trenches extending into the substrate. After etching, a number of first sub-structures and second sub-structures are formed. The first sub-structure includes a first oxide layer and a polysilicon layer extending along the X direction and arranged along the Y direction, and the second sub-structure includes a first oxide layer and a polysilicon layer extending along the Y direction and arranged along the X direction;

[0026] Form the control gate and the select gate to span across the second sub-structure between adjacent first sub-structures;

[0027] Etch the first sub-structure to remove a partial length of the first oxide layer and the polysilicon layer in the first sub-structure along the X direction, so that the remaining polysilicon layer in the first sub-structure constitutes the first strip structure; and,

[0028] Etch and remove a partial length of the remaining first oxide layer in the first sub-structure and the first oxide layer in the second sub-structure, and the remaining second sub-structure serves as the second strip structure.

[0029] Optionally, before forming the control gate and the select gate, it further includes:

[0030] Form an ONO structure layer to span across the second sub-structure between adjacent first sub-structures and located between the second sub-structure and the control gate; and,

[0031] Form a second oxide layer to span across the second sub-structure between adjacent first sub-structures and located between the second sub-structure and the select gate.

[0032] Optionally, before etching and removing the first oxide layer in the remaining first sub-structure, it further includes:

[0033] Sidewalls are formed on the sides of the control gate and the select gate, and the sidewalls cover the sides of the second sub-structure.

[0034] Optionally, after etching away the first oxide layer in the remaining first sub-structure, a doping region is formed in each polysilicon layer of the first strip structure by a plasma doping process.

[0035] In the three-dimensional flash memory device and its manufacturing method provided by the present invention, a stacked structure layer is located on a substrate and includes a plurality of first strip structures and second strip structures. The first strip structures extend in the X direction and are arranged in the Y direction, and the second strip structures extend in the Y direction and are arranged in the X direction. The first strip structures include a plurality of polysilicon layers, and the second strip structures include a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is a first oxide layer. The polysilicon layers in the second strip structures correspond one-to-one to the polysilicon layers in the first strip structures, and the corresponding polysilicon layers are arranged in the same layer. The first oxide layer is located between two adjacent first strip structures, and the length of the first strip structures gradually decreases from bottom to top in a stepped manner; each gate structure is located between two adjacent first strip structures and includes a control gate and a select gate. There is a spacing between the control gate and the select gate, and both span across the second strip structures; a plurality of doping regions are located in each polysilicon layer of the first strip structures; a metal interconnect structure is located on the stacked structure layer and the gate structures and includes a plurality of electrical connectors. The electrical connectors are electrically connected to the corresponding doping regions, control gate, and select gate. In the three-dimensional flash memory device of the present invention, the channel is the stacked structure layer. The extending direction of the stacked structure layer is parallel to the surface of the substrate, the stacked structure layer is perpendicular to the surface of the substrate, the doping regions, control gate, and select gate are all arranged parallel to the surface of the substrate, and the doping regions are used as source regions and drain regions later, which can avoid the vertical stacking of source regions, drain regions, control gates, and select gates, so as to reduce the process integration difficulty and facilitate improving the integration degree of the flash memory device. Brief Description of the Drawings

[0036] Figure 1 is a top view of a three-dimensional flash memory device provided by an embodiment of the present invention;

[0037] Figure 2 is a schematic cross-sectional view along the X1-X2 direction in the top view of a three-dimensional flash memory device provided by an embodiment of the present invention;

[0038] Figure 3 is a flowchart of a manufacturing method of a three-dimensional flash memory device provided by an embodiment of the present invention;

[0039] Figures 4A to 4H is a three-dimensional structure schematic diagram of corresponding steps in the manufacturing method of a three-dimensional flash memory device provided by an embodiment of the present invention, where Figure 4H is a three-dimensional structure schematic diagram of a three-dimensional flash memory device provided by an embodiment of the present invention;

[0040] Among them, the reference numerals are as follows:

[0041] 10 - Substrate; 21 - First oxide layer; 22 - Second oxide layer; 23 - Third oxide layer; 30, 31, 32 - Polysilicon layers; 40 - Trench; 50 - ONO structure layer; 61 - Control gate; 62 - Erase gate; 70 - Sidewall; 81 - Source electrical connector; 82 - Drain electrical connector; 83 - Control gate electrical connector; 84 - Select gate electrical connector; 210 - First sub - structure; 220 - Second sub - structure; 211 - First strip - like structure; 222 - Second strip - like structure. Detailed Description of the Invention

[0042] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0043] Figure 1 It is a top - view diagram of the three - dimensional flash memory device provided in this embodiment. Figure 2 It is a cross - sectional schematic diagram along the X1 - X2 direction in the top - view diagram of the three - dimensional flash memory device provided in this embodiment (this cross - sectional schematic diagram is a sectional view). Figure 4H It is a three - dimensional structure schematic diagram of the three - dimensional flash memory device provided in this embodiment. Please refer to Figure 1 , Figure 2 and Figure 4H , this embodiment provides a three - dimensional flash memory device, including a substrate 10, a stacked structure layer, a plurality of gate structures, a plurality of doped regions, and a metal interconnection structure; wherein the material of the substrate 10 may include one or more of silicon, carbon, germanium, gallium, and arsenic. A plurality of first trenches (not marked in the figure) are formed in the substrate 10, and a third oxide layer 23 is filled in a part of the depth of the first trenches.

[0044] The stacked structure layer is located on the substrate 10, and the stacked structure layer includes a plurality of first strip structures 211 and second strip structures 222. The first strip structures 211 extend in the X direction and are arranged in the Y direction. The second strip structures 222 extend in the Y direction and are arranged in the X direction. The first strip structures 211 include a plurality of polysilicon layers 31. The second strip structures 222 include a plurality of first oxide layers 21 and polysilicon layers 32 stacked in sequence, and the topmost layer of the second strip structures 222 is the first oxide layer 21. The polysilicon layers 32 in the second strip structures 222 correspond to the polysilicon layers 31 in the first strip structures 211 one by one, and the corresponding polysilicon layers are arranged on the same layer. The first oxide layer 21 is located between two adjacent first strip structures 211, and the length of the polysilicon layer 31 in the first strip structures 211 gradually decreases from bottom to top in a stepped manner. In this embodiment, the number of layers of the first oxide layer 21 and the polysilicon layers 31 and 32 stacked in sequence depends on the actual situation.

[0045] Each gate structure is located between two adjacent first strip structures 211, and each gate structure includes a control gate 61 and a select gate 62. There is a spacing between the control gate 61 and the select gate 62, and both span across the second strip structures 222. The control gate 61 and the select gate 62 extend to cover the sidewalls of the remaining depth of the first trench.

[0046] Furthermore, it further includes an ONO structure layer 50 and a second oxide layer 22, both of which span across the second strip structures 222 and extend to cover the sidewalls of the remaining depth of the first trench, so that the ONO structure layer 50 is located between the control gate 61 and the second strip structures 222, and the second oxide layer 22 is located between the select gate 62 and the second strip structures 222. In this embodiment, the ONO structure layer 50 is a stack of an oxide layer, a nitride layer, and an oxide layer. In the three-dimensional flash memory device of this embodiment, the nitride layer is a charge potential well that can store charges. The two oxide layers wrap the nitride layer, and the nitride layer needs to meet a certain thickness to avoid breakdown.

[0047] Further, it further includes sidewalls 70. The sidewalls 70 cover the sides of the control gate 61 and the select gate 62, and the sidewalls also extend to cover the second strip structures 222 where the control gate 61 and the select gate 62 are located (the extension to cover the second strip structures 222 is not shown in Figure 4H ).

[0048] A plurality of doped regions (not labeled in the figure) are located in each polysilicon layer 31 of the first strip structures 211. The doped regions corresponding to the adjacent first strip structures 211 serve as the source region and the drain region respectively, so that the source region and the drain region are arranged at intervals in a plurality of first strip structures 211.

[0049] The metal interconnection structure is located on the stacked structure layer and the gate structure. The metal interconnection structure includes a number of electrical connectors, including a source electrical connector 81, a drain electrical connector 82, a control gate electrical connector 83 and a select gate electrical connector 84. The source electrical connector 81 is electrically connected to the source region, the drain electrical connector 82 is electrically connected to the drain region, the control gate electrical connector 83 is electrically connected to the control gate, and the select gate electrical connector 84 is electrically connected to the select gate. Since the length of the polysilicon layer 31 in the first strip structure 211 gradually decreases from bottom to top in a step-like shape, the source electrical connector 81 and the drain electrical connector 82 can be connected to each polysilicon layer 31 in the corresponding first strip structure 211, respectively, so that the source region or drain region corresponding to each polysilicon layer 31 in the first strip structure 211 can be separately led out.

[0050] In this embodiment, the channel in the three-dimensional flash memory device is a stacked structure layer, the extension direction of the stacked structure layer is parallel to the surface of the substrate, the stacked structure layer is perpendicular to the surface of the substrate, the doped region, the control gate and the select gate are all arranged parallel to the surface of the substrate, which can reduce the difficulty of process integration; and the doped region serves as the source region and the drain region, and the source region or the drain region corresponding to each polysilicon layer in the first strip structure is separately led out through the source electrical connector and the drain electrical connector, which can reduce the difficulty of operation when the three-dimensional flash memory device is erased and written.

[0051] Figure 3 This is a flow chart of the method for preparing a three-dimensional flash memory device provided in this embodiment. Figure 3 In order to form the above-mentioned three-dimensional flash memory device, this embodiment provides a method for preparing a three-dimensional flash memory device, including:

[0052] Step S1: providing a substrate;

[0053] Step S2: forming a stacked structure layer on the substrate, the stacked structure layer comprising a plurality of first strip structures and a second strip structure, forming a plurality of gate structures, each gate structure being located between two adjacent first strip structures;

[0054] Step S3: forming a plurality of doped regions in each polysilicon layer of the first strip structure; and,

[0055] Step S4: forming a metal interconnection structure on the stacked structure layer and the gate structure;

[0056] Among them, the first strip-shaped structure extends along the X direction and is arranged along the Y direction, the second strip-shaped structure extends along the Y direction and is arranged along the X direction, the first strip-shaped structure includes a plurality of polysilicon layers, the second strip-shaped structure includes a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is the first oxide layer. The polysilicon layers in the second strip-shaped structure correspond one-to-one to the polysilicon layers in the first strip-shaped structure, and the corresponding polysilicon layers are arranged on the same layer. The first oxide layer is located between two adjacent first strip-shaped structures, and the length of the first strip-shaped structure gradually decreases from bottom to top in a stepped manner;

[0057] The gate structure includes a control gate and a select gate. There is a spacing between the control gate and the select gate, and both span across the second strip-shaped structure;

[0058] The metal interconnect structure includes a plurality of electrical connectors, and the electrical connectors are electrically connected to the corresponding doped regions, control gates, and select gates.

[0059] Figures 4A to 4H is a flowchart of the manufacturing method of the three-dimensional flash memory device provided in this embodiment. The following will be combined with Figures 4A to 4H to describe in detail the manufacturing method of the three-dimensional flash memory device provided in this embodiment.

[0060] Please refer to Figure 4A , perform step S1: Provide a substrate 10, and the material of the substrate 10 may include one or more of silicon, carbon, germanium, gallium, and arsenic.

[0061] Performing step S2: The steps of forming the stacked structure layer and the gate structure include:

[0062] Please continue to refer to 4A. Form a plurality of first oxide layers 21 and polysilicon layers 30 stacked in sequence on the substrate 10, and the topmost layer after formation is the first oxide layer 21.

[0063] Please refer to Figure 4B , etch the first oxide layer 21, the polysilicon layer 30, and the substrate 10 to form a plurality of trenches 40. The trenches 40 extend into the substrate 10. The trenches 40 include a first trench (not labeled in the figure) located in the substrate 10 and a second trench (not labeled in the figure) located in the first oxide layer 21 and the polysilicon layer 30. The first trench is connected to the second trench; After etching, a plurality of first sub-structures 210 and second sub-structures 220 are formed. Among them, the first sub-structure 210 includes the first oxide layer 21 and the polysilicon layer 30 extending along the X direction and arranged along the Y direction, and the second sub-structure 220 includes the first oxide layer 21 and the polysilicon layer 30 extending along the Y direction and arranged along the X direction. Among them, the X direction and the Y direction may be perpendicular to each other. In Figure 4B In order to facilitate marking the first sub-structure 210 and the second sub-structure 220, brackets are used for marking, and the first sub-structure 210 and the second sub-structure 220 are not completely framed out.

[0064] Furthermore, a third oxide layer 23 is filled in a partial depth of the first trench, and the surface of the third oxide layer 23 is lower than the surface of the substrate 10.

[0065] Please refer to Figure 4C , an ONO structure layer 50 is formed across a second sub-structure 220 between adjacent first sub-structures 210, and the ONO structure layer 50 extends to cover the remaining depth of the first trench, wherein the ONO structure layer 50 is a stack layer composed of an oxide layer, a nitride layer, and an oxide layer. Also, a second oxide layer 22 is formed across the second sub-structure 220 between adjacent first sub-structures 210, and the second oxide layer 22 extends to cover the remaining depth of the first trench, and there is a spacing between the second oxide layer 22 and the ONO structure layer 50.

[0066] Please refer to Figure 4D , a control gate 61 and a select gate 62 are formed across the second sub-structure 220 between adjacent first sub-structures 210, and the materials of both the control gate 61 and the select gate 62 are polysilicon; specifically, the control gate 61 covers the ONO structure layer 50, that is, the ONO structure layer 50 is located between the second sub-structure 220 and the control gate 61; the select gate covers the second oxide layer 22, that is, the second oxide layer 22 is located between the second sub-structure 220 and the select gate 62; the control gate 61 and the select gate 62 on the second sub-structure 220 between adjacent first sub-structures 210 form a gate structure, that is, each gate structure is located on the second sub-structure 220 between adjacent first sub-structures 210.

[0067] Please refer to Figure 4E , sidewalls 70 are formed on the sides of the control gate 61 and the select gate 62, and the sidewalls 70 also extend to cover the sides of the second sub-structure 220 where the control gate 61 and the select gate 62 are located (the extension to cover the sides of the second sub-structure 220 is not shown in the figure).

[0068] Please refer to Figure 4F , the first sub-structure 210 is etched step by step to remove a partial length of the first oxide layer 21 and the polysilicon layer 30 in the first sub-structure 210 along the X direction, so that the remaining polysilicon layer 31 in the first sub-structure 210 forms a first strip structure 211, and the length of the polysilicon layer 31 in the first strip structure 211 gradually decreases from bottom to top in a stepped manner, so as to facilitate separately leading out each polysilicon layer 31 in the first strip structure 211 subsequently.

[0069] Please refer to Figure 4G, etch away the remaining first oxide layer 21 in the first sub-structure 210. The remaining second sub-structure 220 serves as the second strip structure 222. The second strip structure 222 includes a plurality of first oxide layers 21 and polysilicon layers 32 stacked in sequence, and the topmost layer of the second strip structure 222 is the first oxide layer 21. The first oxide layer 21 of the second strip structure 222 is located between two adjacent first strip structures 211.

[0070] Please continue to refer to Figure 4G , perform step S3: form doping regions in each polysilicon layer 31 of the first strip structure 211 by using a plasma doping process. The doping regions corresponding to adjacent first strip structures 211 serve as the source region and the drain region respectively, so that the source region and the drain region are arranged at intervals in a plurality of first strip structures 211. For example, if the doping region in each polysilicon layer 31 of a first strip structure 211 serves as the source region, then the doping region in each polysilicon layer 31 of the adjacent first strip structure 211 serves as the drain region.

[0071] Please refer to Figure 4H , perform step S4: form an interlayer dielectric layer (not shown in the figure) on the gate structure, the first strip structure 211, and the second strip structure 222, form a plurality of plugs in the interlayer dielectric layer, and form a plurality of metal lines on the interlayer dielectric layer. The plugs are connected to the corresponding metal lines to form electrical connectors. The electrical connectors are electrically connected to the corresponding source regions, drain regions, control gates, and select gates. Specifically, a plurality of source electrode connectors 81, drain electrode connectors 82, control gate connectors 83, and select gate connectors 84 are formed. The source electrode connector 81 is electrically connected to the source region, the drain electrode connector 82 is electrically connected to the drain region, the control gate connector 83 is electrically connected to the control gate, and the select gate connector 84 is electrically connected to the select gate. Since the length of the polysilicon layer 31 in the first strip structure 211 gradually decreases from bottom to top in a stepped manner, the source electrode connector 81 and the drain electrode connector 82 can be respectively connected to each polysilicon layer 31 in the corresponding first strip structure 211, so as to realize separately leading out the source region or the drain region corresponding to each polysilicon layer 31 in the first strip structure 211 through the source electrode connector 81 and the drain electrode connector 82, and the operation difficulty can be reduced during the erase and write operations of the 3D flash memory device.

[0072] In summary, in the three-dimensional flash memory device and its manufacturing method provided by the present invention, the stacked structure layer is located on the substrate and includes a plurality of first strip structures and second strip structures. The first strip structures extend along the X direction and are arranged along the Y direction. The second strip structures extend along the Y direction and are arranged along the X direction. The first strip structures include a plurality of polysilicon layers. The second strip structures include a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is a first oxide layer. The polysilicon layers in the second strip structures correspond one by one to the polysilicon layers in the first strip structures, and the corresponding polysilicon layers are arranged in the same layer. The first oxide layer is located between two adjacent first strip structures, and the length of the first strip structures gradually decreases from bottom to top in a stepped manner; each gate structure is located between two adjacent first strip structures and includes a control gate and a select gate. There is a spacing between the control gate and the select gate, and both span across the second strip structures; a plurality of doping regions are located in each polysilicon layer of the first strip structures; the metal interconnect structure is located on the stacked structure layer and the gate structures and includes a plurality of electrical connectors, and the electrical connectors are electrically connected to the corresponding doping regions, control gates, and select gates. In the three-dimensional flash memory device of the present invention, the channel is the stacked structure layer. The extending direction of the stacked structure layer is parallel to the surface of the substrate, and the stacked structure layer is perpendicular to the surface of the substrate. The doping regions, control gates, and select gates are all arranged parallel to the surface of the substrate. The doping regions are used as source regions and drain regions later, which can avoid the vertical stacking of the source regions, drain regions, control gates, and select gates, so as to reduce the process integration difficulty and facilitate improving the integration degree of the flash memory device.

[0073] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content within the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A three-dimensional flash memory device, characterized in that, Comprising: A substrate; A stacked structure layer located on the substrate and including a plurality of first strip-shaped structures and second strip-shaped structures. The first strip-shaped structures extend along the X direction and are arranged along the Y direction. The second strip-shaped structures extend along the Y direction and are arranged along the X direction. The first strip-shaped structures include a plurality of polysilicon layers. The second strip-shaped structures include a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is the first oxide layer. The polysilicon layers in the second strip-shaped structures correspond one-to-one to the polysilicon layers in the first strip-shaped structures, and the corresponding polysilicon layers are arranged in the same layer. The first oxide layer is located between two adjacent first strip-shaped structures, and the lengths of the polysilicon layers in the first strip-shaped structures gradually decrease from bottom to top in a stepped manner; A plurality of gate structures, each gate structure being located between two adjacent first strip-shaped structures and including a control gate and a select gate. There is a spacing between the control gate and the select gate, and both span across the second strip-shaped structures; A plurality of doped regions located in each polysilicon layer of the first strip-shaped structures. The doped regions corresponding to adjacent first strip-shaped structures serve as source regions and drain regions respectively, so that the source regions and drain regions are arranged at intervals in a plurality of first strip-shaped structures; A metal interconnect structure located on the stacked structure layer and the gate structures, which includes a plurality of electrical connectors. The electrical connectors are electrically connected to the corresponding doped regions, control gates, and select gates.

2. The three-dimensional flash memory device according to claim 1, wherein It further includes an ONO structure layer that spans across the second strip-shaped structures and is located between the control gate and the second strip-shaped structures.

3. The three-dimensional flash memory device according to claim 1, characterized in that, It further includes a second oxide layer that spans across the second strip-shaped structures and is located between the select gate and the second strip-shaped structures.

4. The three-dimensional flash memory device according to claim 1, wherein It further includes sidewalls covering the sides of the gate structures.

5. The three-dimensional flash memory device according to claim 1, wherein A plurality of first trenches are formed in the substrate, and a third oxide layer is filled in a part of the depth of the first trenches. The gate structures extend to cover the sidewalls of the remaining depth of the first trenches.

6. A method for manufacturing a three-dimensional flash memory device, characterized in that, Comprising: Providing a substrate; Forming a stacked structure layer on the substrate, the stacked structure layer including a plurality of first strip-shaped structures and second strip-shaped structures, and forming a plurality of gate structures, each gate structure being located between two adjacent first strip-shaped structures; Forming a plurality of doped regions in each polysilicon layer of the first strip-shaped structures; and Forming a metal interconnect structure on the stacked structure layer and the gate structures; Wherein, the first strip-shaped structures extend along the X direction and are arranged along the Y direction. The second strip-shaped structures extend along the Y direction and are arranged along the X direction. The first strip-shaped structures include a plurality of polysilicon layers. The second strip-shaped structures include a plurality of first oxide layers and polysilicon layers stacked in sequence, and the topmost layer is the first oxide layer. The polysilicon layers in the second strip-shaped structures correspond one-to-one to the polysilicon layers in the first strip-shaped structures, and the corresponding polysilicon layers are arranged in the same layer. The first oxide layer is located between two adjacent first strip-shaped structures, and the lengths of the polysilicon layers in the first strip-shaped structures gradually decrease from bottom to top in a stepped manner; The gate structure includes a control gate and a select gate, with a spacing therebetween and both spanning across the second strip structure; The doped regions corresponding to adjacent first strip structures serve as a source region and a drain region respectively, such that the source region and the drain region are arranged at intervals among a plurality of first strip structures, and the source region and the drain region are located in each polysilicon layer of the corresponding first strip structure; The metal interconnect structure includes a plurality of electrical connectors, and the electrical connectors are electrically connected to the corresponding doped regions, the control gate, and the select gate.

7. The method for manufacturing a three-dimensional flash memory device according to claim 6, wherein The steps of forming the stacked structure layer and the gate structure include: Forming a plurality of sequentially stacked first oxide layers and polysilicon layers on the substrate; Etching the first oxide layer, the polysilicon layer, and the substrate to form a plurality of trenches extending into the substrate, and after etching, forming a plurality of first sub-structures and second sub-structures. The first sub-structure includes a first oxide layer and a polysilicon layer extending along the X direction and arranged along the Y direction, and the second sub-structure includes a first oxide layer and a polysilicon layer extending along the Y direction and arranged along the X direction; Forming the control gate and the select gate to span across the second sub-structure between adjacent first sub-structures; Etching the first sub-structure to remove a partial length of the first oxide layer and the polysilicon layer in the first sub-structure along the X direction, such that the remaining polysilicon layer in the first sub-structure constitutes the first strip structure; and, Etching and removing a partial length of the remaining first oxide layer in the first sub-structure and the first oxide layer in the second sub-structure, and the remaining second sub-structure serves as the second strip structure.

8. The manufacturing method of the three-dimensional flash memory device according to claim 7, characterized in that, Before forming the control gate and the select gate, it further includes: Forming an ONO structure layer to span across the second sub-structure between adjacent first sub-structures and located between the second sub-structure and the control gate; and, Forming a second oxide layer to span across the second sub-structure between adjacent first sub-structures and located between the second sub-structure and the select gate.

9. The method for manufacturing a three-dimensional flash memory device according to claim 7, wherein, Before etching and removing the remaining first oxide layer in the first sub-structure, it further includes: Forming sidewalls on the sides of the control gate and the select gate, and the sidewalls cover the sides of the second sub-structure.

10. The method for manufacturing a three-dimensional flash memory device according to claim 7, wherein, After etching and removing the remaining first oxide layer in the first sub-structure, a plasma doping process is used to form the doped regions in each polysilicon layer of the first strip structure.

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