Semiconductor device and method

Abstract

A manufacturing process and device are provided, wherein a first opening is formed in a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed using free radical etching, wherein the free radical etching utilizes neutral ions. Thus, the pushing force of the substrate is reduced. Embodiments of the present invention also relate to a semiconductor device and a method for manufacturing the same.

Description

[0001] This application is a divisional application of the patent application entitled “Semiconductor Device and Method” filed on December 5, 2017 and with patent application number 201711270350.X. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices and methods. Background Art

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements on the various material layers.

[0004] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a gate stack above a semiconductor substrate; forming a first opening in the semiconductor substrate using a first etching process; and reshaping the first opening into a second opening using a second etching process different from the first etching process, wherein the second etching process is a radical etching process.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a dummy gate stack above a semiconductor fin of a substrate, the dummy gate stack comprising a first spacer structure; removing a portion of the semiconductor fin to form a first opening, wherein the first opening is formed using an anisotropic etching process; and modifying the first opening to a second opening, wherein the modification comprises: forming a plasma from a precursor; and directing free radicals from the plasma to the semiconductor fin while filtering charged particles from the plasma to prevent the charged particles from reaching the semiconductor fin.

[0007] Another embodiment of the present invention provides a semiconductor device, comprising: a first semiconductor fin located above a substrate; a gate stack located above the first semiconductor fin; a first spacer located on the sidewall of the gate stack; and a first opening located within the first semiconductor fin and undercutting the first spacer, wherein a surface proximity distance of the first opening and a tip proximity distance have a difference of less than 3 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A to Figure 1B A finFET device is shown in accordance with some embodiments.

[0010] Figure 2 The formation of a first opening in a fin is shown in accordance with some embodiments.

[0011] Figures 3A to 3C The formation of a second opening in the fin is shown in accordance with some embodiments.

[0012] Figure 4 Depth loading of the second opening is shown according to some embodiments.

[0013] Figure 5 A replacement gate process is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] Now refer to Figure 1A and Figure 1B (in, Figure 1B Shown Figure 1Aalong the line BB'), Figure 1A A perspective view of a semiconductor device 100, such as a finFET device (e.g., a PMOSFET or NMOSFET), is shown. In an embodiment, semiconductor device 100 includes a substrate 101 having a trench 103 formed therein. Substrate 101 may be a silicon substrate, although other substrates such as semiconductor-on-insulator (SOI), strained SOI, and silicon-germanium-on-insulator (SiGe) may be used. Substrate 101 may be a p-type semiconductor, but in other embodiments, substrate 101 may be an n-type semiconductor.

[0017] As an initial step in the final formation of the first isolation region 105, the first trench 103 may be formed. A masking layer (not in the Figure 1A The first trench 103 is formed by a masking layer (shown separately in FIG) and a suitable etching process. For example, the masking layer can be a hard mask comprising silicon nitride formed by, for example, chemical vapor deposition (CVD), but other materials such as oxides, oxynitrides, silicon carbide, combinations of these, and other processes such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even silicon oxide formation and subsequent nitridation can be utilized. Once formed, the masking layer can be patterned by a suitable photolithography process to expose those portions of the substrate 101 to be removed to form the first trench 103.

[0018] However, one of ordinary skill in the art will appreciate that the processes and materials for forming the masking layer described above are not the only methods that can be used to protect portions of the substrate 101 while exposing other portions of the substrate 101 for forming the first trench 103. Any suitable process, such as patterning and developing a photoresist, can be utilized to expose the portion of the substrate 101 to be removed to form the first trench 103. All such methods are intended to be included within the scope of the present embodiment.

[0019] Once the masking layer has been formed and patterned, a first trench 103 is formed in the substrate 101. The exposed substrate 101 may be removed by a suitable process such as reactive ion etching (RIE) to form the first trench 103 in the substrate 101, but any suitable process may be used. In an embodiment, the first trench 103 may be formed to have a depth of less than about 100 nm from the top surface of the substrate 101. (such as about ) depth.

[0020] However, those skilled in the art will appreciate that the process for forming the first trench 103 described above is one potential process and is not meant to be the only embodiment. Instead, any suitable process for forming the first trench 103 may be utilized, and any suitable process including any number of masking and removal steps may be used.

[0021] In addition to forming the first trench 103, the masking and etching process additionally forms fins 107 from those portions of the substrate 101 that remain unremoved. For convenience, the fins 107 have been shown as being separated from the substrate 101 by dashed lines, but a physical marking of separation may or may not exist. As discussed below, these fins 107 can be used to form the channel region of a multi-gate FinFET transistor. Although Figure 1A Only three fins 107 formed from substrate 101 are shown, but any number of fins 107 may be utilized.

[0022] The fins 107 can be formed such that they have a width between about 5 nm and about 80 nm (such as about 30 nm) at the surface of the substrate 101. In addition, the fins 107 can be spaced apart from each other by a distance between about 10 nm and about 100 nm (such as about 50 nm). By spacing the fins 107 in this manner, the fins 107 can each form a separate channel region while still being close enough to share a common gate (discussed further below).

[0023] Once the first trench 103 and the fin 107 have been formed, the first trench 103 may be filled with a dielectric material and the dielectric material may be recessed into the first trench 103 to form the first isolation region 105. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, etc. After optional cleaning and lining of the first trench 103, the dielectric material may be formed using a chemical vapor deposition (CVD) method (e.g., a HARP process), a high-density plasma CVD method, or other suitable formation methods known in the art.

[0024] The first trench 103 may be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material and then removing the excess material outside of the first trench 103 and the fin 107 by a suitable process such as chemical mechanical polishing (CMP), etching, combinations of these, etc. In an embodiment, the removal process also removes any dielectric material located above the fin 107, such that the removal of the dielectric material exposes the surface of the fin 107 for further processing steps.

[0025] Once the first trench 103 has been filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fin 107. The recessing may be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface of the fin 107. The dielectric material may be recessed using a wet etch by immersing the top surface of the fin 107 in an etchant such as HF, although other etchants such as H2 may be used, as well as other methods such as reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning. The dielectric material may be recessed a distance from the surface of the fin 107 to form a dielectric layer between about 100 nm and about 100 nm. peace treaty Between (such as about ) of the fin height. In addition, the recess may also remove any remaining dielectric material located above the fin 107 to ensure that the fin 107 is exposed for further processing.

[0026] However, one skilled in the art will appreciate that the steps described above may be only a portion of the overall process flow for filling and recessing the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap filling step, a combination of these, etc. may also be used to form the first trench 103 and fill the first trench 103 with a dielectric material. All potential process steps are fully intended to be included within the scope of this embodiment.

[0027] After the first isolation region 105 has been formed, a dummy gate dielectric 109 and a dummy gate electrode 111 located above the dummy gate dielectric 109 may be formed over each of the fins 107. In an embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known and used in the art for forming a gate dielectric. Depending on the technique used to form the gate dielectric, the thickness of the dummy gate dielectric 109 located on top of the fin 107 may be different from the thickness of the dummy gate dielectric located on the sidewalls of the fin 107.

[0028] The dummy gate dielectric 109 may include a material such as silicon dioxide or silicon oxynitride having a thickness ranging from about 3 angstroms to about 100 angstroms (such as about 10 angstroms). The dummy gate dielectric 109 may be formed of a high dielectric constant (high-k) material (e.g., having a relative dielectric constant greater than about 5) having an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms (such as 10 angstroms or less), such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium dioxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or a combination thereof. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0029] The dummy gate electrode 111 may include a conductive material and may be selected from the group consisting of W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known and used in the art for depositing conductive materials. The thickness of the dummy gate electrode 111 may be about 1000 Å. to about The top surface of the dummy gate electrode 111 may have a non-flat top surface and may be flattened before patterning or gate etching of the dummy gate electrode 111. At this time, ions may or may not be introduced into the dummy gate electrode 111. Ions may be introduced, for example, by ion implantation technology.

[0030] Once formed, the dummy gate dielectric 109 and the dummy gate electrode 111 may be patterned to form a series of gate stacks 115 over the fin 107. The gate stacks 115 define a plurality of channel regions on each side of the fin 107 beneath the dummy gate dielectric 109. The gate stacks 115 may be formed by depositing and patterning a first hard mask 113 and a second hard mask 117 over the dummy gate dielectric 109 and the dummy gate electrode 111. In an embodiment, the first hard mask 113 may be a material such as silicon nitride, although any suitable masking material such as silicon oxide, silicon oxynitride, SiCON, SiC, SiOC may be utilized. The first hard mask 113 may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition and may be formed to a thickness between about peace treaty Between (such as about However, any suitable process or thickness may be utilized.

[0031] A second hard mask 117 may be formed over the first hard mask 113. In an embodiment, the second hard mask 117 may be a different material than the first hard mask 113, such as silicon oxide, but any other suitable material such as silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride may also be used. Furthermore, the second hard mask 117 may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition, and may be formed to a thickness between about 100 nm and about 100 nm. peace treaty Between (such as about However, any suitable process or thickness may be utilized.

[0032] Once the first hard mask 113 and the second hard mask 117 have been formed, the second hard mask 117 can be patterned using, for example, one or more photolithographic masking and etching processes. Furthermore, once the second hard mask 117 has been patterned, the pattern of the second hard mask 117 can be transferred to the first hard mask 113, the dummy gate electrode 111, and the dummy gate dielectric 109 using one or more etching processes that utilize the second hard mask 117 as a masking material. However, any suitable process can be utilized.

[0033] After the gate stack 115 has been formed, the sidewalls of the gate stack 115 may be protected by depositing a material to cover the sidewalls of the gate stack 115. In an embodiment, the sidewalls of the gate stack 115 may be protected by depositing a first spacer material 119, a second spacer material 121, and a third spacer material 123. In an embodiment, the first spacer material 119 may be a material such as silicon nitride formed using a conformal method such as atomic layer deposition, but any suitable method such as chemical vapor deposition or physical vapor deposition may be used. The first spacer material 119 may be deposited to have a thickness between about peace treaty The first spacer material 119 may be patterned using, for example, one or more etching processes, once deposited, to a thickness of between 100 nm and 200 nm, such as about 2 nm, but any suitable method may be used.

[0034] The second spacer material 121 is deposited over the first spacer material 119 and can be a different material than the first spacer material 119, such as SiOCN, but any other suitable material such as SiCN or SiOC can alternatively be utilized. The second spacer material 121 can be formed using a conformal deposition process such as atomic layer deposition or other deposition processes such as chemical vapor deposition or physical vapor deposition to form a blanket layer of the material of the second spacer material 121.

[0035] Once the second spacer material 121 has been deposited, it can be patterned. In an embodiment, after deposition of the second spacer material 121, the second spacer material 121 can be patterned using, for example, one or more etches to remove portions of the second spacer material 121 from horizontal surfaces of the structure.

[0036] Once the first spacer material 119 and the second spacer material 121 have been patterned, a third spacer material 123 may be formed. In an embodiment, the third spacer material 123 may be formed of a material such as silicon nitride, although any other suitable material may be utilized. In an embodiment, the third spacer material 123 may be blanket deposited using a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and may then be patterned by one or more etches to remove the third spacer material 123 from the horizontal surfaces of the structure.

[0037] Figure 2 The first step in the process of removing portions of the fin 107 and forming a first opening 201 within the fin 107 is shown. In an embodiment, the removal process may begin by placing a mask 203 to cover those portions of the fin 107 (and the gate stack 115, if desired) that are not desired to be removed. In an embodiment, the mask 203 may be a photosensitive material, such as photoresist, that has been placed, exposed, and developed to form the mask 203. However, any suitable mask material may be utilized.

[0038] Once the mask 203 is in place, a first etching process ( Figure 2 107 ) to form a first opening 201 within the exposed portion of the fin 107. In an embodiment, the first etching process 205 may be an anisotropic etching process, such as reactive ion etching (RIE) using an etchant suitable for etching the material of the fin 107. Thus, while the particular etchant selected depends at least in part on the material of the fin 107, in embodiments where the fin 107 comprises silicon, the etchant may be arsenic, phosphorus, or boron in combination with any other suitable etchant or diluent as may be desired. However, any suitable etchant may be utilized.

[0039] In certain embodiments, the first etching process 205 may be performed by receiving an etchant and forming a plasma before the material of the fin 107 contacts the etchant. Figure 2 The etchant is ignited into a plasma (shown separately in FIG), but any suitable method of forming a plasma (including a remote plasma system) may be utilized. Furthermore, once the plasma is ignited, the first etching process 205 may be performed at a power between about 150 W and about 550 W (such as about 350 W) and a bias between about 60 V and about 180 V (such as about 130 V). The first etching process 205 may be continued at a temperature between about 30° C. and about 70° C. (such as about 60° C.) and a pressure between about 3 mTorr and about 100 mTorr (such as about 5 mTorr). However, any suitable process conditions may be utilized.

[0040] By using the first etching process 205, a first opening 201 is formed in the fin 107. Specifically, by using an anisotropic etching process for the first etching process 205, the first opening 201 will be formed to have a "U" shape. For example, the first opening 201 will have a thickness between about peace treaty Between (such as about ) and will also have a first height H1 between about peace treaty Between (such as about ) has a first width W1. However, any suitable dimensions may be utilized.

[0041] Figure 3A The removal of the mask 203 and the ex-situ second etching process (in FIG. 1 ) for modifying the shape of the first opening 201 into the second opening 301 (wherein, for comparison, the shape of the first opening 201 is shown using a dotted line labeled 201) are shown. Figure 3A (indicated by the arrow labeled 303 in the figure). In embodiments where mask 203 is a photoresist, mask 203 can be removed by an ashing process, thereby raising the temperature of the photoresist to a point where the photoresist undergoes thermal decomposition. Thereafter, mask 203 can be easily removed. However, any suitable method can be used to remove mask 203.

[0042] In an embodiment, the second etching process 303 is an isotropic etching process using a second etching precursor 309 (not shown). Figure 3A However, the following reference Figure 3B 107 ) instead of plasma to etch the material of the fin 107 (e.g., silicon) and form the second opening 301 by reshaping the first opening 201. In an embodiment, the second etch precursor 309 can be selected to be selective to the material of the fin 107 without over-reacting with the material of other exposed structures. Thus, while the precise material of the second etch precursor 309 may depend at least in part on the material of the fin 107, in an embodiment where the fin 107 is silicon, the second etch precursor 309 can be a nitrogen-containing gas, such as ammonia (NH3). However, any other suitable precursor, such as NF3 or H2, can be utilized.

[0043] Figure 3BThe fin 107 (located on the substrate 101) is shown placed under the selection modulation device 307 within the etching chamber 305 to start the second etching process 303. In an embodiment, the selection modulation device 307 can be a charged grid that acts as a barrier to the movement of charged ions from the plasma while allowing uncharged plasma components (e.g., free radicals) to pass through the selection modulation device 307. In an embodiment, the selection modulation device 307 can prevent charged plasma ions (e.g., positively charged ions or negatively charged ions) from passing through by repelling charged plasma ions or by attracting charged plasma ions. However, any suitable device that can separate free radicals from the plasma can be utilized.

[0044] Once the substrate 101 with the fins 107 has been placed in the chamber, the second etching process 303 can be started by introducing a second etching precursor 309 (e.g., NH 3) into the plasma region 310 of the etching chamber 305. In an embodiment, the second etching precursor 309 can be introduced at a flow rate between about 10 sccm and about 10,000 sccm, such as about 500 sccm. However, any suitable flow rate of the second etching precursor 309 can be utilized.

[0045] Once the second etch precursor 309 has been introduced into the plasma region 310 of the etch chamber 305, power is applied and the second etch precursor 309 is excited to form a plasma 311 comprising positive ions 311 disposed within the plasma region 310. P 、Negative ions 311 N and free radical ingredients 311 R In an embodiment, the plasma 311 may be generated within the etch chamber 305 using radio frequency energy having a power between about 10 watts and about 2500 watts, although any suitable process conditions and methods may be used to ignite the plasma.

[0046] In addition, although the above process is described as being introduced into the etching chamber 305 and then ignited, this is intended to illustrate the embodiment and is not intended to limit the embodiment. Instead, any suitable method of providing plasma may be utilized, such as using a remote plasma system. All such methods are intended to be included within the scope of the embodiment.

[0047] Once the plasma 311 has been generated, the modulation device 307 is selected to allow the radical components 311 to R The positive ions 311 are prevented from passing through the selective modulation device 307 to the wafer processing area 313 of the etching chamber 305 where the substrate 101 with the fin 107 is located. P and negative ions 311 NThe wafer is moved into the wafer processing area 313 of the etching chamber 305. In practice, the modulation device 307 is selected to filter the positive ions 311 from the plasma 311. P and negative ions 311 N , thereby allowing only the radical component 311 to be used in the second etching process 303 R .

[0048] In an embodiment, the second etching process 303 may be performed at a pressure between about 1 Torr and about 20 Torr (such as about 2 Torr) and at a temperature between about 10° C. and about 100° C. (such as about 40° C.). In addition, the second etching process 303 may be performed for a time between about 5 seconds and about 100 seconds (such as about 10 seconds). However, any suitable process conditions may be utilized.

[0049] By performing the second etching process 303 of free radical etching instead of plasma etching, only positive ions 311 are used. P Or negative ion 311 N The neutral ions with a smaller charge reshape the first opening 201 into the second opening 301. Therefore, the first opening 202 is less rounded during the second etching process 303 because the surface near the fin 107 is pushed outward from the "U"-shaped first opening 201. In addition, due to the less rounded shape, less material of the fin 107 (e.g., silicon) is converted into polymer byproducts, which can interfere with other processes if not removed.

[0050] Figure 3C To help illustrate this benefit, the dashed box labeled 401 is shown. Figure 3A 1. A close-up view of the structure of FIG. 1. In this embodiment, the pushing of the material of the fin 107 (e.g., the pushing of silicon) will undercut the third spacer material 123 and form an overhang (the distance between the tip of the fin 107 and the outer edge of the third sidewall spacer material 123). While previous etching processes (such as plasma etching) will form an overhang of no more than 1 nm, the use of the second etching process 303 as described herein can form an overhang having a first distance D1 between about 1 nm and about 4 nm while minimizing other undesirable side effects.

[0051] In addition, referring back to Figure 3A, the second etching process 303 described herein forms less rounded shapes than when using plasma etching. Specifically, if the reference line is aligned with the outer surface of the gate stack 115 (e.g., aligned with the side of the dummy gate electrode 111 and / or the dummy gate dielectric 109), a first distance can be measured along the top surface of the material of the fin 107 from the reference line to the material of the fin 107 adjacent to the second opening 301 to obtain the tip proximity distance TP1. In a specific embodiment, the surface proximity distance SP1 can be between about peace treaty Between, such as However, any suitable distance may be obtained.

[0052] Furthermore, a second distance can be measured from a reference line to the material surrounding the second opening 301 at a mid-height of the fin 107 to obtain a surface proximity distance SP1. In an embodiment, the tip proximity distance TP1 can be between about 1 nm and about 4 nm. However, any suitable distance can be obtained.

[0053] Given the two distances of surface proximity distance SP1 and tip proximity distance TP1, a measure of the primary roundness of second opening 301 can be determined by the difference between these two distances. For example, in an embodiment, the difference between surface proximity distance SP1 and tip proximity distance TP1 can be less than about 3 nm. This is an improvement over plasma-based processes, in which the difference between surface proximity distance SP1 and tip proximity distance TP1 is greater than 3 nm.

[0054] In addition, the use of the second etching process 303 described herein allows for greater control over the channel length within the fin 107. For example, the surface channel length within the fin 107 (as measured from a first surface tip to a second surface tip located on opposite sides of the gate stack 115) can be shortened and have a distance between about 30 nm and about 40 nm, which results in improved device performance. Furthermore, the channel length at the tip (e.g., measured at half the height of the fin 107) can be between about 20 nm and about 40 nm. However, any suitable distance can be utilized.

[0055] Figure 4 Another benefit of using the second etching process 303 as described herein is shown. Specifically, Figure 4A plurality of fins 107 are shown located in a first region 401 and a second region 403 of a substrate 101 (for convenience, shown as a single fin 107 extending between the two regions). In an embodiment, the first region 401 of the substrate 101 is a region having densely packed gate stacks 115. For example, in the first region 401 of the substrate 101 having the gate stacks 115 (for convenience, the first spacer material 119, the second spacer material 121, and the third spacer material 123 are shown here as a single spacer structure 405), the gate stacks 115 having the spacer structure 405 are separated by a second distance D2 that is less than about 100 nm (such as between about 20 nm and about 50 nm). However, any suitable distance may be utilized.

[0056] Furthermore, the second region 403 can be a less dense region than the first region 401. For example, within the second region 403, the gate stacks 115 with their corresponding spacer structures 405 can be separated by a third distance D3 that is greater than the second distance D2 (e.g., less than 100 nm). In a particular embodiment, the third distance D3 is between approximately 100 nm and approximately 400 nm. However, any suitable distance can be utilized.

[0057] Unfortunately, the difference in distance between the structures in the first region 401 and the structures in the second region 403 will also affect the first etching process 205 and the second etching process 303, causing the openings formed between the dense structures in the first region 401 to be shallower than the openings formed between the less dense structures in the second region 403. This difference in the depth of the openings is called the depth loading of the structure, and a larger depth loading may affect the improved saturation current uniformity (IDU / interactivity) of the entire structure between different modes such as thermal conductivity detectors (TCDs), ring oscillators (ROs), and input / output regions (IOs).

[0058] However, using the second etch process 303 as described herein, the depth loading can be adjusted to minimize the effects of the depth loading. In a specific embodiment where the gate stacks 115 and their corresponding spacer structures 405 in the first region 401 are separated by between about 20 nm and about 50 nm, and the gate stacks 115 and their corresponding spacer structures 405 in the second region 403 are separated by between about 100 nm and about 400 nm, the use of the second etch process 303 allows the second opening 301 in the first region 401 to extend to a fourth distance D4 between about 30 nm and about 70 nm (such as about 55 nm) within the fin 107. Furthermore, the second opening 301 in the second region 403 can extend to a fifth distance D5 between about 30 nm and about 70 nm (such as about 50 nm) within the fin 107. However, any other suitable distances can be utilized.

[0059] Given that the second opening 301 in the first region 401 extends to a fourth distance D4 within the fin 107 and the second opening 301 in the second region 403 extends to a fifth distance D5 within the fin 107, the depth load between the second region 403 and the first region 401 is the difference between the fifth distance D5 and the fourth distance D4 (depth load = D5 - D4). In some embodiments, the use of the second etch process 303 allows for control of the depth load such that the depth load remains between approximately -3 nm and approximately 3 nm. This is much better than plasma-based etching, which achieves a depth load greater than 5 nm (such as 10 nm), and allows for improved depth load control, which can improve wafer acceptance test results and device performance (e.g., benefiting on-current) for both NMOSFETs and PMOSFETs.

[0060] Figure 5 It is shown that once the second opening 301 has been formed within the fin 107, source / drain regions 501 can be grown to fill and overfill the second opening 301. In an embodiment, to form the source / drain regions 501, a hard mask (not separately shown) is placed and patterned to cover the dummy gate electrode 111 to prevent the growth of the source / drain regions 501, and the source / drain regions 501 can be regrown within the second opening 301. In an embodiment, the source / drain regions 501 can be regrown, and in some embodiments, the source / drain regions 501 can be regrown to form a stressor that applies stress to the channel region of the fin 107 located below the gate stack 115. In embodiments where the fin 107 comprises silicon and the FinFET is a p-type device, the source / drain regions 501 can be regrown using a material such as silicon or a material such as silicon germanium (having a different lattice constant than the channel region) through a selective epitaxial process. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, etc., and may last between about 5 minutes and about 120 minutes, such as about 30 minutes. In an embodiment, the source / drain regions 501 may be formed to have a height between about 20 nm and about 100 nm, such as about 50 nm, above the first isolation region 105. However, any suitable height may be utilized.

[0061] Once the source / drain regions 501 are formed, the dopants in the fins 107 can be supplemented by implanting appropriate dopants into the source / drain regions 501. For example, p-type dopants such as boron, gallium, indium, etc. can be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, etc. can be implanted to form an NMOS device. These dopants can be implanted using the gate stack 115 as a mask. It should be noted that one of ordinary skill in the art will appreciate that many other processes, steps, etc. can be used to implant dopants. For example, one of ordinary skill in the art will appreciate that multiple implants can be performed using various combinations of spacers and liners to form source / drain regions with specific shapes or characteristics suitable for specific purposes. Dopants can be implanted using any of these processes, and the above description is not meant to limit the present embodiment to the steps presented above.

[0062] Furthermore, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain regions 501 is removed at this time. In an embodiment, the hard mask can be removed using, for example, a wet or dry etch process that is selective to the material of the hard mask. However, any suitable removal process can be utilized.

[0063] Figure 5 Also shown is an interlayer dielectric (ILD) layer 503 (in the FIGURE 5B) located above the gate stack 115 and the source / drain regions 501. Figure 5 The ILD layer 503 may be formed using a process such as PECVD, but other processes such as LPCVD may alternatively be used. The ILD layer 503 may be formed to a thickness between about 100 nm and about 100 nm. peace treaty Once formed, the ILD layer 503 may be planarized using a planarization process such as a chemical mechanical polishing process, although any suitable process may be utilized.

[0064] After the formation of the ILD layer 503, the material of the dummy gate electrode 111 and the dummy gate dielectric 109 may be removed and replaced to form a replacement gate stack 505. In an embodiment, the dummy gate electrode 111 may be removed using, for example, a wet or dry etching process utilizing an etchant that is selective to the material of the dummy gate electrode 111. However, any suitable removal process may be utilized.

[0065] Once the dummy gate electrode 111 has been removed, the remaining opening can be refilled to form a replacement gate stack 505. In a particular embodiment, the replacement gate stack 505 includes a first dielectric material 507, a first metal material 509, a second metal material 511, and a third metal material 513. In an embodiment, the first dielectric material 507 is a high-k material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc., deposited by a process such as atomic layer deposition, chemical vapor deposition, etc. The first dielectric material 507 can be deposited to a thickness between about peace treaty Thicknesses between, but any suitable material and thickness may be utilized.

[0066] The first metallic material 509 may be formed adjacent to the first dielectric material 507 and may be formed of a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. The first metallic material 509 may be deposited to a depth between about 100 nm and about 100 nm using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. peace treaty A thickness between , but any suitable deposition process or thickness may be used.

[0067] The second metal material 511 can be formed adjacent to the first metal material 509 and, in certain embodiments, can be different from or similar to the first metal material 509. For example, the second metal material 511 can be formed of a metal material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. Furthermore, the second metal material 511 can be deposited to a depth between about 100 nm and about 100 nm using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. peace treaty A thickness between , but any suitable deposition process or thickness may be used.

[0068] The third metal material 513 fills the remaining portion of the opening left by the removal of the dummy gate electrode 111. In an embodiment, the third metal material 513 is a metal material such as W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc., and can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. to fill and / or overfill the opening left by the removal of the dummy gate electrode 111. In a specific embodiment, the third metal material 513 can be deposited to a thickness between about 100 nm and about 100 nm. peace treaty Thicknesses between , but any suitable material, deposition process, and thickness may be utilized.

[0069] Once the opening left by the removal of the dummy gate electrode 111 has been filled, the material may be planarized to remove any material outside the opening left by the removal of the dummy gate electrode 111. In certain embodiments, the removal may be performed using a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process may be utilized.

[0070] After the material of the replacement gate stack 505 has been formed and planarized, the material of the replacement gate stack 505 may be recessed and the replacement gate stack 505 may be covered with a capping layer 515. In an embodiment, the material of the replacement gate stack 505 may be recessed using, for example, a wet or dry etching process utilizing an etchant that is selective to the material of the replacement gate stack 505. However, any suitable process may be utilized.

[0071] Once the material of the replacement gate stack 505 has been recessed, a capping layer 515 may be deposited and planarized. In an embodiment, the capping layer 515 is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations of these, etc., deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. The capping layer 515 may be deposited to a depth between about peace treaty and then planarized using a planarization process such as chemical mechanical polishing so that the capping layer 515 is flat.

[0072] Once the replacement gate stack 505 has been formed, additional processing can proceed. For example, contacts can be formed through the ILD layer 503 to the source / drain regions 501, additional dielectric layers (not separately shown) can be formed over the ILD layer 503, contacts can be formed to the replacement gate stack 505, and metal layers can be formed to interconnect the various devices. Any suitable additional steps can be utilized to aid in the fabrication of the various devices, and all such steps are intended to be included within the scope of the embodiments.

[0073] According to an embodiment, a method for manufacturing a semiconductor device is provided, the method including forming a gate stack above a semiconductor substrate, forming a first opening in the semiconductor substrate using a first etching process, and reshaping the first opening into a second opening using a second etching process different from the first etching process, wherein the second etching process is a radical etching process.

[0074] In the above method, the first opening is formed in a fin of the semiconductor substrate.

[0075] In the above method, the free radical etching process further comprises: exciting an etching precursor into plasma; and separating free radicals from the plasma.

[0076] In the above method, the radical etching process further comprises: exciting an etching precursor into plasma; and separating radicals from the plasma, wherein the etching precursor is ammonia.

[0077] In the above method, the first etching process is reactive ion etching.

[0078] In the above method, wherein the first etching process is reactive ion etching, wherein the radical etching process is isotropic.

[0079] In the above method, the second opening undercuts the gate stack by a distance between 1 nm and 4 nm.

[0080] According to another embodiment, a method for manufacturing a semiconductor device is provided. The method includes forming a dummy gate stack above a semiconductor fin of a substrate, the dummy gate stack including a spacer structure. A portion of the semiconductor fin is removed to form a first opening, wherein the first opening is formed using an anisotropic etching process. The first opening is modified to a second opening, wherein the modifying includes forming a plasma from a precursor and directing radicals from the plasma toward the semiconductor fin while filtering charged particles from the plasma to prevent the charged particles from reaching the semiconductor fin.

[0081] In the above method, wherein the first spacer structure has an overhang above the surface of the semiconductor fin of between 1 nm and 4 nm after the modification.

[0082] In the above method, wherein the second opening has a difference of less than 3 nm between a surface proximity distance and a tip proximity distance.

[0083] In the above method, modifying the first opening also modifies the third opening, wherein the second opening is located in the first region of the substrate and the third opening is located in the second region of the substrate, and wherein the depth loading between the second opening and the third opening is between -3nm and 3nm.

[0084] In the above method, wherein modifying the first opening also modifies the third opening, wherein the second opening is located in a first region of the substrate and the third opening is located in a second region of the substrate, and wherein the depth loading between the second opening and the third opening is between -3nm and 3nm, wherein the first region includes a second spacer structure adjacent to the first spacer structure, wherein the second spacer structure is separated from the first spacer structure by a distance of less than 100nm.

[0085] In the above method, wherein modifying the first opening also modifies the third opening, wherein the second opening is located in a first region of the substrate and the third opening is located in a second region of the substrate, and wherein the depth loading between the second opening and the third opening is between -3nm and 3nm, wherein the first region includes a second spacer structure adjacent to the first spacer structure, wherein the second spacer structure is separated from the first spacer structure by a distance less than 100nm, wherein the first region includes the second spacer structure adjacent to the first spacer structure, wherein the second spacer structure is separated from the first spacer structure by a distance between 20nm and 50nm.

[0086] In the above method, wherein modifying the first opening also modifies the third opening, wherein the second opening is located in the first region of the substrate and the third opening is located in the second region of the substrate, and wherein the depth loading between the second opening and the third opening is between -3nm and 3nm, wherein the first region includes a second spacer structure adjacent to the first spacer structure, wherein the second spacer structure is separated from the first spacer structure by a distance less than 100nm, wherein the second region includes a third spacer structure adjacent to the third opening and a fourth spacer structure adjacent to the third spacer structure, wherein the third spacer structure is separated from the fourth spacer structure by a distance between 100nm and 400nm.

[0087] According to yet another embodiment, a semiconductor device is provided, the semiconductor device including a first semiconductor fin located above a substrate and a gate stack located above the first semiconductor fin. First sidewall spacers are located on sidewalls of the gate stack, and a first opening is located within the first semiconductor fin and undercuts the first spacer. The difference between a surface-proximate distance and a tip-proximate distance of the first opening is less than 3 nm.

[0088] In the above semiconductor device, the first spacer overhangs the first opening by between 1 nm and 4 nm.

[0089] In the above semiconductor device, the surface channel length is between 30 nm and 40 nm.

[0090] In the above semiconductor device, the surface channel length is between 30 nm and 40 nm, and the tip channel length is between 20 nm and 40 nm.

[0091] In the above-mentioned semiconductor device, it also includes: a second opening located in a second semiconductor fin above the substrate, and the depth loading between the first opening and the second opening is between -3nm and 3nm, wherein the first opening is located in a first region of the substrate having a first density, and the second opening is located in a second region of the substrate having a second density different from the first density.

[0092] In the above-mentioned semiconductor device, it also includes: a second opening located in a second semiconductor fin above the substrate, and the depth loading between the first opening and the second opening is between -3nm and 3nm, wherein the first opening is located in a first region of the substrate having a first density, and the second opening is located in a second region of the substrate having a second density different from the first density, and the semiconductor device also includes a second spacer adjacent to the first spacer in the first region of the substrate, wherein the first spacer is separated from the second spacer by a distance between 20nm and 50nm.

[0093] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various variations, substitutions, and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising: a first semiconductor fin located above the substrate; a gate stack located above the first semiconductor fin; a first spacer located on a sidewall of the gate stack; as well as a first opening located within the first semiconductor fin and undercutting the first spacer, wherein a surface proximity distance and a tip proximity distance of the first opening have a difference of less than 3 nm, and if a reference line is aligned with a sidewall of the gate stack, a first distance is measured along a top surface of the first semiconductor fin from the reference line to a tip of the first semiconductor fin adjacent to the first opening to obtain the tip proximity distance, and a second distance is measured from the reference line to an outer edge of the first spacer around the first opening at an intermediate height of the first semiconductor fin to obtain the surface proximity distance; A second opening is located in a second semiconductor fin above the substrate, wherein the first opening has a first depth and the second opening has a second depth different from the first depth.

2. The semiconductor device according to claim 1, wherein The first spacer overhangs the first opening by between 1 nm and 4 nm.

3. The semiconductor device according to claim 1, wherein The surface channel length is between 30 nm and 40 nm.

4. The semiconductor device according to claim 3, wherein The tip channel length is between 20 nm and 40 nm. The semiconductor device according to claim 1 , wherein A depth loading between the first opening and the second opening is between -3 nm and 3 nm, wherein the first opening is located in a first region of the substrate having a first density, and the second opening is located in a second region of the substrate having a second density different from the first density.

6. The semiconductor device according to claim 5, further comprising a second spacer adjacent to the first spacer in the first region of the substrate, wherein The first spacer is spaced apart from the second spacer by a distance between 20 nm and 50 nm.

7. A semiconductor device comprising: a first gate stack adjacent to a second gate stack in a first region of the substrate, the first gate stack being separated from the second gate stack by a first distance between 20 nm and 50 nm; a third gate stack adjacent to the fourth gate stack in the second region of the substrate, the third gate stack being separated from the fourth gate stack by a second distance between 100 nm and 400 nm; a first epitaxial region between the first gate stack and the second gate stack, the first epitaxial region extending into the first semiconductor fin of the substrate by a third distance; as well as A second epitaxial region is provided between the third gate stack and the fourth gate stack, wherein the second epitaxial region extends to a fourth distance different from the third distance in the second semiconductor fin of the substrate, wherein the difference between the third distance and the fourth distance is -3 nm and 3 nm.

8. The semiconductor device according to claim 7, wherein One of the first gate stack or the third gate stack has a surface proximity distance between 20 Å and 200 Å and a tip proximity distance between 1 nm and 4 nm.

9. The semiconductor device according to claim 8, wherein The difference between the surface proximity distance and the tip proximity distance is less than 3 nm.

10. The semiconductor device according to claim 8, wherein The surface proximity distance is between 20 Å and 50 Å.

11. The semiconductor device according to claim 8, wherein The surface proximity distance is between 50 Å and 2000 Å.

12. The semiconductor device according to claim 7, wherein A surface channel length within the first semiconductor fin is between 30 nm and 40 nm.

13. The semiconductor device according to claim 7, wherein Gate spacers adjacent to the first gate stack have a canopy distance between 1 nm and 4 nm.

14. A semiconductor device comprising: a semiconductor fin adjacent to the first gate stack, wherein the semiconductor fin has a surface channel length between 30 nm and 40 nm; and a first opening located in the semiconductor fin, wherein the first opening has a difference between a surface proximity distance and a tip proximity distance of less than 3 nm, and the first opening has a first depth; A second opening is located in the second semiconductor fin, the second opening having a second depth different from the first depth.

15. The semiconductor device according to claim 14, wherein The gate spacers of the first gate stack have a cantilever distance between 1 nm and 4 nm.

16. The semiconductor device according to claim 14, wherein The first opening has the first depth between 30 nm and 70 nm.

17. The semiconductor device according to claim 16, wherein The first depth is greater than the second depth.

18. The semiconductor device according to claim 14, wherein A difference between the first depth and the second depth is no greater than 3 nm.

19. The semiconductor device according to claim 14, wherein The second depth is between 30 nm and 70 nm.

20. The semiconductor device according to claim 15, wherein If a reference line is aligned with a sidewall of the first gate stack, a first distance is measured from the reference line to a tip of the semiconductor fin adjacent to the first opening along a top surface of the semiconductor fin to obtain the tip proximity distance, and a second distance is measured from the reference line to an outer edge of the gate spacer around the first opening at a mid-height of the semiconductor fin to obtain the surface proximity distance.

Images