A four-terminal perovskite and crystalline silicon stacked battery component and its preparation method

Abstract

The present invention relates to a four-terminal perovskite and crystalline silicon laminated battery assembly, comprising an upper encapsulation glass, an upper adhesive film, a perovskite battery assembly string, an intermediate adhesive film, a crystalline silicon battery assembly string, a lower adhesive film and a lower encapsulation glass arranged in sequence from top to bottom, the perovskite battery assembly string and the crystalline silicon battery assembly string have similar short-circuit current and open-circuit voltage, and the perovskite battery assembly string and the crystalline silicon battery assembly string share an inverter. The present invention also discloses a method for preparing the battery assembly. The output power of the perovskite battery assembly string used in the present invention is similar to that of the crystalline silicon battery assembly, and the upper and lower battery assembly strings can be connected in any series-parallel manner, so that the connection method of the four-terminal laminated battery has diversity, and is a four-terminal perovskite and crystalline silicon laminated battery assembly without current loss.

Description

Technical Field

[0001] The present invention belongs to the technical field of perovskite battery assembly preparation, and in particular relates to a four-terminal perovskite and crystalline silicon stacked battery assembly and a preparation method thereof. Background Art

[0002] The existing two-terminal perovskite and crystalline silicon stacked cells require current matching between the upper and lower cells, and require the top perovskite to have a high band gap (about 1.7eV, higher than the band gap of the general perovskite light-absorbing layer of 1.5eV~1.6eV). The preparation method is complex and the repeatability is poor, which makes it unsuitable for commercial applications. The two-terminal stacked cells are generally connected in series, but the voltage difference between the perovskite cell and the crystalline silicon cell is large, which affects the improvement of the overall performance of the stack. And as the size increases, the series resistance generated by the transparent electrode of the semi-transparent perovskite cell on the top will gradually increase.

[0003] The four-terminal perovskite battery has a simple preparation method and the circuits of the two batteries are independent of each other. The existing crystalline silicon module can be directly used for the preparation of the four-terminal laminated battery. Only an additional semi-transparent perovskite photovoltaic module needs to be prepared to be stacked and used. Therefore, it has great potential for commercial application. In the conventional four-terminal laminated battery module, the original series structure and cutting method of the perovskite module are retained. In this cutting method, the open circuit voltage of the perovskite sub-cells inside the monolithic perovskite battery increases after being connected in series, and the short-circuit current remains unchanged, including the patent with the published publication number of patent CN111312905A. Although the top and bottom can realize separate series-parallel circuits without affecting each other, due to the inherent properties of the perovskite material, it has a higher open circuit voltage per unit area than the crystalline silicon battery module, but the short-circuit current is indeed lower than that of the crystalline silicon battery module. Therefore, the top perovskite battery module and the bottom crystalline silicon battery module have different output powers per unit area, requiring two inverters suitable for different output voltages and currents. The inverter is very expensive, which limits the commercial application of four-terminal perovskite and crystalline silicon stacked battery modules. In addition, the laser cutting method of conventional perovskite battery modules (such as three cuts to form a series structure) will cause many laser-cut grooves in the battery module, which will increase the risk of battery module attenuation.

[0004] Since the band gap of perovskite and crystalline silicon changes with temperature in different trends, both the two-terminal structure and the four-terminal structure of perovskite and crystalline silicon stacked battery components have the defect that the current and voltage cannot be fully matched. When used outdoors, the temperature is higher than 50 degrees Celsius from time to time, which will cause the band gap of the light absorption layer of the two batteries to change, resulting in a greater difference in voltage, current and output power, and accelerate the attenuation and aging of equipment such as battery components and adapters. At the same time, for the four-terminal structure of perovskite and crystalline silicon stacked battery components, the voltage of the top perovskite battery component is basically greater than 0.8V, but the voltage of the bottom crystalline silicon battery component is less than 0.7V. If the current and voltage of the two battery components at the top and bottom do not match, we need to use two inverters suitable for different applications, which greatly increases the operating cost. Therefore, although having an independent output does not affect the normal use of the four-terminal stacked battery component, it increases the operating and maintenance costs. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a four-terminal perovskite and crystalline silicon stacked battery component and a preparation method thereof, which solves the problem that the working current and working voltage of the top perovskite component and the bottom crystalline silicon component do not match, thus requiring two adapted inverters. At the same time, laser cutting of the battery component in the effective light absorption area is avoided, and a transparent electrode layer is sputtered on the effective area using a mask plate, so that the battery forms a plurality of parallel sub-battery structures, and the prepared top perovskite battery is more stable.

[0006] The present invention is implemented in this way, providing a four-terminal perovskite and crystalline silicon stacked battery assembly, including an upper packaging glass, an upper layer of glue film, a perovskite battery assembly string, an intermediate glue film, a crystalline silicon battery assembly string, a lower layer of glue film and a lower packaging glass arranged in sequence from top to bottom, the perovskite battery assembly string and the crystalline silicon battery assembly string have similar short-circuit current and open-circuit voltage, the perovskite battery assembly string and the crystalline silicon battery assembly string share an inverter, and the upper packaging glass, the upper layer of glue film, the perovskite battery assembly string and the intermediate glue film are respectively in a translucent or transparent state.

[0007] Furthermore, the perovskite battery assembly string includes a plurality of perovskite batteries connected in series with each other through a conductive circuit, and each of the perovskite batteries includes a positive bus and a negative bus strip and a plurality of perovskite sub-batteries connected in parallel with each other through the positive bus and the negative bus strip.

[0008] Furthermore, each of the perovskite cells includes, from bottom to top, a conductive substrate, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer, a buffer layer, a transparent electrode layer and a passivation layer. The positive bus and the negative bus belts are respectively arranged on both sides of the perovskite cell and are located on the surface of the transparent electrode layer. The positive bus and the negative bus belts are isolated from each other by the passivation layer. A scoring groove is arranged on each of the perovskite cells, and the scoring groove is filled with the same material as the passivation layer. A common transparent electrode layer is arranged on one side of the scoring groove. The bottom surface of the common transparent electrode layer is in contact with and connected to the conductive substrate, and the top surface thereof is in contact with and connected to the bus belt. A plurality of perovskite sub-cells are arranged on the other side of the scoring groove. The transparent electrode layers of two adjacent perovskite sub-cells are separated by a spacing groove, and the spacing groove is filled with the same material as the passivation layer.

[0009] The present invention is implemented in this way, and also provides a method for preparing the four-terminal perovskite and crystalline silicon stacked battery assembly as described above, comprising the following steps:

[0010] Step 1: sequentially preparing a first carrier transport layer, a perovskite light absorption layer and a second carrier transport layer on a conductive substrate;

[0011] Step 2: performing edge cleaning on a side region of a conductive substrate on which a second carrier transport layer has been prepared, removing the first carrier transport layer, the perovskite light absorption layer and the second carrier transport layer that have been prepared on the surface of the side region, and only retaining the conductive layer portion of the conductive substrate;

[0012] Step 3: using the first mask to prepare a buffer layer on the surface of the retained second carrier transport layer, leaving the mask area of ​​the first mask blank;

[0013] Step 4: using a second mask to prepare a transparent electrode layer on the buffer layer, and separating the transparent electrode layer on the surface of the buffer layer into a plurality of small areas where perovskite sub-cells of the same size are located through the provided spacing grooves, and preparing a common transparent electrode layer in the side area at the same time, and the common transparent electrode layer is directly prepared on the conductive substrate;

[0014] Step 5: laying a busbar on the surface of the transparent electrode layer and the common transparent electrode layer, using a third mask to remove the remaining surface of the busbar on the transparent electrode layer and the common transparent electrode layer to prepare a passivation layer, and the material of the passivation layer also fills the scribed grooves and each spacing groove, so as to obtain a single perovskite cell;

[0015] Step 6: Connecting the individual perovskite cells in series through a conductive circuit to obtain a perovskite cell assembly string;

[0016] Step seven: Lay the lower encapsulation glass, the lower layer of adhesive film, the prepared crystalline silicon battery module string, the middle adhesive film, the perovskite battery module string prepared in step six, the upper layer of adhesive film and the upper encapsulation glass in sequence, and then put the assembled components into a laminator for lamination to obtain a four-terminal perovskite and crystalline silicon laminated battery module.

[0017] Compared with the prior art, the four-terminal perovskite and crystalline silicon laminated battery assembly and its preparation method of the present invention, by using a narrow bandgap perovskite light-absorbing layer (bandgap between 1.2eV and 1.5eV), and the parallel connection of the internal structure of the monolithic battery, reduce the voltage of the perovskite battery, increase the short-circuit current, and achieve the current and voltage matching of the monolithic perovskite battery and the crystalline silicon battery assembly. And it changes the method of three cuttings required in the commonly used series structure, only one laser cutting edge cleaning is required, and the cutting is not done on the effective light-absorbing area, avoiding the exposure of the laser cutting groove to the outdoor long-term use. The battery performance attenuation caused by long-term use. The present invention also proposes a method for preparing a four-terminal perovskite and crystalline silicon laminated battery assembly, and the crystalline silicon assembly and the perovskite assembly with similar open circuit voltage and short-circuit photocurrent are connected in parallel and in series with each other, which will not cause losses to each other like the voltage and current are different, affecting the life of the battery assembly. The perovskite module prepared by the present invention has an open circuit voltage and short circuit current similar to those of a crystalline silicon battery module, and can realize arbitrary series and parallel connections, making the connection method of the four-terminal stacked battery diverse. The prepared semi-transparent perovskite battery module has an output power similar to that of the crystalline silicon battery module, and only needs to use a common inverter. It is a four-terminal perovskite and crystalline silicon stacked battery module with no current loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the internal structure of a preferred embodiment of a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention;

[0019] Figure 2 This is a schematic diagram of the internal structure of the component prepared in step 1 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention;

[0020] Figure 3 A schematic diagram of the internal structure of the component prepared in step 2 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention;

[0021] Figure 4a The figure is a schematic cross-sectional view of the internal structure of the component prepared in step 3 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention, Figure 4b It is a top view schematic diagram;

[0022] Figure 5a The figure is a schematic cross-sectional view of the internal structure of the component prepared in step 4 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention, Figure 5bIt is a top view schematic diagram;

[0023] Figure 6a This is a schematic cross-sectional view of the internal structure of the component prepared in step 5 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention, Figure 6b It is a top view schematic diagram;

[0024] Figure 7 A schematic diagram of the series connection of 48 crystalline silicon battery component strings and perovskite battery component strings in the four-terminal perovskite and crystalline silicon stacked battery component prepared in step 5 of the preparation method of the four-terminal perovskite and crystalline silicon stacked battery component of the present invention;

[0025] Figure 8 A schematic diagram of the series connection of a string of 24 crystalline silicon battery components and a string of perovskite battery components in a four-terminal perovskite and crystalline silicon stacked battery component prepared in step 5 of the method for preparing a four-terminal perovskite and crystalline silicon stacked battery component of the present invention;

[0026] Fig. 9 This is a schematic diagram of the internal structure of the perovskite battery prepared in Example 1 of the present invention;

[0027] Fig.10 Schematic diagram of the internal structure of the perovskite battery prepared in Example 2 of the present invention. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] Please refer to Figure 1 as well as Figure 2 As shown, a preferred embodiment of the four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention includes an upper packaging glass 1, an upper adhesive film 2, a perovskite battery assembly string 3, an intermediate adhesive film 4, a crystalline silicon battery assembly string 5, a lower adhesive film 6 and a lower packaging glass 7, which are arranged in sequence from top to bottom.

[0030] Butyl rubber 8 is provided around the edges of the perovskite battery assembly string 3 and the crystalline silicon battery assembly string 5 for sealing. The perovskite battery assembly string 3 and the crystalline silicon battery assembly string 5 have similar short-circuit current and open-circuit voltage, and the perovskite battery assembly string 3 and the crystalline silicon battery assembly string 5 share an inverter (not shown in the figure). The upper encapsulation glass 1, the upper adhesive film 2, the perovskite battery assembly string 3 and the intermediate adhesive film 4 are respectively in a semi-transparent or transparent state.

[0031] The perovskite battery assembly string 3 includes a plurality of perovskite batteries 9 connected in series via a conductive circuit, and each of the perovskite batteries includes a positive and a negative busbar 10 and a plurality of perovskite sub-batteries 11 connected in parallel via the positive and negative busbars 10 .

[0032] Each of the perovskite cells 9 includes, from bottom to top, a conductive substrate 91, a first carrier transport layer 92, a perovskite light absorption layer 93, a second carrier transport layer 94, a buffer layer 95, a transparent electrode layer 96 and a passivation layer 97. The positive and negative bus strips 10 are respectively arranged on both sides of the perovskite cell 9 and on the surface of the transparent electrode 96. The positive and negative bus strips 10 are isolated from each other by the passivation layer 97. The first carrier transport layer 92 is an electron transport layer or a hole transport layer, and correspondingly, the second carrier transport layer 94 is a hole transport layer or an electron transport layer.

[0033] A scribe groove 12 is provided on each of the perovskite cells 9. The scribe groove 12 is filled with the same material as the passivation layer 97. A common transparent electrode layer 96' is provided on one side of the scribe groove 12. The bottom surface of the common transparent electrode layer 96' is in contact with and connected to the conductive substrate 91, and the top surface thereof is in contact with and connected to the busbar 10. A plurality of perovskite sub-cells 11 are provided in parallel on the other side of the scribe groove 12. The transparent electrode layers 96 of two adjacent perovskite sub-cells 11 are separated by the provided spacing grooves 13, and the same material as the passivation layer 97 is also filled in each spacing groove 13.

[0034] The materials for preparing the first carrier transport layer 92 and the second carrier transport layer 94 include any one of imide compounds, quinone compounds, fullerene (C60) and its derivatives, or any one of metal oxides including cadmium (Cd), zinc (Zn), indium (In), lead (Pb), molybdenum (Mo), tungsten (W), antimony (Sb), bismuth (Bi), copper (Cu), mercury (Hg), titanium (Ti), silver (Ag), manganese (Mn), iron (Fe), vanadium (V), tin (Sn), zirconium (Zr), strontium (Sr), gallium (Ga) and chromium (Cr). One, or any one of the perovskite oxides including strontium titanate (SrTiO3) and calcium titanate (CaTiO3), or aluminum oxide (Al2O3), tin oxide (SnO2), zinc magnesium oxide (MZO), zinc tin oxide (ZnSnO), titanium dioxide (TiO2), zinc oxide (ZnO), lithium fluoride (LiF), calcium fluoride (CaF2), magnesium oxide (MgO), niobium pentoxide (Nb2O5), 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene (S piro-MeOTAD), OMeTPA-FA, poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PSS), 3-hexyl substituted polythiophene (P3HT), poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), 4,4'-cyclohexylbis[N,N-di(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), N,N'-diphenyl-N,N'-di( At least one of 3-methylphenyl)-1,1'-biphenyl-4,4'-diamine (TPD), cuprous thiocyanate (CuSCN), nickel trioxide (Ni2O3), ferric oxide (Fe2O3), EDOT-OMeTPA, CzPAF-SBF, cuprous iodide (CuI), copper oxide (CuO), cuprous oxide (Cu2O), nickel oxide (NiO), molybdenum oxide (MoO3), and 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBI), and the thickness thereof is 10nm~300nm.

[0035] The material for preparing the perovskite light absorbing layer 93 is a narrow bandgap perovskite light absorbing material, including a halide crystal with an ABX3 structure, wherein A is at least one of methylamine, methylamidine, and cesium, B is any one of Sn, Bi, Sb, Ge, Cu, or Pb ions, and X is at least one of halogen F, Cl, Br, and I, and its thickness is 80nm to 500nm. The voltage of the perovskite battery prepared by the present invention is less than 1V, which is equivalent to the voltage of a crystalline silicon battery module.

[0036] The material for preparing the buffer layer 95 includes any one of fullerene (C60) and its derivatives, metal oxides, BCP, and LiF.

[0037] The material for preparing the transparent electrode layer 96 includes a composite electrode formed by at least one of AZO, ITO, IZO, silver nanowires, copper, silver, graphene, and carbon nanotubes, and the thickness thereof is 80 nm to 200 nm.

[0038] The passivation layer 97 includes an inorganic passivation layer, an organic passivation layer and a polymer passivation layer. The material for preparing the inorganic passivation layer includes any one of SiO2, SiNx, Al2O3, and BN; the material for preparing the organic passivation layer includes any one of arylene diamine derivatives, carbazole derivatives (containing carbazole groups and heterocyclic derivatives bonded to carbazole groups), phosphorus-oxy derivatives, and quinolinone derivatives; the material for preparing the polymer passivation layer includes any one of PEI, PMMA, PS, PU, ​​acrylic resin, and epoxy resin, and the thickness thereof is 100nm~1000nm.

[0039] The present invention also discloses a method for preparing the above-mentioned four-terminal perovskite and crystalline silicon stacked battery assembly, comprising the following steps:

[0040] Step 1: sequentially prepare a first carrier transport layer 92, a perovskite light absorption layer 93 and a second carrier transport layer 94 on a conductive substrate 91. Figure 2 shown.

[0041] Step 2: Clean the side region 98 of one side of the conductive substrate 91 on which the second carrier transport layer 94 has been prepared, remove the first carrier transport layer 92, the perovskite light absorption layer 93 and the second carrier transport layer 94 prepared on the surface of the side region 98, and only retain the conductive layer part of the conductive substrate 91. The cleaning method can be laser cutting or etching. Figure 3 shown.

[0042] Step 3: Use the first mask (not shown) to prepare a buffer layer 95 on the surface of the retained second carrier transport layer 94, leaving the mask area 98' of the first mask blank without preparing the buffer layer 95. The mask area 98' of the first mask is equivalent to the side area 98. Figure 4a and Figure 4b shown.

[0043] Step 4: Use a second mask (not shown in the figure) to prepare a transparent electrode layer 96 on the buffer layer 95. The mask area 98″ of the second mask includes the positions of the scribe grooves 12 and the spacing grooves 13. The transparent electrode layer 96 on the surface of the buffer layer 95 is divided into a plurality of small areas where the perovskite sub-cells 11 of the same size are located by the provided spacing grooves 13. At the same time, a common transparent electrode layer 96′ is prepared in the side area 98. The common transparent electrode layer 96′ is directly prepared on the conductive substrate 91. The common transparent electrode layer 96′ is separated from the other transparent electrode layers 96 by the scribe grooves 12. Figure 5a and Figure 5b shown.

[0044] Step 5: Lay the busbar 10 on the surface of the transparent electrode layer 96 and the common transparent electrode layer 96', and use a third mask (not shown in the figure) to remove the remaining surface of the busbar 10 on the transparent electrode layer 96 and the common transparent electrode layer 96' to prepare a passivation layer 97, and the material of the passivation layer 97 also fills the scribe groove 12 and each spacing groove 13, so as to obtain a single perovskite cell 9. Figure 6a and Figure 6b shown.

[0045] Step six: connect the individual perovskite cells 9 in series through a conductive circuit to obtain a perovskite cell assembly string 3.

[0046] Step 7: Lay the lower encapsulation glass 7, the lower adhesive film 6, the prepared crystalline silicon battery component string 5, the middle adhesive film 4, the perovskite battery component string 3 prepared in step 6, the upper adhesive film 2 and the upper encapsulation glass 1 in sequence, and then put the assembled components into a laminator for lamination to obtain a four-terminal perovskite and crystalline silicon stacked battery component, such as Figure 1 As shown, the prepared crystalline silicon battery component string 5 and the perovskite battery component string 3 have the same short-circuit current and matching rated voltage, which facilitates mutual series connection or parallel connection.

[0047] Figure 7 What is shown is that a crystalline silicon cell assembly string 5 including 24 crystalline silicon cells 5 ′ and a perovskite cell assembly string 3 including 24 perovskite cells 9 are connected in series.

[0048] Figure 8 The figure shows that a crystalline silicon cell assembly string 5 including 12 crystalline silicon cells 5 ′ and a perovskite cell assembly string 3 including 12 perovskite cells 9 are connected in series.

[0049] In step seven, the lamination parameters of the machine are: temperature 100° C. to 150° C., pressure 60 kPa to 90 kPa, and lamination time 5 min to 15 min.

[0050] The following is a specific example to further illustrate the method for preparing the four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention.

[0051] Example 1

[0052] Please also refer to Fig. 9 as well as Figure 1 to Figure 5a , Figure 5b As shown, the first embodiment of the method for preparing the four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention comprises the following steps:

[0053] (11). Clean the 16*16cm 2 Tin dioxide is prepared on the FTO surface (ie, the surface of the conductive substrate 91 ) as an electron transport layer (ie, the first carrier transport layer 92 ).

[0054] (12) Preparation of CsFASnF on SnO2 layer 0.3 I 2.7 Perovskite light absorbing layer 93. Prepare 0.9 mol / L CsFASnF 0.3 I 2.7 The DMSO solution was scraped onto the tin dioxide and annealed at 100°C for 10 min.

[0055] (13) Prepare a Spiro-OMeTAD hole transport layer (i.e., the second carrier transport layer 94) on the perovskite light absorption layer 93. Use laser cutting to clean the side edge area 98, leaving the FTO conductive layer on the glass.

[0056] (14) Using the first mask, a MoO3 buffer layer 95 is evaporated.

[0057] (15) Using the second mask plate, an ITO transparent electrode layer 96 is prepared to divide the semi-transparent perovskite battery 9 into 40 perovskite sub-batteries 11 of equal size to form a parallel structure. After the parallel connection, the current of the perovskite battery 9 increases by 40 times, while the voltage remains unchanged.

[0058] (16) Use a third mask to prepare an Al2O3 passivation layer 97.

[0059] (17) The positive and negative electrodes of the perovskite battery 9 are led out from the edge using the busbar 10, and a semi-transparent perovskite battery 9 with low open circuit voltage and high short circuit current is prepared, with a voltage of about 0.69V and a current of about 4A. Fig. 9 Different semi-transparent perovskite cells 9 are connected in series to obtain a semi-transparent perovskite cell assembly string 3.

[0060] (18) Lay a layer of EVA film (i.e., lower film 6) and butyl rubber 8 on the lower encapsulation glass 7, and then use a busbar 10 to seal the 16*16cm2 The positive and negative electrodes of the crystalline silicon battery are led out, and the voltage of the crystalline silicon battery is about 0.69V, and the current is about 4A. Different crystalline silicon batteries are connected in series to obtain a crystalline silicon battery assembly string 5.

[0061] (19). Lay a layer of EVA film (i.e., intermediate film 4) on the connected crystalline silicon battery assembly string 5, and then lay a string of semi-transparent perovskite battery assembly strings 3 prepared in step (17), with the coating surface facing downward. The top is the semi-transparent perovskite battery assembly string 3, and the bottom is the crystalline silicon battery assembly string 5. The upper and lower 48 battery assemblies are directly connected in series, and the voltage of the upper and lower battery assembly strings is about 33V, and the current is 4A, such as Figure 7 When 24 battery modules are connected in series, the voltage of the upper and lower battery module strings is about 16.6V and the current is 4A. Figure 8 shown.

[0062] (110). Then, an upper adhesive film 2 and an upper encapsulation glass 1 are laid on the top of the semi-transparent perovskite battery assembly string 3, and then the assembled battery assembly is placed in a laminator for lamination, wherein the lamination parameters are: temperature 120°C, pressure 60kPa, and lamination time 5min. After lamination, a four-terminal stacked structure of the perovskite battery assembly and the crystalline silicon battery assembly is obtained. Among them, the upper perovskite battery assembly string 3 and the lower crystalline silicon battery assembly string 5 have similar open circuit voltage and short circuit current, and have similar output power. There is no need to use different inverters, and only one common inverter is used, which saves production and operation costs.

[0063] Example 2

[0064] Please also refer to Fig.10 as well as Figure 1 to Figure 5a , Figure 5b As shown, the second embodiment of the method for preparing the four-terminal perovskite and crystalline silicon stacked battery assembly of the present invention comprises the following steps:

[0065] (21). Clean the 16*16cm 2 PEDOT:PSS is prepared on the ITO surface (ie, the surface of the conductive substrate 91 ) as a hole transport layer (ie, the first carrier transport layer 92 ).

[0066] (22). Preparation of MAPbI3 perovskite absorber layer on PEDOT:PSS93.

[0067] (23) A C60 electron transport layer (i.e., the second carrier transport layer 94) is prepared on the perovskite light absorption layer 93. Laser cutting is used to clean the side edge region 98, remove a portion of PEDOT:PSS, MAPbI3, and C60, and retain the ITO conductive layer portion on the glass.

[0068] (24) Using the first mask, a BCP buffer layer 95 is evaporated.

[0069] (25) Use the second mask to prepare the AZO transparent electrode layer 96. Divide the semi-transparent perovskite cell 9 into 40 perovskite sub-cells 11 of equal size to form a parallel structure. After the parallel connection, the current of the perovskite cell 9 increases by 40 times, while the voltage remains unchanged.

[0070] (26) A tris(8-hydroxyquinoline)aluminum passivation layer 97 is prepared using a third mask.

[0071] (27). The positive and negative electrodes of the perovskite battery 9 are led out from the edge using the busbar 10, and a semi-transparent perovskite battery 9 with low open circuit voltage and high short circuit current is prepared, with a voltage of about 0.69V and a current of about 4A. Fig.10 Different semi-transparent perovskite cells 9 are connected in series to obtain a semi-transparent perovskite cell assembly string 3.

[0072] (28) A layer of EVA film (i.e., lower film 6) and butyl rubber 8 are applied on the lower encapsulation glass 7, and then a busbar 10 is used to connect the 16*16cm 2 The positive and negative electrodes of the crystalline silicon battery are led out, and the voltage of the crystalline silicon battery is about 0.69V, and the current is about 4A. Different crystalline silicon batteries are connected in series to obtain a crystalline silicon battery assembly string 5.

[0073] (29). Lay a layer of EVA film (i.e., intermediate film 4) on the connected crystalline silicon battery module, and then lay a string of semi-transparent perovskite battery module strings 3 prepared in step (27), with the coated surface facing downward. The top is the semi-transparent perovskite battery module string 3, and the bottom is the crystalline silicon battery module string 5. The upper and lower 48 battery modules are directly connected in series, and the voltage of the upper and lower battery module strings is about 33V, and the current is 4A, such as Figure 7 When 24 battery modules are connected in series, the voltage of the upper and lower battery module strings is about 16.6V and the current is 4A. Figure 8 shown.

[0074] (210). Then, an upper adhesive film 2 and an upper encapsulation glass 1 are laid on the top of the semi-transparent perovskite battery assembly string 3, and then the assembled battery assembly is placed in a laminator for lamination, wherein the lamination parameters are: temperature 120°C, pressure 60kPa, and lamination time 5min. After lamination, a four-terminal stacked structure of the perovskite battery assembly and the crystalline silicon battery assembly is obtained. Among them, the upper perovskite battery assembly string 3 and the lower crystalline silicon battery assembly string 5 have similar open circuit voltage and short circuit current, and have similar output power. There is no need to use different inverters, and only one common inverter is used, which saves production and operation costs.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A four-terminal perovskite and crystalline silicon stacked battery assembly, characterized in that: The invention comprises an upper encapsulation glass, an upper adhesive film, a perovskite battery assembly string, an intermediate adhesive film, a crystalline silicon battery assembly string, a lower adhesive film and a lower encapsulation glass arranged in sequence from top to bottom, wherein the perovskite battery assembly string and the crystalline silicon battery assembly string have the same short-circuit current and a matching rated voltage, the perovskite battery assembly string and the crystalline silicon battery assembly string share an inverter, and the upper encapsulation glass, the upper adhesive film, the perovskite battery assembly string and the intermediate adhesive film are respectively in a semi-transparent or transparent state; The perovskite battery assembly string includes a plurality of perovskite batteries connected in series via a conductive circuit, and each of the perovskite batteries includes a positive busbar and a negative busbar and a plurality of perovskite sub-batteries connected in parallel via the positive busbar and the negative busbar; Each of the perovskite cells includes, from bottom to top, a conductive substrate, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer, a buffer layer, a transparent electrode layer and a passivation layer. The positive and negative busbars are respectively arranged on both sides of the perovskite cell and on the surface of the transparent electrode layer. A scribe groove is arranged on each of the perovskite cells, and the scribe groove is filled with the same material as the passivation layer. A common transparent electrode layer is arranged on one side of the scribe groove. The bottom surface of the common transparent electrode layer is in contact with and connected to the conductive substrate, and the top surface thereof is in contact with and connected to the busbar. A plurality of perovskite sub-cells are arranged in parallel on the other side of the scribe groove. The transparent electrode layers of two adjacent perovskite sub-cells are separated by a spacer groove, and each spacer groove is also filled with the same material as the passivation layer.

2. The four-terminal perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The materials for preparing the first carrier transport layer and the second carrier transport layer include any one of imide compounds, quinone compounds, fullerenes and their derivatives, or any one of metal oxides including cadmium, zinc, indium, lead, molybdenum, tungsten, antimony, bismuth, copper, mercury, titanium, silver, manganese, iron, vanadium, tin, zirconium, strontium, gallium and chromium, or any one of perovskite oxides including strontium titanate and calcium titanate, or aluminum oxide, tin oxide, zinc magnesium oxide, zinc tin oxide, titanium dioxide, zinc oxide, lithium fluoride, calcium fluoride, magnesium oxide, niobium pentoxide, 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene, OMeTPA-FA, poly(3,4-ethylenedioxythiophene)-polystyrene sulfone At least one of acid, 3-hexyl substituted polythiophene, poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine], 4,4'-cyclohexylbis[N,N-bis(4-methylphenyl)aniline], N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine, N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine, cuprous thiocyanate, nickel trioxide, ferric oxide, EDOT-OMeTPA, CzPAF-SBF, cuprous iodide, copper oxide, cuprous oxide, nickel oxide, molybdenum oxide, and 1,3,5-tri(1-phenyl-1H-benzimidazol-2-yl)benzene, and the thickness thereof is 10nm~300nm.

3. The four-terminal perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The material for preparing the perovskite light-absorbing layer is a narrow-bandgap perovskite light-absorbing material, including a halide crystal with an ABX3 structure, wherein A is at least one of methylamine, methylamidine, and cesium, B is any one of Sn, Bi, Sb, Ge, Cu or Pb ions, and X is at least one of the halogens F, Cl, Br, and I, and its thickness is 80nm~500nm.

4. The four-terminal perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The material for preparing the buffer layer includes any one of fullerene and its derivatives, metal oxides, BCP and LiF.

5. The four-terminal perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The material for preparing the transparent electrode layer includes a composite electrode formed by at least one of AZO, ITO, IZO, silver nanowires, copper, silver, graphene, and carbon nanotubes, and the thickness thereof is 80nm-200nm.

6. The four-terminal perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The passivation layer includes an inorganic passivation layer, an organic passivation layer and a polymer passivation layer. The material for preparing the inorganic passivation layer includes any one of SiO2, SiNx, Al2O3, and BN. The material for preparing the organic passivation layer includes any one of arylene diamine derivatives, carbazole derivatives, phosphorus-oxy derivatives, and quinolinone derivatives. The material for preparing the polymer passivation layer includes any one of PEI, PMMA, PS, PU, ​​acrylic resin, and epoxy resin, and its thickness is 100nm~1000nm.

7. A method for preparing a four-terminal perovskite and crystalline silicon stacked battery assembly as claimed in any one of claims 1 to 6, characterized in that: The steps include: Step 1: sequentially preparing a first carrier transport layer, a perovskite light absorption layer and a second carrier transport layer on a conductive substrate; Step 2: performing edge cleaning on a side region of a conductive substrate on which a second carrier transport layer has been prepared, removing the first carrier transport layer, the perovskite light absorption layer and the second carrier transport layer that have been prepared on the surface of the side region, and only retaining the conductive layer portion of the conductive substrate; Step 3: using the first mask to prepare a buffer layer on the surface of the retained second carrier transport layer, leaving the mask area of ​​the first mask blank; Step 4: using a second mask to prepare a transparent electrode layer on the buffer layer, and separating the transparent electrode layer on the surface of the buffer layer into a plurality of small areas where perovskite sub-cells of the same size are located through the provided spacing grooves, and preparing a common transparent electrode layer in the side area at the same time, and the common transparent electrode layer is directly prepared on the conductive substrate; Step 5: laying a busbar on the surface of the transparent electrode layer and the common transparent electrode layer, using a third mask to remove the remaining surface of the busbar on the transparent electrode layer and the common transparent electrode layer to prepare a passivation layer, and the material of the passivation layer also fills the scribed grooves and each spacing groove, so as to obtain a single perovskite cell; Step 6: Connecting the individual perovskite cells in series through a conductive circuit to obtain a perovskite cell assembly string; Step seven: Lay the lower encapsulation glass, the lower layer of adhesive film, the prepared crystalline silicon battery module string, the middle adhesive film, the perovskite battery module string prepared in step six, the upper layer of adhesive film and the upper encapsulation glass in sequence, and then put the assembled components into a laminator for lamination to obtain a four-terminal perovskite and crystalline silicon laminated battery module.

8. The method for preparing a four-terminal perovskite and crystalline silicon laminated battery assembly according to claim 7, characterized in that: In step seven, the laminating parameters of the laminator are: temperature 100° C. to 150° C., pressure 60 kPa to 90 kPa, and laminating time 5 min to 15 min.

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