Power factor correction converter and method of controlling the same

Abstract

The application provides a power factor correction converter and a control method thereof. The power factor correction converter includes a first bridge arm, an inductor, a second bridge arm and a control unit. The first bridge arm includes a first switch and a second switch connected in series, wherein the first switch and the second switch have a first node therebetween. The inductor has two ends coupled to the first node and a first end of an alternating current (AC) power source respectively. The second bridge arm includes a third switch and a fourth switch connected in series, wherein the third switch and the fourth switch have a second node therebetween, and the second node is coupled to a second end of the AC power source. The control unit controls a proportion of a high-level potential on the second node in each power frequency cycle to be less than a threshold value, wherein the threshold value is equal to (250 / Vbus) 2 , and Vbus is an output voltage of the power factor correction converter.

Description

TECHNICAL FIELD

[0001] The present application relates to a power factor correction converter and a control method thereof, in particular to a totem-pole power factor correction converter and a control method thereof. BACKGROUND

[0002] For the existing Boost PFC (Power Factor Correction) converter, since the rectifier bridge diode loss is large, the power density is difficult to improve. In comparison, the totem-pole PFC converter does not have a rectifier bridge, so its efficiency is higher. With the development of power devices, the totem-pole PFC converter is receiving more and more attention.

[0003] However, compared with the Boost PFC converter, the primary and secondary side ground working voltage of the rear stage isolation converter of the totem-pole PFC is higher. Since the interval distance between the primary and secondary sides of the converter is determined by the primary and secondary side ground working voltage, a higher primary and secondary side ground working voltage will result in a longer interval distance between the primary and secondary sides of the rear stage converter of the totem-pole PFC, thereby making the isolation communication optocoupler volume required between the primary and secondary sides larger and the cost higher.

[0004] Therefore, how to develop a power factor correction converter and a control method thereof that can improve the above-mentioned prior art is a current urgent need. SUMMARY

[0005] The purpose of the present application is to provide a power factor correction converter and a control method thereof, which controls the proportion of the high-level potential on the slow bridge arm midpoint in each power frequency cycle to be less than a threshold value, thereby reducing the working voltage of the primary and secondary side ground of the rear stage converter of the power factor correction converter, and further shortening the interval distance between the primary and secondary sides of the rear stage converter. In this way, the isolation communication optocoupler volume between the primary and secondary sides can be reduced, and the cost can be reduced.

[0006] To achieve the above-mentioned purpose, the present application provides a power factor correction converter, which comprises a first bridge arm, an inductor, a second bridge arm and a control unit. The first bridge arm comprises a first switch and a second switch connected in series with each other, wherein the first switch and the second switch have a first node therebetween. The two ends of the inductor are respectively coupled to the first node and a first end of an alternating current power supply. The second bridge arm comprises a third switch and a fourth switch connected in series with each other, wherein the third switch and the fourth switch have a second node therebetween, and the second node is coupled to a second end of the alternating current power supply. The control unit controls the proportion of the high-level potential on the second node in each power frequency cycle to be less than a threshold value, wherein the threshold value is equal to (250 / Vbus) 2 , and Vbus is the output voltage of the power factor correction converter.

[0007] To achieve the above object, the application provides a control method, which is suitable for a power factor correction converter. The power factor correction converter comprises a first bridge arm, a second bridge arm and an inductor. The first bridge arm comprises a first switch and a second switch connected in series with each other, and the first switch and the second switch have a first node therebetween. The inductor has two ends respectively coupled to the first node and a first end of an alternating current power supply. The second bridge arm comprises a third switch and a fourth switch connected in series with each other, and the third switch and the fourth switch have a second node therebetween, and the second node is coupled to a second end of the alternating current power supply. The control method comprises: controlling a proportion of a high-level potential on the second node in each power frequency switching cycle to be less than a threshold value, wherein the threshold value is equal to (250 / Vbus) 2 , and Vbus is an output voltage of the power factor correction converter. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A schematic diagram of working voltage between primary side ground and secondary side ground of a post-stage isolation converter connected to the power factor correction converter.

[0009] Figure 2 A schematic diagram of working voltage between primary side ground and secondary side ground of the post-stage isolation converter in Figure 1 .

[0010] Figure 3 A schematic diagram of circuit structure of the power factor correction converter of the preferred embodiment of the application.

[0011] Figure 4 A schematic diagram of normal working waveform of the power factor correction converter of the preferred embodiment of the application.

[0012] Figure 5 , Figure 6 and Figure 7 are respectively schematic diagrams of working waveforms of the power factor correction converter of the application when controlled by the control method of various preferred embodiments of the application.

[0013] Figure 8 A schematic diagram showing a variation of the circuit structure of the power factor correction converter of the application.

[0014] In the drawings, reference signs are explained as follows:

[0015] 1: power factor correction converter

[0016] 2: post-stage isolation converter

[0017] VPS: voltage between primary side ground and secondary side ground of the post-stage isolation converter

[0018] Sec-GND: secondary side ground wire

[0019] Pri-GND: primary side ground wire

[0020] 11: first bridge arm

[0021] Q1: first switch

[0022] Q2: second switch

[0023] L1: inductance

[0024] 12: second bridge arm

[0025] Q3: third switch

[0026] Q4: fourth switch

[0027] HB: second node

[0028] 13: control unit

[0029] VAC: AC power supply

[0030] Vbus: output voltage

[0031] Vin: input voltage

[0032] Iin: input current

[0033] V Q3 : drive signal of third switch

[0034] V Q4 : drive signal of fourth switch

[0035] V HB : potential at second node

[0036] P1: first zero-crossing point

[0037] T1: first time period

[0038] T2: second time period

[0039] P2: second zero-crossing point

[0040] T3: third time period

[0041] T4: fourth time period

[0042] R D : resistance

[0043] R L : load DETAILED DESCRIPTION

[0044] The features and advantages of the present application will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is understood that various changes in the details can be made without departing from the scope of the present application, and that the description and drawings are to be regarded as illustrative only and not restrictive.

[0045] Figure 1 The working voltage measurement topology between the primary side and the secondary side ground of the post-stage isolation converter connected by the power factor correction converter is shown in the figure. Figure 1 The power factor correction converter 1 is connected to the post-stage isolation converter 2 through the bus capacitor C, as shown in the figure. The working voltage between the primary side and the secondary side ground of the post-stage isolation converter 2 requires short-circuiting the primary side N line, the PE line and the secondary side ground line Sec-GND for testing (the short-circuiting path is shown by arrows). Figure 2 The voltage between the primary side and the secondary side ground of the post-stage isolation converter 2 is shown in the figure. The working voltage between the primary side and the secondary side ground is equal to the effective value of the voltage VPS between the primary side and the secondary side ground, i.e. equal to Vbus / (√2). Generally, Vbus on the bus capacitor C is about 400V, so the working voltage between the primary side and the secondary side ground can be calculated to be about 283V. In medical applications, it is usually required to meet the IEC-60601 safety regulations. According to the IEC 60601-1 creepage distance and air distance requirements, when the working voltage between the primary side and the secondary side ground is greater than 250V, the communication optocoupler between the primary side and the secondary side ground of the post-stage isolation converter 2 needs to flash away a creepage distance of 12mm, and the conventional 8mm optocoupler cannot be used. This results in a larger volume and a higher price of the primary side and secondary side isolation devices of the post-stage isolation converter 2.

[0046] After analysis, the voltage between the primary side and the secondary side ground of the post-stage isolation converter 2 has a corresponding relationship with the slow bridge arm midpoint voltage of the power factor correction converter 1. In order to reduce the working voltage between the primary side and the secondary side ground of the post-stage isolation converter 2, the effective value of the slow bridge arm midpoint voltage of the power factor correction converter 1 can be reduced. Specifically, by controlling the proportion of the high-level potential on the slow bridge arm midpoint of the power factor correction converter 1 in each power frequency cycle to be less than a threshold value, the effective value of the slow bridge arm midpoint voltage of the power factor correction converter 1 can be reduced, thereby reducing the working voltage between the primary side and the secondary side ground of the post-stage isolation converter 2, for example, making the working voltage less than 250V.

[0047] Figure 3 The circuit structure schematic diagram of the power factor correction converter of the preferred embodiment of the present application is shown in the figure. Figure 3As shown, the power factor correction converter 1 comprises a first bridge arm 11, an inductor L1, a second bridge arm 12 and a control unit 13, and the power factor correction converter 1 is preferably a totem pole power factor correction converter. The first bridge arm 11 (i.e. fast bridge arm) comprises a first switch Q1 and a second switch Q2 connected in series with each other, wherein the first switch Q1 and the second switch Q2 are connected to a first node. Two ends of the inductor L1 are coupled to the first node and a first end of an AC power source VAC, respectively. The second bridge arm 12 (i.e. slow bridge arm) comprises a third switch Q3 and a fourth switch Q4 connected in series with each other, wherein the third switch Q3 and the fourth switch Q4 are connected to a second node HB coupled to a second end of the AC power source VAC. The first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 can be, for example but not limited to, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), GaN power tube or SiC power tube. The control unit 13 controls the ratio of the high level potential on the second node HB in each power frequency cycle to be less than a threshold value, wherein the threshold value is equal to (250 / Vbus) 2 , and Vbus is the output voltage of the power factor correction converter 1. In some embodiments, for example, the output voltage Vbus of the power factor correction converter 1 can be 400V, but the present application is not limited thereto. It should be noted that since the voltage between the primary side and the secondary side of the post-stage converter of the power factor correction converter 1 can be equivalent to the voltage on the second node HB, the post-stage converter is not shown in the figure, and the present application focuses on reducing the interval distance between the primary side and the secondary side of the post-stage converter by reducing the ratio of the high level potential on the second node HB. As known from the foregoing, the present application controls the ratio of the high level potential on the second node HB in each power frequency cycle to be less than a threshold value, thereby reducing the effective value of the voltage on the second node HB, and further reducing the operating voltage between the primary side and the secondary side, and shortening the interval distance between the primary side and the secondary side of the post-stage converter. In this way, the volume of the isolation communication optocoupler between the primary side and the secondary side can be reduced, and the cost can be reduced.

[0048] In some embodiments, the control unit 13 can be a digital controller or an analog chip controller, and the control unit 13 can be used to perform various detections, perform various control operations and provide switch driving signals, such as Figure 3As shown, for example, the control unit 13 can provide driving signals to the drivers of the respective switches to correspondingly control the operations of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4. In addition, the control unit 13 can perform input voltage detection, zero-crossing detection, limit frequency detection, inductor current detection and / or output voltage detection. The user can increase or decrease the functions of the control unit 13 as needed, and the functions of the control unit 13 are not limited to those listed.

[0049] The operating waveforms in the power factor correction converter 1 are shown in Figure 4 , where Vin represents the input voltage received by the power factor correction converter 1 from the AC power source VAC, Iin represents the input current of the power factor correction converter 1, V Q3 and V Q4 represent the driving signals of the third switch Q3 and the fourth switch Q4, respectively, and V HB represents the potential on the second node HB. The third switch Q3 is turned on during the negative half cycle of the AC power source VAC, and the fourth switch Q4 is turned on during the positive half cycle of the AC power source VAC. The input voltage Vin has a first zero-crossing point P1 when the polarity of the input voltage Vin changes from negative to positive. During a first time period T1 before the first zero-crossing point P1, the input current Iin is zero, and during a second time period T2 after the first zero-crossing point P1, the input current Iin is also zero. During the first time period T1 and the second time period T2, the third switch Q3 and the fourth switch Q4 are both turned off. The input voltage Vin has a second zero-crossing point P2 when the polarity of the input voltage Vin changes from positive to negative. During a third time period T3 before the second zero-crossing point P2, the input current Iin is zero, and during a fourth time period T4 after the second zero-crossing point P2, the input current Iin is also zero. During the third time period T3 and the fourth time period T4, the third switch Q3 and the fourth switch Q4 are both turned off. In some embodiments, the durations of the first time period T1, the second time period T2, the third time period T3 and the fourth time period T4 can range from, for example but not limited to, 0.7-1.8 ms.

[0050] As shown in Figure 4 , the ratio of the high-level potential on the second node HB is about 0.5. In order to reduce the operating voltage between the primary side and the secondary side of the subsequent-stage isolation converter, the control unit 13 can control the ratio of the high-level potential on the second node HB to be less than a threshold value in each operating cycle, so as to reduce the ratio of the high-level voltage on the second node HB, and thus reduce the operating voltage between the primary side and the secondary side of the subsequent-stage isolation converter. The following is an example illustrating various possible control methods.

[0051] In some embodiments, as shown in Figure 5 , the control unit 13 controls the fourth switch Q4 to be turned on for a preset duration at the beginning of the first time period T1. Since the potential V HBThe high level potential on the second node HB can be reduced by lowering the on time of the fourth switch Q4. The preset time period is shorter than the first time period T1. The preset time period for the fourth switch Q4 to be on is very short, and a short driving pulse can lower the potential on the second node HB. In some embodiments, the preset time period can be 10-50us, which is not limited in the present application. In some embodiments, as shown in Figure 6 The control unit 13 also controls the fourth switch Q4 to be on in the second time period T2 to reduce the proportion of the high level potential on the second node HB.

[0052] In some embodiments, as shown in Figure 7 The control unit 13 increases the fourth time period T4, and the potential VHB on the second node HB rises to the high level at the end of the fourth time period T4. The control unit 13 can reduce the proportion of the high level potential on the second node HB by controlling the fourth time period T4 to be increased, i.e. delaying the turn-on time of the third switch Q3. HB The control unit 13 can reduce the proportion of the high level potential on the second node HB by controlling the fourth time period T4 to be increased, i.e. delaying the turn-on time of the third switch Q3.

[0053] In addition to the above control method, in some embodiments, as shown in Figure 8 The proportion of the high level potential on the second node HB can be reduced by connecting a resistor R4 in parallel to the fourth switch Q4. Specifically, by connecting the resistor R4 in parallel to the fourth switch Q4, the discharging speed on the second node HB (i.e. the transition speed of the potential VHB on the second node HB from the high level to the low level) can be accelerated after the third switch Q3 is turned off, thereby reducing the proportion of the high level potential on the second node HB. D The proportion of the high level potential on the second node HB can be reduced by connecting a resistor R4 in parallel to the fourth switch Q4. Specifically, by connecting the resistor R4 in parallel to the fourth switch Q4, the discharging speed on the second node HB (i.e. the transition speed of the potential VHB on the second node HB from the high level to the low level) can be accelerated after the third switch Q3 is turned off, thereby reducing the proportion of the high level potential on the second node HB. D The proportion of the high level potential on the second node HB can be reduced by connecting a resistor R4 in parallel to the fourth switch Q4. Specifically, by connecting the resistor R4 in parallel to the fourth switch Q4, the discharging speed on the second node HB (i.e. the transition speed of the potential VHB on the second node HB from the high level to the low level) can be accelerated after the third switch Q3 is turned off, thereby reducing the proportion of the high level potential on the second node HB. HB The proportion of the high level potential on the second node HB can be reduced by connecting a resistor R4 in parallel to the fourth switch Q4. Specifically, by connecting the resistor R4 in parallel to the fourth switch Q4, the discharging speed on the second node HB (i.e. the transition speed of the potential VHB on the second node HB from the high level to the low level) can be accelerated after the third switch Q3 is turned off, thereby reducing the proportion of the high level potential on the second node HB.

[0054] In summary, the present application provides a power factor correction converter and a control method thereof, which controls the proportion of the high level potential on the slow bridge arm midpoint to be less than a threshold value in each power frequency cycle, thereby reducing the primary and secondary side ground working voltage of the subsequent converter of the power factor correction converter, and further shortening the interval distance between the primary and secondary sides of the subsequent converter. In this way, the volume of the isolation communication optocoupler between the primary and secondary sides can be reduced, and the cost can be reduced.

[0055] It should be noted that the above is only a preferred embodiment proposed for illustrating the present application, and the present application is not limited to the embodiment described above, and the scope of the present application is determined by the appended claims. The present application can be modified by those skilled in the art, but all modifications shall not deviate from the protection scope of the appended claims.

Claims

1. A power factor correction converter characterized by, Comprising: a first bridge arm comprising a first switch and a second switch connected in series with each other, wherein a first node is between the first switch and the second switch; an inductor, wherein two ends of the inductor are coupled to the first node and a first end of an AC power source, respectively; a second bridge arm comprising a third switch and a fourth switch connected in series with each other, wherein a second node is between the third switch and the fourth switch, and the second node is coupled to a second end of the AC power source; and wherein the output voltage of the power factor correction converter is greater than 250 V. a control unit configured to control a ratio of a high level potential on the second node in each power frequency cycle to be less than a threshold value, wherein the threshold value is equal to (250 / Vbus) 2 , and Vbus is an output voltage of the power factor correction converter. The power factor correction converter receives an input voltage from the AC power source, the input voltage has a first zero-crossing point when the input voltage changes from negative polarity to positive polarity, and the input current of the power factor correction converter is zero in a first time period and a second time period before and after the first zero-crossing point, respectively.

2. The power factor correction converter of claim 1, wherein, The control unit controls the fourth switch to be turned on for a preset time length at the beginning of the first time period, so as to reduce the proportion of high level potential on the second node, wherein the preset time length is shorter than the first time period.

3. The power factor correction converter of claim 2, wherein, The control unit controls the fourth switch to be in a turned-on state in the second time period, so as to reduce the proportion of high level potential on the second node.

4. The power factor correction converter of claim 3, wherein, The first time period and the second time period range from 0.7 ms to 1.8 ms.

5. The power factor correction converter of claim 2, wherein, The power factor correction converter receives an input voltage from the AC power source, the input voltage has a second zero-crossing point when the input voltage changes from positive polarity to negative polarity, and the input current of the power factor correction converter is zero in a third time period and a fourth time period before and after the second zero-crossing point, respectively.

6. The power factor correction converter of claim 1, wherein, The control unit reduces the proportion of high level potential on the second node by controlling the fourth time period to increase.

7. The power factor correction converter of claim 6, wherein, The third time period and the fourth time period range from 0.7 ms to 1.8 ms.

8. The power factor correction converter of claim 6, wherein, Further comprising a resistance, wherein the resistance is connected in parallel to both ends of the fourth switch, and the resistance is configured to reduce the proportion of high level potential on the second node.

9. The power factor correction converter of claim 1, wherein, The first switch, the second switch, the third switch and the fourth switch are IGBT, MOSFET, GaN power tube or SiC power tube.

10. The power factor correction converter of claim 1, wherein, The output voltage of the power factor correction converter is 400 V.

11. The power factor correction converter of claim 1, wherein, The power factor correction converter comprises a first bridge arm, a second bridge arm and an inductor, the first bridge arm comprises a first switch and a second switch connected in series with each other, wherein a first node is between the first switch and the second switch; two ends of the inductor are coupled to the first node and a first end of an AC power source, respectively; the second bridge arm comprises a third switch and a fourth switch connected in series with each other, wherein a second node is between the third switch and the fourth switch, and the second node is coupled to a second end of the AC power source, and the control method comprises:

12. A control method suitable for a power factor correction converter, characterized in that, wherein the output voltage of the power factor correction converter is greater than 250 V. controlling a ratio of the high level potential on the second node in each power frequency switching cycle to be less than a threshold, wherein the threshold is equal to (250 / Vbus) 2 , Vbus being an output voltage of the power factor correction converter; The power factor correction converter receives an input voltage from the AC power source, the input voltage has a first zero-crossing point when the input voltage changes from negative polarity to positive polarity, and the input current of the power factor correction converter is zero in a first time period and a second time period before and after the first zero-crossing point, respectively.

13. The control method according to claim 12, characterized by, ​ 14. The control method according to claim 13, characterized by, The method further includes a sub-step of controlling the fourth switch to be turned on for a preset time period at the beginning of the first time period to reduce the proportion of high-level potential on the second node, wherein the preset time period is shorter than the first time period.

15. The control method according to claim 14, characterized by, The method further includes a sub-step of controlling the fourth switch to be turned on during the second time period to reduce the proportion of high-level potential on the second node.

16. The control method according to claim 12, characterized by The power factor correction converter receives an input voltage from the AC power source, the input voltage has a second zero-crossing point when the input voltage changes from positive polarity to negative polarity, and the input current of the power factor correction converter is zero during a third time period and a fourth time period before and after the second zero-crossing point respectively.

17. The control method of claim 16, wherein The method further includes a sub-step of increasing the fourth time period to reduce the proportion of high-level potential on the second node.

18. The control method according to claim 12, wherein The output voltage of the power factor correction converter is 400V.

19. The control method according to claim 12, wherein The method further includes a sub-step of connecting a resistor in parallel to both ends of the fourth switch.

Images