Semiconductor structure, method of manufacturing the same, MEMS device, and electronic device

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof, a MEMS device and an electronic device. The semiconductor structure comprises: a first substrate with a first defined surface; a second substrate with a second defined surface, the first defined surface and the second defined surface being opposite to each other; a metal sealing ring structure arranged between the first defined surface and the second defined surface, the sealing ring structure, the first defined surface and the second defined surface defining a containing space; and a MEMS device, the containing space being suitable for containing the MEMS device, the MEMS device comprising an input end, an output end and at least one ground end, wherein: one end of the ground end, the input end and the output end is an electrically connected end electrically connected with the sealing ring structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and more particularly to a semiconductor structure and its manufacturing method, a MEMS device, and an electronic device. Background Technology

[0002] With the rapid development of 5G communication technology, the requirements for communication frequency bands are becoming increasingly stringent. Traditional radio frequency filters, limited by their structure and performance, cannot meet the requirements of high-frequency communication. Thin-film bulk acoustic resonators (FBARs), as a novel MEMS device, have advantages such as small size, light weight, low insertion loss, wide bandwidth, and high quality factor, making them well-suited for the upgrading of wireless communication systems and making FBAR technology one of the research hotspots in the field of communication.

[0003] FBARs or FBAR filters require good sealing to prevent corrosion from external environmental moisture, otherwise it will lead to frequency shift and performance degradation.

[0004] Figure 1 This is a schematic diagram of an exemplary filter topology. Figure 1 The diagram shows the input terminal (IN), the output terminal (OUT), and the ground terminals (G1, G2, and G3).

[0005] In existing acoustic wave filters, since the packaging substrate and the functional substrate used to make the resonator need to be sealed and packaged through a wafer-level semiconductor structure, vias and interconnects are required to bring out the PADs or conductive blocks on the functional substrate to the packaging substrate.

[0006] Figure 2a The diagram illustrates the arrangement of PADs on a functional substrate in the prior art, showing PADs IN, OUT, G1, G2, and G3. Figure 2a In the middle, the outermost ring is the sealing ring M used for gold-to-gold bonding. Figure 2a In the middle, a resonator can be placed in the area inside the sealing ring M, excluding the PAD. Figure 2a The resonator is not shown or marked in the diagram.

[0007] Figure 2b The corresponding arrangement of PADs IN, OUT, G1, G2, and G3 on the existing packaging substrate. Figure 2a Each PAD of the functional substrate is connected to the top of the package substrate through a central conductive part. Figure 2b This is a top view of the packaging substrate.

[0008] However, vias or conductive parts D1 and wiring introduce a large parasitic inductance (typically around 0.1nH). The increase in parasitic inductance will worsen the filter's roll-off, and the transmission zero at high frequencies will shift to lower frequencies, thus significantly worsening high-frequency suppression. In addition, in some cases, parasitic inductance will also worsen the matching, i.e., return loss.

[0009] Figure 3a This is a top-view diagram of the IN, OUT, G1, G2, and G3 pads on the functional base. Figure 3b This is a top view of the IN, OUT, G1, G2, and G3 pads on the package substrate. Figure 3a In the middle, the outermost ring is the sealing ring M used for gold-to-gold bonding. Figure 3a In the middle, a resonator can be placed in the area inside the sealing ring M, excluding the PAD. Figure 3a The resonator is not shown or marked in the diagram.

[0010] like Figure 3a and Figure 3b As shown, relative to Figure 2a and Figure 2b The proposed solution, in Figure 3a and Figure 3b The number of vias or conductive parts D1 is increased by increasing the number of PADs on the two substrates, thereby reducing parasitic inductance. However, since the PAD area is large, a lot of area is wasted, increasing the chip cost.

[0011] Figure 4a The diagram illustrates the arrangement of PADs on a functional base in existing technology, showing PADs IN, OUT, G1, G2, and G3. Figure 4a In the middle, the outermost ring can be a sealing ring M for gold-to-gold bonding. Figure 4a In the middle, a resonator can be placed in the area outside the PAD within the sealing ring. Figure 4a The resonator is not marked or shown in the diagram.

[0012] Figure 4b This diagram illustrates the arrangement of PADs on a package substrate using existing technology, showing PADs IN, OUT, G1, G2, and G3. Figure 4b The indicator shows the conductive part D1 located in these PADs.

[0013] As can be seen, with Figure 3a and Figure 3b compared to, Figure 4a and Figure 4b The number of PADs was not increased.

[0014] In addition, such as Figure 4b As shown, along Figure 4aThe sealing ring on the functional substrate is positioned by multiple spaced blocks 60 on the packaging substrate, and each block 60 has a through hole or conductive part D2. The conductive part D2 and the sealing ring are positioned by multiple spaced blocks 60 on the packaging substrate. Figure 4a The sealing ring M on the functional substrate forms an electrical connection.

[0015] Figure 4a and Figure 4b The plan and Figure 3a and Figure 3b The difference also lies in, such as Figure 3b As shown, such a block 60 does not exist on the packaging substrate.

[0016] However, similar to Figure 2a and Figure 2b The scheme shown, in Figure 4a and Figure 4b In the scheme shown, the via or conductive part D1 and the connection will introduce parasitic inductance. The increase of parasitic inductance will worsen the roll-off of the filter. At the same time, the transmission zero at high frequency will shift to low frequency, thus worsening the high frequency suppression. In addition, in some cases, parasitic inductance will also worsen the matching, that is, the return loss. Summary of the Invention

[0017] The present invention is proposed to alleviate or solve at least one of the above-mentioned problems in the prior art.

[0018] According to one aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising:

[0019] A first substrate, the first substrate having a first defining surface and a first non-defining surface opposite the first defining surface in the thickness direction of the substrate;

[0020] The second substrate has a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and the first defining surface and the second defining surface are opposite to each other;

[0021] A metal sealing ring structure is disposed between a first limiting surface and a second limiting surface, and the sealing ring structure, the first limiting surface and the second limiting surface define an accommodating space;

[0022] The space is adapted to accommodate the MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal.

[0023] in:

[0024] One of the grounding terminal, input terminal, and output terminal is an electrical connection terminal that is electrically connected to the sealing ring structure.

[0025] Embodiments of the present invention also relate to a method for manufacturing a semiconductor structure, comprising the steps of:

[0026] A second substrate is provided, the second substrate having a first defining surface and a first non-defining surface opposite to the first defining surface in the thickness direction of the substrate, and a first metal sealing layer is disposed on the first defining surface;

[0027] A second substrate is provided, the second substrate having a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and a second metal sealing layer is disposed on the second defining surface;

[0028] A first metal sealing layer and a second metal sealing layer are joined together opposite to each other to form a sealing ring structure. The sealing ring structure, the first defining surface, and the second defining surface define a receiving space. The receiving space is suitable for accommodating a MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal.

[0029] The method further includes the following steps:

[0030] This allows one of the grounding terminal, input terminal, and output terminal to be electrically connected to the sealing ring structure, whereby the one terminal is the electrical connection terminal.

[0031] Embodiments of the present invention also relate to a MEMS device comprising the semiconductor structure described above.

[0032] Embodiments of the present invention also relate to an electronic device, including the semiconductor structure or MEMS device described above. Attached Figure Description

[0033] The following description and accompanying drawings will better aid in understanding these and other features and advantages of the various embodiments disclosed herein, wherein the same reference numerals in the drawings always denote the same parts, wherein:

[0034] Figure 1 A schematic diagram of an exemplary filter topology;

[0035] Figure 2a An example of a prior art filter is shown, illustrating the arrangement of PADs IN, OUT, G1, G2, and G3 on a functional base.

[0036] Figure 2b An example is shown with Figure 2a Correspondingly, in existing technologies, the filters are arranged with PADs IN, OUT, G1, G2, and G3 on the packaging substrate;

[0037] Figure 3a An example of a prior art filter is shown, illustrating the arrangement of PADs IN, OUT, G1, G2, and G3 on a functional base.

[0038] Figure 3b An example is shown with Figure 3aCorrespondingly, existing filters have the following arrangement of PADs (IN, OUT, G1, G2, G3) on the packaging substrate;

[0039] Figure 4a An example of a prior art filter is shown, illustrating the arrangement of PADs IN, OUT, G1, G2, and G3 on a functional base.

[0040] Figure 4b An example is shown with Figure 4a The corresponding existing technology filters have the following arrangement of PADs (IN, OUT, G1, G2, G3) on the packaging substrate;

[0041] Figure 5a This is a top view schematic diagram of the functional substrate of a MEMS device according to an exemplary embodiment of the present invention, wherein a ground terminal is electrically connected to a sealing ring;

[0042] Figure 5b for Figure 5a The diagram shows a top view of the packaging substrate of the corresponding MEMS device, where a ground terminal G1 on the packaging substrate is electrically connected to the conductive part D2 in multiple blocks.

[0043] Figure 6 An example is shown, illustrating the passband comparison of the filter, where the solid lines correspond to the passbands based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure shows the change in channel insertion loss after reducing the ground inductance;

[0044] Figure 7 An example is shown in the filter roll-off comparison graph, where the solid line corresponds to the roll-off based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure shows the change in roll-off after the ground inductance is reduced;

[0045] Figure 8 An example is shown, illustrating a comparison of high-frequency suppression of the filter, where the solid line corresponds to the high-frequency suppression based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure shows the change in high-frequency suppression after the ground inductance is reduced;

[0046] Figure 9 This is a top view of a packaging substrate for a MEMS device according to yet another exemplary embodiment of the present invention, wherein a plurality of conductive portions D2 are electrically connected to the input terminal IN;

[0047] Figure 10 An example is shown in the filter return loss comparison graph, where the solid line corresponds to the return loss based on... Figure 9 The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure is shown, illustrating the change in return loss after reducing the input inductance;

[0048] Figure 11a This is a top view schematic diagram of the functional substrate of a MEMS device according to an exemplary embodiment of the present invention, wherein a ground terminal is electrically connected to a sealing ring, and it is connected to... Figure 5a same;

[0049] Figure 11b for Figure 11a The diagram shows a top view of the packaging substrate of the corresponding MEMS device, where a ground terminal G1 on the packaging substrate is electrically connected to a conductive part D2 in multiple blocks, and the number of conductive parts near the input terminal IN, the ground terminal G3 and the output terminal OUT is less than the number of conductive parts near the ground terminal G1.

[0050] Figure 12 An example is shown illustrating the frequency-insertion loss curves of the filter's high-frequency zero-point shift before and after the introduction of a metal seal, where the solid line corresponds to the case without a metal seal, and the dashed line corresponds to the case based on... Figure 4a and Figure 4b If a metal sealing ring has already been installed;

[0051] Figure 13 An exemplary frequency-insertion loss plot of a filter with a metal sealing ring is shown, where the dashed line corresponds to the frequency-insertion loss plot of the filter with a metal sealing ring. Figure 11a and Figure 11b The layout structure, with solid lines corresponding to the arrangement structure. Figure 4a and Figure 4b The layout structure;

[0052] Figure 14 For an exemplary embodiment of the present invention, along Figure 5b A schematic diagram of the cross-section of line B-B' in the diagram;

[0053] Figure 15 For an exemplary embodiment of the present invention, along Figure 5b A schematic diagram of the cross-section of line C-C' in the diagram;

[0054] Figure 16 For another exemplary embodiment of the invention, similar to along Figure 5b A schematic diagram of the cross-section of line C-C' in the diagram;

[0055] Figure 17 For example Figure 5aA cross-sectional schematic diagram of the sealing effect of the sealing ring in the middle. Detailed Implementation

[0056] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof. These are only some embodiments of the invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0057] exist Figure 1 In the topology diagram of the filter, the filter includes series resonators and parallel resonators, as well as corresponding matching inductors. The inductances and matching at the IN and OUT ports are related to return loss. In some cases, a smaller inductance results in better matching, but in others, specific inductance values ​​are required. The inductances at ports G1, G2, and G3 are related to high-frequency suppression; a smaller inductance results in better high-frequency suppression. All the aforementioned inductors are related to roll-off. The IN and OUT inductors determine the roll-off on the right side of the filter's passband, while G1, G2, and G3 determine the roll-off on the left side of the passband. Smaller inductances result in better roll-off.

[0058] The above is only based on Figure 1 The exemplary illustration of the topology is provided below; as those skilled in the art will understand, similar understandings may apply to filters with different topologies. Generally speaking, a smaller matching inductance is desirable.

[0059] The following is a reference to the appendix. Figures 5a-17 The technical solution of the present invention is illustrated by example.

[0060] Figure 5a This is a top view schematic diagram of the functional substrate of a MEMS device according to an exemplary embodiment of the present invention.

[0061] Figure 5a The text shows the pads IN, OUT, G1, G2, and G3, and in... Figure 5a In the middle, the outermost ring can be a sealing ring M for gold-to-gold bonding. Figure 5a In the middle, a resonator can be placed in the area outside the PAD within the sealing ring. Figure 5a The resonator is not marked or shown in the diagram.

[0062] Figure 5a In this configuration, one grounding terminal G1 is electrically connected to the sealing ring M. For example... Figure 5a As shown, PADs IN, OUT, G1, G2, and G3 are provided with through holes or conductive parts D1.

[0063] Figure 5b for Figure 5a A top view of the packaging mechanism of the corresponding MEMS device. Figure 5b The diagram shows the pads IN, OUT, G1, G2, and G3. Figure 5b The indicator shows the conductive part D1 located in these PADs.

[0064] like Figure 5b As shown, along Figure 5a The sealing ring on the functional substrate is positioned by multiple spaced blocks 60 on the packaging substrate, and each block 60 has a through hole or conductive part D2. The conductive part D2 and the sealing ring are positioned by multiple spaced blocks 60 on the packaging substrate. Figure 5a The sealing ring M on the functional substrate forms an electrical connection.

[0065] like Figure 5b As shown, a ground terminal G1 on the package substrate is electrically connected to the conductive part D2 in multiple blocks 60.

[0066] Figure 5a and Figure 5b The arrangement shown is the same as Figure 4a as well as Figure 4b The difference in the arrangement shown is that: Figure 4a and Figure 4b In the process, the input, output, and ground terminals of the MEMS device (e.g., a filter) are not electrically connected to the conductive portion D2 in block 60 on the package substrate; while Figure 5a and Figure 5b In the middle, the input terminal or the ground terminal (in Figure 5b Specifically, the grounding terminal G1) is electrically connected to the conductive part D2.

[0067] like Figure 1 As shown, ground terminal G1 is the ground terminal that is electricalally closest to the input terminal IN. Figure 5b As can be seen, the grounding terminal G1 is electrically connected to three conductive parts D2 simultaneously. It should be noted that the grounding terminal G1 may be electrically connected to only one conductive part D2, two conductive parts D2, or more than three conductive parts D2.

[0068] It is obvious that since the grounding terminal G1 is electrically connected to all three conductive parts D2, and the conductive parts D2 are also electrically connected to the sealing ring M on the functional substrate, this will reduce the ground inductance at the grounding terminal G1.

[0069] Figure 6 An example is shown, illustrating the passband comparison of the filter, where the solid lines correspond to the passbands based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure shows the change in channel insertion loss after reducing the inductance to ground. Figure 7 An example is shown in the filter roll-off comparison graph, where the solid line corresponds to the roll-off based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure illustrates the change in roll-off after the ground inductance is reduced. From Figure 6 and 7 It can be seen that, in adopting Figure 5a and Figure 5b With this arrangement, the ground inductance is reduced, and the passband insertion loss remains almost unchanged, but the corresponding roll-off is improved by at least 1MHz.

[0070] Figure 8 An example is shown, illustrating a comparison of high-frequency suppression of the filter, where the solid line corresponds to the high-frequency suppression based on... Figure 5a and Figure 5b The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure illustrates the change in high-frequency suppression after reducing the ground inductance. From Figure 8 It can be seen that in adopting Figure 5a and Figure 5b The arrangement of the circuitry reduces ground inductance, resulting in a significant improvement in high-frequency suppression beyond 5.2 GHz.

[0071] Figure 9 This is a top view schematic diagram of the packaging substrate of a MEMS device according to yet another exemplary embodiment of the present invention, wherein multiple conductive portions are electrically connected to the input terminal IN. Figure 9 In the middle, multiple conductive parts D2 are electrically connected to the input terminal IN. Figure 9 As can be seen, the input terminal IN is electrically connected to three conductive parts D2 simultaneously. It should be noted that the input terminal IN can be electrically connected to only one conductive part D2, two conductive parts D2, or more than three conductive parts D2.

[0072] Clearly, since the input terminal IN is electrically connected to all three conducting parts D2 simultaneously, this reduces the ground inductance at the ground terminal G1.

[0073] Figure 10 An example is shown in the filter return loss comparison graph, where the solid line corresponds to the return loss based on... Figure 9 The layout structure, with dashed lines corresponding to the layout based on... Figure 4a and Figure 4b The arrangement structure illustrates the change in return loss as the input inductance is reduced. From... Figure 10It can be seen that reducing the input inductance improves the echo. However, in some cases, a smaller input inductance does not necessarily lead to better echo; this depends on the specific frequency band and design specifications. Nevertheless, this method can be effective for situations requiring the smallest possible inductance.

[0074] Figure 11a This is a top view schematic diagram of the functional substrate of a MEMS device according to an exemplary embodiment of the present invention, wherein a ground terminal is electrically connected to a sealing ring, and it is connected to... Figure 5a same. Figure 11b for Figure 11a The diagram shows a top view of the packaging substrate of the corresponding MEMS device, where a ground terminal G1 on the packaging substrate is electrically connected to a conductive part D2 in multiple blocks, and the number of conductive parts near the input terminal IN, the ground terminal G3 and the output terminal OUT is less than the number of conductive parts near the ground terminal G1.

[0075] Figure 12 An example is shown illustrating the frequency-insertion loss curves of the filter's high-frequency zero-point shift before and after the introduction of a metal seal, where the solid line corresponds to the case without a metal seal, and the dashed line corresponds to the case based on... Figure 4a and Figure 4b The case where a metal seal ring has already been installed. From... Figure 12 It can be seen that adding metal sealing rings introduces coupling between the various PADs. This coupling causes the high-frequency zero point to shift to a lower frequency, thus worsening high-frequency suppression. Figure 12 As shown. In Figure 12 In the diagram, the dashed line represents the curve shifted towards lower frequencies. There's a need for suppression in the 5G-6G range, so the suppression in this segment needs to be as good as possible.

[0076] For example, corresponding to Figure 1 In the diagram, the input terminal IN, the output terminal OUT, and the ground terminal G3 are relatively sensitive nodes. Coupling can be reduced by decreasing the sealing ring blocks 60 and the through holes or conductive parts D2 around the PADs at these nodes. Since the ground terminal G1 is a non-sensitive port, some of the sealing ring blocks and conductive parts can be connected to the ground terminal G1. Figure 11a and Figure 11b Such an embodiment is shown in the figure.

[0077] Figure 11a This is a top view schematic diagram of the functional substrate of a MEMS device according to an exemplary embodiment of the present invention, wherein a ground terminal is electrically connected to a sealing ring, and it is connected to... Figure 5a same. Figure 11b for Figure 11aThe diagram shows a top view of the packaging substrate of the corresponding MEMS device, in which a ground terminal G1 on the packaging substrate is electrically connected to the conductive parts D2 in multiple blocks 60, and the number of conductive parts D2 near the input terminal IN, the ground terminal G3 and the output terminal OUT is less than the number of conductive parts D2 near the ground terminal G1.

[0078] exist Figure 11a and Figure 11b In the middle, block 60 and the conducting part D2 can be flexibly set to reduce the impact of adverse coupling on the filter performance.

[0079] Figure 13 An exemplary frequency-insertion loss plot of a filter with a metal sealing ring is shown, where the dashed line corresponds to the frequency-insertion loss plot of the filter with a metal sealing ring. Figure 11a and Figure 11b The layout structure, with solid lines corresponding to the arrangement structure. Figure 4a and Figure 4b The arrangement structure shows that, in the 5G-6G frequency band, the shift of high-frequency null points to low frequencies is suppressed.

[0080] The following reference Figure 14-17 An example is provided to illustrate a semiconductor structure. Figure 14 For an exemplary embodiment of the present invention, along Figure 5b A cross-sectional diagram of line B-B' in the diagram. Figure 15 For an exemplary embodiment of the present invention, along Figure 5b A cross-sectional diagram of line C-C' in the diagram. Figure 16 For another exemplary embodiment of the invention, similar to along Figure 5b A cross-sectional diagram of line C-C' in the diagram. Figure 17 For example Figure 5a A cross-sectional schematic diagram of the sealing effect of the sealing ring in the middle.

[0081] exist Figure 14-17 The reference numerals in the accompanying drawings of this invention are explained as follows:

[0082] 10: Functional substrate, with optional materials including single-crystal silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond, etc. In this embodiment, the substrate on which MEMS devices, such as FBARs, are disposed is a functional substrate.

[0083] 20: Packaging substrate, with optional materials including single-crystal silicon, gallium nitride, gallium arsenide, sapphire, quartz, silicon carbide, diamond, etc. The packaging substrate provides the packaging function.

[0084] 101: An acoustic mirror, which can be a cavity, a Bragg reflector layer, or other equivalent forms. In the embodiment shown in this invention, it is disposed inside the substrate; in an optional embodiment, the cavity can also be located on the upper surface of the substrate.

[0085] 102: Bottom electrode, materials can be selected from: molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.

[0086] 103: The piezoelectric layer can be a single-crystal piezoelectric material, such as single-crystal aluminum nitride, single-crystal gallium nitride, single-crystal lithium niobate, single-crystal lead zirconate titanate (PZT), single-crystal potassium niobate, single-crystal quartz film, or single-crystal lithium tantalate, etc. It can also be a polycrystalline piezoelectric material (as opposed to single-crystal, a non-single-crystal material), such as polycrystalline aluminum nitride, zinc oxide, PZT, etc. It can also be a rare earth element doped with a certain atomic ratio of the above materials. Mixed materials, such as doped aluminum nitride, contain at least one rare earth element, such as scandium (Sc), yttrium (Y), magnesium (Mg), titanium (Ti), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0087] 104: Top electrode. Materials can include molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or composites or alloys of these metals. The top and bottom electrodes are generally made of the same material, but they can also be different.

[0088] 30A, 30B: Metal sealing layer or metal bonding layer, the materials can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.

[0089] 30: Metal sealing ring.

[0090] 40, 401, 402: Recessed areas filled with metal, the same metal as the metal-filled areas.

[0091] 50: Through hole, which is filled with metal. The filling metal can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or their alloys.

[0092] 60: Pads or conductive blocks or PADs, the materials of which include but are not limited to metal fillers, and other materials may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.

[0093] In this invention, an annular space (including, for example, recesses 401 and / or 402) is provided in the sealing ring 30 region, and this annular space is filled with filler metal to enhance the sealing performance of the FBAR. The filler metal may be the same as or different from the material of the metal bonding layer. The filler metal may be formed by electroplating or other deposition processes.

[0094] It should be noted that in this invention, an FBAR filter is used as an example of a MEMS device to illustrate the semiconductor structure, but the MEMS device of this invention is not limited to an FBAR filter, and can also be any other MEMS structure.

[0095] like Figure 14-15 As shown, an FBAR filter (shown as FBAR in the figure) is disposed on the lower substrate 10. The lower substrate is the functional substrate, and the upper substrate 20 is the packaging substrate. Figure 14-15 As shown, a conductive portion 102A is disposed on the upper surface of the lower substrate 10 in the same layer as the bottom electrode 102, and a recessed portion 40 is disposed in the conductive portion. Due to the presence of the recessed portion 40, when the metal sealing layer 30A is disposed on the upper surface of the lower substrate 10, a portion of the lower side of the metal sealing layer 30A falls into the recessed portion 40 to form a protrusion, and a corresponding recessed portion 401 is formed on the upper side (at the joint surface) of the metal sealing layer 30A based on shape conduction.

[0096] like Figure 15 As shown, the sealing ring is only provided in the recess 401; in other words, the sealing ring only has a portion extending into the metal sealing layer 30A. The sealing ring is formed after the annular space is filled with metal.

[0097] like Figure 14 As shown, a channel 50 is also provided to form a sealing ring, extending along the thickness direction of the encapsulation substrate. Figure 14 In the illustrated embodiment, the lower end of channel 50 communicates with or connects to the annular space, and channel 50 extends through the entire metal sealing layer 30B and substrate 20, opening onto the upper surface of substrate 20. Thus, a sealing ring can be formed subsequently by deposition or electroplating, allowing filler to flow into the annular space through channel 50. As will be understood, the lower end of channel 50 can be as follows: Figure 14 The filling metal is completely aligned with the recessed portion 401, but partial alignment is also acceptable, as long as the filling metal can flow into the annular space to form a sealing ring.

[0098] like Figure 14 As shown, the pad 60 is connected to the upper end of the fill metal in channel 50. Therefore, the fill metal in channel 50 can be formed together with the external leads of the FBAR filter during subsequent fabrication, without the need for additional special process steps.

[0099] like Figure 14-15 As shown, due to the presence of the recess 401, the sealing ring is embedded in the metal sealing layer 30A. The sealing ring has a portion that is lower than the mating surface or bonding interface of the metal sealing layer 30A, thereby achieving a sealing effect against moisture. Figure 17 It also demonstrates its effectiveness in blocking water vapor.

[0100] As can be understood, when the annular space is filled through channel 50, channel 50 and the metal within the annular space form a single structure.

[0101] exist Figure 14-15 In the conductive part 102A, a recess 40 is provided, while the upper surface of the substrate 10 does not have a recess. However, the present invention is not limited to this; other methods can be used to form a recess at the joint surface of the metal sealing layer.

[0102] For example, a base recess can be provided on the upper surface of the base 10 first, and then, when the conductive part 102A is formed, the conductive part 102A is recessed to form the conductive part recess 40.

[0103] Alternatively, the recess 401 may not be formed on the conductive part 102A, but is formed directly in the metal sealing layer 30A instead of through shape conduction.

[0104] The sealing ring can also extend vertically into the metal sealing layer, such as... Figure 16 As shown. Figure 16 Examples and Figure 14-15 The difference between the examples shown is that in the former, a recess 402 is provided in the metal sealing layer 30B and a recess 401 is provided in the metal sealing layer 30A, while in the latter, a recess 401 is provided only in the metal sealing layer 30A.

[0105] Due to the presence of recesses 401 and 402, the sealing ring is embedded in the corresponding metal sealing layer. Relative to the corresponding metal sealing layer, the sealing ring has a portion lower than the mating surface or bonding interface, thereby sealing against moisture.

[0106] In the previous embodiments, the channel 50 opens into the substrate 20 (or the encapsulation substrate 20), but the present invention is not limited thereto, and the channel 50 may also open into the substrate 10.

[0107] It should be noted that the conductive part can be electrically connected not only to the ground terminal or the input terminal, but also to the output terminal. That is, any one of the input terminal, output terminal, and ground terminal can be an electrical connection part that is electrically connected to the conductive part.

[0108] In this invention, "upper" and "lower" are relative to the bottom surface of the functional substrate of the semiconductor structure. For a component, the side closer to the bottom surface is the lower side, and the side farther from the bottom surface is the upper side.

[0109] In this invention, "inner" and "outer" are relative to the MEMS device located within the accommodating space in the lateral or radial direction. The side or end of a component closer to the MEMS device is called the inner side or inner end, while the side or end of the component farther from the MEMS device is called the outer side or outer end. For a reference position, being inside the position means being between the position and the MEMS device in the lateral or radial direction, while being outside the position means being farther away from the MEMS device in the lateral or radial direction.

[0110] In this invention, by utilizing the aforementioned metal sealing ring structure and the distribution of through holes or conductive portions at specific locations, one of the terminals of a MEMS device—for example, the ground terminal, the input terminal, and the output terminal—is electrically connected to the sealing ring structure. This reduces parasitic inductance at specific locations, thereby improving roll-off, matching, and high-frequency suppression. See, for example, [link to relevant documentation]. Figure 5a , Figure 5b and Figure 9 Since the metal sealing ring structure and the corresponding through holes or conductive parts around the filter can form unfavorable coupling between different locations on the filter, causing the transmission zero of the filter to shift to lower frequencies, adopting an arrangement structure such as that shown in Figure 11 helps to improve coupling.

[0111] Accordingly, the present invention also proposes a method to reduce parasitic inductance, namely, to make one of the ground terminal, input terminal and output terminal of a MEMS device electrically connected to the sealing ring structure.

[0112] As will be understood by those skilled in the art, bulk acoustic resonators can be used to form filters or other semiconductor devices.

[0113] Based on the above, the present invention proposes the following technical solution:

[0114] 1. A semiconductor structure, comprising:

[0115] A first substrate, the first substrate having a first defining surface and a first non-defining surface opposite the first defining surface in the thickness direction of the substrate;

[0116] The second substrate has a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and the first defining surface and the second defining surface are opposite to each other;

[0117] A metal sealing ring structure is disposed between a first limiting surface and a second limiting surface, and the sealing ring structure, the first limiting surface and the second limiting surface define an accommodating space;

[0118] The space is adapted to accommodate the MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal.

[0119] in:

[0120] One of the grounding terminal, input terminal, and output terminal is an electrical connection terminal that is electrically connected to the sealing ring structure.

[0121] 2. According to the semiconductor structure described in 1, wherein:

[0122] The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the first conductive disks is directly electrically connected to the sealing ring structure at the first substrate, and the first conductive disk corresponds to the electrical connection terminal.

[0123] 3. According to the semiconductor structure described in 2, wherein:

[0124] The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring. Both the second conductive disk and the first conductive disk correspond to the electrical connection terminal.

[0125] 4. The semiconductor structure according to 1, wherein:

[0126] The first substrate is provided with a plurality of first conductive pads corresponding to the input terminal, output terminal, and ground terminal. One of the first conductive pads is spaced apart from the sealing ring structure at the first substrate, and the first conductive pad corresponds to the electrical connection terminal.

[0127] The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring, and the second conductive disk corresponds to the electrical connection terminal.

[0128] 5. The resonator according to 3 or 4, wherein:

[0129] The semiconductor structure also includes a plurality of conductive portions spaced apart from each other along the circumferential direction of the sealing ring structure, the conductive portions extending in the thickness direction of the second substrate;

[0130] One end of the conductive part is electrically connected to the sealing ring structure, and the other end is located on the non-limited surface of the second substrate and electrically connected to the corresponding second conductive disk.

[0131] 6. The resonator according to 5, wherein:

[0132] The other ends of at least two conductive parts are simultaneously electrically connected to the electrical connection terminal.

[0133] 7. The resonator according to 6, wherein:

[0134] The sealing ring structure includes a metal sealing ring;

[0135] The plurality of conductive parts are arranged at intervals from each other along the circumferential direction of the sealing ring.

[0136] 8. According to the semiconductor structure described in 6, wherein:

[0137] The electrical connection terminal is either an input or an output terminal.

[0138] 9. According to the semiconductor structure described in 6, wherein:

[0139] The electrical connection terminal is the grounding terminal.

[0140] 10. According to the semiconductor structure described in 9, wherein:

[0141] The plurality of grounding terminals includes one grounding terminal that is electrically adjacent to the input terminal, and the one grounding terminal is the electrical connection terminal.

[0142] 11. According to the semiconductor structure described in 5, wherein:

[0143] The number of conductive portions near at least one of the grounding terminal, input terminal, and output terminal is less than the number of conductive portions near the other terminals of the grounding terminal, input terminal, and output terminal.

[0144] 12. The semiconductor structure according to 11, wherein:

[0145] The grounding terminal includes multiple grounding terminals;

[0146] The number of conductive portions near the input terminal and / or the output terminal is less than the number of conductive portions near one of the plurality of ground terminals.

[0147] 13. According to the semiconductor structure described in 12, wherein:

[0148] The plurality of grounding terminals includes one grounding terminal that is electrically adjacent to the input terminal, and the one grounding terminal is the electrical connection terminal;

[0149] The number of conductive portions near the input terminal, the output terminal, and the plurality of ground terminals, excluding the electrical connection terminal, is less than the number of conductive portions near the electrical connection terminal.

[0150] 14. According to the semiconductor structure described in 7, wherein:

[0151] The conductive part and the sealing ring are made of the same material, and the inner ring surface of the sealing ring is spaced apart from the receiving space in the horizontal direction.

[0152] 15. According to the semiconductor structure described in 7, wherein:

[0153] The sealing ring structure includes a first metal sealing layer disposed on a first defining surface and a second metal sealing layer disposed on a second defining surface. The first metal sealing layer and the second metal sealing layer are opposite to each other and are joined to each other at the mating surface. The sealing ring includes a first extension extending from the mating surface toward the first metal sealing layer and / or a second extension extending from the mating surface toward the second metal sealing layer.

[0154] 16. The semiconductor structure according to any one of 1-15, wherein:

[0155] The first substrate is a functional substrate, and the MEMS device is disposed on the functional substrate; and

[0156] The second substrate is a packaging substrate.

[0157] 17. The semiconductor structure according to any one of 1-15, wherein:

[0158] The MEMS device includes a filter, which includes an input terminal, an output terminal, and multiple ground terminals.

[0159] 18. A method for manufacturing a semiconductor structure, comprising the steps of:

[0160] A second substrate is provided, the second substrate having a first defining surface and a first non-defining surface opposite to the first defining surface in the thickness direction of the substrate, and a first metal sealing layer is disposed on the first defining surface;

[0161] A second substrate is provided, the second substrate having a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and a second metal sealing layer is disposed on the second defining surface;

[0162] A first metal sealing layer and a second metal sealing layer are joined together opposite to each other to form a sealing ring structure. The sealing ring structure, the first defining surface, and the second defining surface define a receiving space. The receiving space is suitable for accommodating a MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal.

[0163] The method further includes the following steps:

[0164] This allows one of the grounding terminal, input terminal, and output terminal to be electrically connected to the sealing ring structure, whereby the one terminal is the electrical connection terminal.

[0165] 19. According to the method described in 18, wherein:

[0166] The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal;

[0167] The step of “making one of the grounding terminal, input terminal and output terminal electrically connected to the sealing ring structure” includes: making one of the plurality of first conductive disks directly electrically connected to the sealing ring structure at the first base, wherein the first conductive disk corresponds to the electrical connection terminal.

[0168] 20. According to the method described in 18, wherein:

[0169] The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring. Both the second conductive disk and the first conductive disk correspond to the electrical connection terminal.

[0170] 21. According to the method described in 18, wherein:

[0171] The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of first conductive disks is spaced apart from the sealing ring structure at the first substrate. The first conductive disk corresponds to the electrical connection terminal.

[0172] The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, output terminal and ground terminal;

[0173] The step of “making one of the grounding terminal, input terminal and output terminal electrically connected to the sealing ring structure” includes: making one of the plurality of second conductive disks electrically connected to the sealing ring, wherein the one second conductive disk corresponds to the electrical connection terminal.

[0174] 22. According to the method described in 18, wherein:

[0175] The steps to form the sealing ring structure include:

[0176] An annular space is formed at the joint surface, and the inner interface of the annular space is spaced apart from the receiving space in the horizontal direction;

[0177] Multiple extending channels are formed that penetrate through the corresponding substrate and pass through at least a portion of the corresponding metal sealing layer along the thickness direction of the substrate. One end of each extending channel opens into a non-limiting surface of the corresponding substrate, and the other end of each extending channel communicates with the cylindrical annular space. The multiple extending channels are arranged circumferentially spaced along the annular space.

[0178] The annular space is filled with metal using the extended channel. The metal filled in the annular space forms a sealing ring, and the metal filled in the extended channel forms a conductive portion. The sealing ring is sealed and joined with the first metal sealing layer and the second metal sealing layer, and at least one of the conductive portions is electrically connected to the electrical connection terminal.

[0179] 23. According to the method described in 22, wherein:

[0180] This ensures that at least one end of the conductive portion located on the non-limited surface is electrically connected to one of the ground terminal, input terminal, or output terminal.

[0181] 24. According to the method described in 22, wherein:

[0182] This ensures that at least one of the conductive parts is electrically connected to the input or output terminal.

[0183] 25. According to the method described in 22, wherein:

[0184] The plurality of grounding terminals includes a grounding terminal that is electrically adjacent to the input terminal, and the grounding terminal that is electrically adjacent to the input terminal is the first grounding terminal;

[0185] The method includes the step of: electrically connecting at least one of the conductive portions to the first grounding terminal, wherein the first grounding terminal constitutes the electrical connection terminal.

[0186] 26. According to the method described in 22, wherein:

[0187] In the step of forming the extension channel, the number of extension channels near at least one of the grounding terminal, input terminal, and output terminal is less than the number of extension channels near the other terminals of the grounding terminal, input terminal, and output terminal.

[0188] 27. According to the method described in 26, wherein:

[0189] The plurality of grounding terminals includes a grounding terminal that is electrically adjacent to the input terminal, and the grounding terminal that is electrically adjacent to the input terminal is the first grounding terminal;

[0190] In the step of forming the extended channel, the number of extended channels near the input terminal, the output terminal, and all of the plurality of ground terminals except the first ground terminal is less than the number of extended channels near the first ground terminal; and

[0191] In the step of filling the annular space with metal, at least one end of the conductive portion on the non-limiting surface is electrically connected to the first grounding terminal.

[0192] 28. A MEMS device comprising a semiconductor structure according to any one of 1-17.

[0193] 29. An electronic device comprising a MEMS device according to claim 28, or a semiconductor structure according to any one of claims 1-17.

[0194] The electronic devices mentioned here include, but are not limited to, intermediate products such as radio frequency front-ends and filtering and amplification modules, as well as terminal products such as mobile phones, WIFI, and drones.

[0195] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that variations may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A semiconductor structure, comprising: A first substrate, the first substrate having a first defining surface and a first non-defining surface opposite the first defining surface in the thickness direction of the substrate; The second substrate has a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and the first defining surface and the second defining surface are opposite to each other; A metal sealing ring structure is disposed between a first limiting surface and a second limiting surface, and the sealing ring structure, the first limiting surface and the second limiting surface define an accommodating space; The space is adapted to accommodate the MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal. in: One of the grounding terminal, input terminal, and output terminal is an electrical connection terminal that is electrically connected to the sealing ring structure, so as to reduce the parasitic inductance caused by the longitudinal electrical connection line between the first substrate and the second substrate.

2. The semiconductor structure according to claim 1, wherein: The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the first conductive disks is directly electrically connected to the sealing ring structure at the first substrate, and the first conductive disk corresponds to the electrical connection terminal.

3. The semiconductor structure according to claim 2, wherein: The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring. Both the second conductive disk and the first conductive disk correspond to the electrical connection terminal.

4. The semiconductor structure according to claim 1, wherein: The first substrate is provided with a plurality of first conductive pads corresponding to the input terminal, output terminal, and ground terminal. One of the first conductive pads is spaced apart from the sealing ring structure at the first substrate, and the first conductive pad corresponds to the electrical connection terminal. The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring, and the second conductive disk corresponds to the electrical connection terminal.

5. The semiconductor structure according to claim 3 or 4, wherein: The semiconductor structure also includes a plurality of conductive portions spaced apart from each other along the circumferential direction of the sealing ring structure, the conductive portions extending in the thickness direction of the second substrate; One end of the conductive part is electrically connected to the sealing ring structure, and the other end is located on the non-limited surface of the second substrate and electrically connected to the corresponding second conductive disk.

6. The semiconductor structure according to claim 5, wherein: The other ends of at least two conductive parts are simultaneously electrically connected to the electrical connection terminal.

7. The semiconductor structure according to claim 6, wherein: The sealing ring structure includes a metal sealing ring; The plurality of conductive parts are arranged at intervals from each other along the circumferential direction of the sealing ring.

8. The semiconductor structure according to claim 6, wherein: The electrical connection terminal is either an input or an output terminal.

9. The semiconductor structure according to claim 6, wherein: The electrical connection terminal is the grounding terminal.

10. The semiconductor structure according to claim 9, wherein: The plurality of grounding terminals includes one grounding terminal that is electrically adjacent to the input terminal, said grounding terminal being the electrical connection terminal.

11. The semiconductor structure according to claim 5, wherein: The number of conductive portions near at least one of the grounding terminal, input terminal, and output terminal is less than the number of conductive portions near the other terminals of the grounding terminal, input terminal, and output terminal.

12. The semiconductor structure according to claim 11, wherein: The grounding terminal includes multiple grounding terminals; The number of conductive portions near the input terminal and / or the output terminal is less than the number of conductive portions near one of the plurality of ground terminals.

13. The semiconductor structure according to claim 12, wherein: The plurality of grounding terminals includes one grounding terminal that is electrically adjacent to the input terminal, and the one grounding terminal is the electrical connection terminal; The number of conductive portions near the input terminal, the output terminal, and the plurality of ground terminals, excluding the electrical connection terminal, is less than the number of conductive portions near the electrical connection terminal.

14. The semiconductor structure according to claim 7, wherein: The conductive part and the sealing ring are made of the same material, and the inner ring surface of the sealing ring is spaced apart from the receiving space in the horizontal direction.

15. The semiconductor structure according to claim 7, wherein: The sealing ring structure includes a first metal sealing layer disposed on a first defining surface and a second metal sealing layer disposed on a second defining surface. The first metal sealing layer and the second metal sealing layer are opposite to each other and are joined to each other at the mating surface. The sealing ring includes a first extension extending from the mating surface toward the first metal sealing layer and / or a second extension extending from the mating surface toward the second metal sealing layer.

16. The semiconductor structure according to any one of claims 1-4 and 6-15, wherein: The first substrate is a functional substrate, and the MEMS device is disposed on the functional substrate; and The second substrate is a packaging substrate.

17. The semiconductor structure according to any one of claims 1-4 and 6-15, wherein: The MEMS device includes a filter, which includes an input terminal, an output terminal, and multiple ground terminals.

18. A method for manufacturing a semiconductor structure, comprising the steps of: A first substrate is provided, the first substrate having a first defining surface and a first non-defining surface opposite to the first defining surface in the thickness direction of the substrate, and a first metal sealing layer is disposed on the first defining surface; A second substrate is provided, the second substrate having a second defining surface and a second non-defining surface opposite to the second defining surface in the thickness direction of the substrate, and a second metal sealing layer is disposed on the second defining surface; A first metal sealing layer and a second metal sealing layer are joined together opposite to each other to form a sealing ring structure. The sealing ring structure, the first defining surface, and the second defining surface define a receiving space. The receiving space is suitable for accommodating a MEMS device, which includes an input terminal, an output terminal, and at least one ground terminal. The method further includes the following steps: One of the grounding terminal, input terminal, and output terminal is electrically connected to the sealing ring structure, and the one terminal is the electrical connection terminal, so as to reduce the parasitic inductance caused by the longitudinal electrical connection line between the first substrate and the second substrate.

19. The method of claim 18, wherein: The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal; The step of "making one of the grounding terminal, input terminal and output terminal electrically connected to the sealing ring structure" includes: making one of the plurality of first conductive disks directly electrically connected to the sealing ring structure at the first base, wherein the first conductive disk corresponds to the electrical connection terminal.

20. The method of claim 19, wherein: The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of second conductive disks is electrically connected to the sealing ring. Both the second conductive disk and the first conductive disk correspond to the electrical connection terminal.

21. The method according to claim 18, wherein: The first substrate is provided with a plurality of first conductive disks corresponding to the input terminal, the output terminal and the ground terminal. One of the plurality of first conductive disks is spaced apart from the sealing ring structure at the first substrate. The first conductive disk corresponds to the electrical connection terminal. The second substrate is provided with a plurality of second conductive disks corresponding to the input terminal, output terminal and ground terminal; The step of "making one of the grounding terminal, input terminal and output terminal electrically connected to the sealing ring structure" includes: making one of the plurality of second conductive disks electrically connected to the sealing ring, wherein the one second conductive disk corresponds to the electrical connection terminal.

22. The method of claim 18, wherein: The steps to form the sealing ring structure include: An annular space is formed at the joint surface, and the inner interface of the annular space is spaced apart from the receiving space in the horizontal direction; Multiple extending channels are formed that penetrate through the corresponding substrate and pass through at least a portion of the corresponding metal sealing layer along the thickness direction of the substrate. One end of each extending channel opens into a non-limiting surface of the corresponding substrate, and the other end of each extending channel communicates with a cylindrical annular space. The multiple extending channels are arranged circumferentially spaced along the annular space. The annular space is filled with metal using the extended channel. The metal filled in the annular space forms a sealing ring, and the metal filled in the extended channel forms a conductive portion. The sealing ring is sealed and joined with the first metal sealing layer and the second metal sealing layer, and at least one of the conductive portions is electrically connected to the electrical connection terminal.

23. The method according to claim 22, wherein: This ensures that at least one end of the conductive portion located on the non-limited surface is electrically connected to one of the ground terminal, input terminal, or output terminal.

24. The method of claim 22, wherein: This ensures that at least one of the conductive parts is electrically connected to the input or output terminal.

25. The method according to claim 22, wherein: The plurality of grounding terminals includes a grounding terminal that is electrically adjacent to the input terminal, wherein the grounding terminal that is electrically adjacent to the input terminal is the first grounding terminal; The method includes the step of: electrically connecting at least one of the conductive portions to the first grounding terminal, wherein the first grounding terminal constitutes the electrical connection terminal.

26. The method according to claim 22, wherein: In the step of forming the extension channel, the number of extension channels near at least one of the grounding terminal, input terminal, and output terminal is less than the number of extension channels near the other terminals of the grounding terminal, input terminal, and output terminal.

27. The method according to claim 26, wherein: The plurality of grounding terminals includes a grounding terminal that is electrically adjacent to the input terminal, wherein the grounding terminal that is electrically adjacent to the input terminal is the first grounding terminal; In the step of forming the extended channel, the number of extended channels near the input terminal, the output terminal, and all of the plurality of ground terminals except the first ground terminal is less than the number of extended channels near the first ground terminal; and In the step of filling the annular space with metal, at least one end of the conductive portion on the non-limiting surface is electrically connected to the first grounding terminal.

28. A MEMS device comprising a semiconductor structure according to any one of claims 1-17.

29. An electronic device comprising a MEMS device according to claim 28, or a semiconductor structure according to any one of claims 1-17.

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