A photolithography method
By analyzing the defocusing defect patterns on wafers and adjusting the exposure parameters in the photolithography process, the problem of uneven wafer polishing caused by the load effect in chemical mechanical polishing was solved, thereby improving the yield of semiconductor chips.
Patent Information
- Application Number
- CN202210336655.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-31
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2042-03-31
AI Technical Summary
In the chemical mechanical polishing process, different pattern density areas on the wafer surface are prone to load effects, leading to over-polishing or insufficient polishing in some areas, which affects the performance of semiconductor chips.
By analyzing the defocus defect pattern of the exposed wafer, the location of the fixed defocus defect is determined, and the exposure parameters of the segmentation pattern, especially the exposure offset, are adjusted to adjust the position of the mask pattern in the photolithography process and avoid the load effect during chemical mechanical polishing.
This effectively avoids the problem of over-grinding or insufficient grinding in local areas of the wafer surface, thus improving the yield of semiconductor chips.
Smart Images
Figure CN114675504B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor lithography technology, and in particular to a lithography method. BACKGROUND
[0002] At present, chemical mechanical polishing (CMP) process is widely used in various stages of improving wafer flatness.
[0003] In the early stage of the manufacturing process of integrated circuit chips, the integrated circuit chip pattern needs to be designed, and different patterns can be designed through layout, and different patterns have different pattern densities. In the later manufacturing process, due to the characteristics of the CMP process, the areas with different pattern densities on the wafer are prone to loading effect, which causes the local area of the wafer surface to be over-polished or insufficiently polished, thereby affecting the performance of the final prepared radio frequency chip (semiconductor chip). SUMMARY
[0004] The present application provides a lithography method, which can solve the problem that the wafer surface is over-polished or insufficiently polished due to the loading effect of the wafer surface during chemical mechanical polishing of the wafer surface.
[0005] In one aspect, the present application provides a lithography method, wherein an initial mask pattern is composed of a plurality of arrayed partition patterns, which is used to completely transfer the designed pattern to the wafer, and the lithography method comprises:
[0006] According to the defocus defect pattern of at least two batches of exposed wafers, it is determined whether the defocus defect position of the wafer surface is fixed;
[0007] If the defocus defect position is fixed, the partition pattern corresponding to the defocus defect position is determined according to the initial mask pattern and the defocus defect pattern;
[0008] The exposure parameter of the partition pattern corresponding to the defocus defect position is adjusted;
[0009] All partition patterns are used to expose the wafer to be exposed in sequence.
[0010] Optionally, in the lithography method, the step of adjusting the exposure parameter of the partition pattern corresponding to the defocus defect position comprises:
[0011] The exposure offset of the partition pattern corresponding to the defocus defect position is adjusted.
[0012] Optionally, in the lithography method, the exposure offset is -800 μm to -1200 μm.
[0013] Optionally, in the photolithography method, the exposure offset is +800μm to +1200μm.
[0014] Optionally, in the photolithography method, if the defocus defect position is fixed, the step of confirming the split mask layout corresponding to the defocus defect position according to the initial mask layout and the defocus defect pattern comprises:
[0015] If the defocus defect position is fixed, the initial mask layout and the defocus defect pattern are superimposed to determine the split mask layout corresponding to the defocus defect position.
[0016] Optionally, in the photolithography method, each defocus defect position corresponds to at least two split mask layouts.
[0017] Optionally, in the photolithography method, the split mask layout corresponding to the defocus defect position is a design pattern of a shallow trench isolation structure.
[0018] The technical scheme of the present application has at least the following advantages:
[0019] The present application fixes the defocus defect position, and then determines the split mask layout corresponding to the defocus defect position by using the initial mask layout and the defocus defect pattern, so as to adjust the exposure parameter of the split mask layout corresponding to the defocus defect position, thereby adjusting the position of the mask layout pattern transferred to the wafer in the photolithography process in advance, avoiding the problem that the wafer surface is over-polished or insufficiently polished due to the load effect of the wafer surface during chemical mechanical polishing of the wafer surface, and improving the yield of the finally prepared semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.
[0021] Figure 1 is a flow chart of the photolithography method of the embodiment of the present application. DETAILED DESCRIPTION
[0022] With reference to the drawings, the technical solutions in the present application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall into the scope of the present application.
[0023] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0024] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0025] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.
[0026] The embodiment of the present application provides a photolithography method, an initial mask plate pattern is composed of a plurality of arrayed split patterns, which is used to completely transfer the designed pattern to a wafer, please refer to Figure 1 , Figure 1 is a flowchart of the photolithography method of the embodiment of the present application, the photolithography method comprises:
[0027] S10: comparing and analyzing the defocus defect patterns of at least two batches of exposed wafers to determine whether the defocus defect positions on the wafer surface are fixed. Specifically, in the present embodiment, the defocus defect positions are at the edge positions of the wafer, and the split pattern corresponding to the defocus defect position can be a designed pattern of a shallow trench isolation structure.
[0028] S20: If the defocus defect position is fixed, the split mask layout corresponding to the defocus defect position is determined according to the initial mask layout and the defocus defect pattern. Specifically, if the defocus defect position is fixed, the initial mask layout and the defocus defect pattern are superimposed to determine the split mask layout corresponding to the defocus defect position. In this embodiment, each defocus defect position corresponds to at least two split mask layouts.
[0029] S30: The exposure parameter of the split mask layout corresponding to the defocus defect position is adjusted. Specifically, the exposure offset of the split mask layout corresponding to the defocus defect position is adjusted. The exposure offset is -800 μm to -1200 μm. The exposure offset is +800 μm to +1200 μm.
[0030] S40: All the split mask layouts are used to expose the wafer to be exposed in sequence.
[0031] In this application, the fixed defocus defect position is first determined by comparing and analyzing the defocus defect patterns of a plurality of batches of exposed wafers, and then the split mask layout corresponding to the defocus defect position is determined by superimposing the defocus defect pattern and the initial mask layout. The exposure offset of the split mask layout corresponding to the defocus defect position is adjusted, so that the position of the mask pattern transferred to the wafer is adjusted in advance in the photolithography process, thereby avoiding the problem that the wafer surface is over-polished or not polished enough due to the load effect of the wafer surface during the subsequent chemical mechanical polishing of the wafer surface, and improving the yield of the finally prepared semiconductor chip.
[0032] Obviously, the above embodiments are only examples for clearly illustrating, and are not intended to limit the implementation. For those skilled in the art, other different forms of changes or variations can be made on the basis of the above description. Here, all the implementations do not need to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the application.
Claims
1. A photolithography method, characterized by, The initial mask layout is composed of a plurality of arrayed segmentation layouts for completely transferring the designed pattern to a wafer, and the photolithography method comprises: determining whether the defocus defect positions on the wafer surface are fixed according to the defocus defect patterns of the exposed wafers of at least two batches; if the defocus defect positions are fixed, superimposing the initial mask layout and the defocus defect patterns to determine the segmentation layouts corresponding to the defocus defect positions; adjusting the exposure offset of the segmentation layouts corresponding to the defocus defect positions; exposing the wafer to be exposed by using all the segmentation layouts in sequence.
2. The photolithography method of claim 1, wherein, The exposure offset is -800μm to -1200μm.
3. The photolithography method of claim 1, wherein, The exposure offset is +800μm to +1200μm.
4. The photolithography method of claim 1, wherein, Each of the defocus defect positions corresponds to at least two of the segmentation layouts.
5. The photolithography method of claim 1, wherein, The segmentation layouts corresponding to the defocus defect positions are the design patterns of shallow trench isolation structures.
Citation Information
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