A method for determining a simulation model, a method for classifying chips, and related devices

Abstract

The present invention provides a method for determining a simulation model, a method for classifying chips, and related devices. The method for determining the simulation model includes: obtaining test data of semiconductor devices fabricated under various process corner conditions, where the semiconductor devices include wafers on which multiple chips are fabricated, and the test data includes the test data of the chips; dividing the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, and the similarity between the test data of the chips in different regions and the simulation data is different; determining adjustment values of the simulation parameters of the initial simulation model according to the test data of the chips in different regions, and obtaining optimal simulation models corresponding to the chips in different regions respectively, so as to perform simulations on the chips in different regions based on the optimal simulation models and improve the accuracy of the simulation by the simulation model.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of chip manufacturing technology, and in particular, to a method for determining a simulation model, a method for classifying chips, and related devices. Background Art

[0002] In chip design, the SPICE (Simulation Program With Integrated Circuits Emphasis) model is usually used for simulation to verify the integrity of the connection and function of the chip design and predict the behavior of the chip. Although the SPICE model can characterize the influence of normal process fluctuations during the production process on the chip, due to the influence of non-uniformity of semiconductor manufacturing processes, there are differences in the device characteristics of chips in different regions of the wafer, resulting in inaccurate simulation of the chip performance when using a unified SPICE model to simulate chips in different regions on the same wafer. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method for determining a simulation model, a method for classifying chips, and related devices to improve the accuracy of simulation by the simulation model.

[0004] To achieve the above object, embodiments of the present invention provide the following technical solutions.

[0005] In a first aspect, the present invention provides a method for determining a simulation model, including:

[0006] Obtaining test data of semiconductor devices manufactured under various process corner conditions, where the semiconductor devices include wafers on which multiple chips are manufactured, and the test data includes the test data of the chips;

[0007] Dividing the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, where the similarity between the test data of chips in different regions and the simulation data is different;

[0008] Obtaining adjusted values of simulation parameters of the initial simulation model according to the test data of chips in the different regions, and obtaining optimal simulation models corresponding to the chips in the different regions respectively, so as to simulate the chips in the different regions based on the optimal simulation models.

[0009] In a second aspect, the present invention provides a method for classifying chips, including:

[0010] Obtaining measurement data of measurement structures in the chips, where the measurement data includes performance parameters of the measurement structures;

[0011] Determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the optimal simulation models corresponding to the chips in different regions on the same semiconductor device are different;

[0012] Determine the functional relationship between the first performance parameter and the second performance parameter according to the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure;

[0013] Determine the target value of the second performance parameter according to the target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter;

[0014] Classify the chip according to the actual value of the performance parameter of the adjusted chip.

[0015] In a third aspect, the present invention provides a simulation parameter determination device, including:

[0016] A first acquisition unit, configured to acquire test data of a semiconductor device fabricated under various process corner conditions, the semiconductor device including a wafer on which a plurality of chips are fabricated, and the test data including the test data of the chips;

[0017] A first processing unit, configured to divide the semiconductor device into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, and the similarity between the test data of the chips in different regions and the simulation data is different;

[0018] A second processing unit, configured to obtain the optimal simulation models corresponding to the chips in different regions according to the adjustment values of the simulation parameters of the initial simulation model determined according to the test data of the chips in different regions, so as to perform simulation on the chips in different regions based on the optimal simulation models.

[0019] In a fourth aspect, the present invention provides a chip classification device, including:

[0020] A second acquisition unit, configured to acquire measurement data of a measurement structure in a chip, and the measurement data includes the performance parameters of the measurement structure;

[0021] A third processing unit, configured to determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the optimal simulation models corresponding to the chips in different regions on the same semiconductor device are different;

[0022] A fourth processing unit, configured to determine a functional relationship between the first performance parameter and the second performance parameter according to a functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure;

[0023] A fifth processing unit, configured to determine a target value of the second performance parameter according to a target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter;

[0024] A classification unit, configured to classify the chip according to an actual value of the performance parameter of the adjusted chip.

[0025] In a fifth aspect, the present invention provides an electronic device, including:

[0026] A memory, storing at least one set of instructions;

[0027] A processor, configured to execute the at least one set of instructions to execute the simulation parameter determination method described in any one of the above, or the chip classification method described in any one of the above.

[0028] In a sixth aspect, the present invention provides a readable storage medium, where the readable storage medium stores at least one set of instructions, and the at least one set of instructions is used to cause execution of the simulation parameter determination method described in any one of the above, or the chip classification method described in any one of the above.

[0029] The simulation model determination method, chip classification method and related devices provided by the embodiments of the present invention, after obtaining the test data of semiconductor devices fabricated under various process corner conditions, divide the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model. The similarity between the test data and the simulation data of the chips in different regions is different. According to the test data of the chips in different regions, the simulation parameters of the initial simulation model are adjusted to obtain the best simulation models corresponding to the chips in different regions respectively, so as to perform simulation on the chips in different regions based on the best simulation models, thereby improving the accuracy of the simulation of the simulation model. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0031] Figure 1 It is a schematic diagram of the voltage-current characteristic curves of PMOS transistors in the central region of the wafer and PMOS transistors in the edge region;

[0032] Figure 2 Flow chart of the simulation model determination method provided by an embodiment of the present invention;

[0033] Figure 3 Schematic diagram of the chip arrangement structure of a wafer provided by an embodiment of the present invention;

[0034] Figure 4 Flow chart of the chip classification method provided by an embodiment of the present invention;

[0035] Figure 5 Schematic diagram of the structure of the simulation model determination device provided by an embodiment of the present invention;

[0036] Figure 6 Schematic diagram of the structure of the chip classification device provided by an embodiment of the present invention. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0038] In chip design, wafer foundries use SPICE models to characterize the impact of normal process fluctuations during wafer production on the devices within the chip. Chip designers can make reasonable designs based on the SPICE models, which can cover the impact of normal fluctuations in wafer production on the chip.

[0039] However, the SPICE model cannot cover the impact of semiconductor manufacturing process non-uniformity on the chip. For example, the non-uniformity of semiconductor manufacturing processes (such as FAB processes) can lead to differences in the characteristics of devices within the chips in the central and edge regions of the wafer, and further lead to differences in the performance of the chips in the central and edge regions of the wafer. As Figure 1 shown, Figure 1 is a schematic diagram of the voltage-current characteristic curves of PMOS transistors in the central region of the wafer and PMOS transistors in the edge region. It can be seen from the figure that the voltage-current characteristic curves of the two do not overlap, but there are obvious differences.

[0040] Therefore, although using a unified SPICE model to simulate the chips on the same wafer can characterize the impact of normal process fluctuations during the production of the same wafer on the chips, it cannot accurately characterize the impact of semiconductor manufacturing process non-uniformity on the chips, and thus cannot accurately simulate the performance of the chips.

[0041] Based on this, the present invention provides a simulation model determination solution, which divides a wafer into at least two regions, and the similarity between the test data and the simulation data of the chips in different regions is different. Then, the optimal simulation model corresponding to the chips in different regions is determined to improve the simulation accuracy of the simulation models of the chips in different regions.

[0042] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a simulation model determination method for determining the simulation models of the chips in different regions of a wafer to improve the simulation accuracy of the chips in each region. As Figure 2 shown, Figure 2 is a flowchart of the simulation model determination method provided by an embodiment of the present invention. The simulation model determination method includes:

[0043] S201: Obtain the test data of semiconductor devices fabricated under various process corner conditions. The semiconductor devices include wafers with multiple chips fabricated thereon, and the test data includes the test data of the chips;

[0044] To improve production efficiency, multiple chips are usually fabricated on the same wafer and under the same process conditions to form semiconductor devices with multiple chips. Among them, multiple chips can be fabricated on a silicon wafer or on a semiconductor substrate of other materials. Optionally, the semiconductor devices in the embodiments of the present invention include wafers with multiple chips fabricated thereon. As Figure 3 shown, Figure 3 is a schematic diagram of the chip arrangement structure on a wafer provided by an embodiment of the present invention. There are multiple chips 31 arranged in an array on the wafer.

[0045] Before fabricating the chips 31 on the wafer, the wafer process corner (corner) slicing conditions are designed and then handed over to the wafer foundry for wafer fabrication. It should be noted that to reduce the design difficulty, process engineers need to ensure that the performance of the semiconductor devices in the fabricated chips is maintained within a certain performance range to control parameter variations by scrapping the chips outside this performance range. This performance range is given in the form of the usual process corners, and the usual process corners include FF, SS, FS, SF, and TT. Among them, fast NMOS transistors and fast PMOS transistors are FF; fast NMOS transistors and slow PMOS transistors are FS; slow NMOS transistors and fast PMOS transistors are SF; slow NMOS transistors and slow PMOS transistors are SS, and TT is the process corner at the geometric center of the above four process corners (i.e., the four process critical points). Usually, the quadrilateral region determined by the above five process corners represents the acceptable wafers.

[0046] After the wafer is shipped from the factory, the ATE (Automatic Test Equipment) test program can be used to obtain the test data of the chips at each process corner of the wafer. The test data includes the characteristic data of the preset devices in the chip, and the characteristic data includes characteristic curves or characteristic parameters. Among them, the preset devices include transistors, such as PMOS transistors and / or NMOS transistors. The characteristic curves include the source-drain current Ids-gate-source voltage Vgs curve, the source-drain current Ids-source-drain voltage Vds curve, etc. The characteristic parameters include the saturation region threshold voltage Vtsat, the linear region threshold voltage Vtlin, the equivalent current Ieff, and the leakage current Ioff, etc.

[0047] S202: Divide the semiconductor device into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model. The similarity between the test data and the simulation data of the chips in different regions is different;

[0048] Among them, the initial simulation model is the SPICE model, which is a simulation program for integrated circuit performance analysis based on the spice simulation algorithm, and includes various device models such as passive components resistors, capacitors, inductors and active devices diodes, triodes, field effect transistors, etc. closely related to the Foundry process.

[0049] Under the influence of the non-uniformity of the semiconductor manufacturing process, the performance of the chips in each region of the semiconductor device is different. In particular, the wafer edge is usually an incomplete chip structure. Therefore, it is impossible to test and obtain the FAB process data, and it is possible that the SPICE model cannot accurately characterize the device characteristics of this part of the region, that is, according to the SPICE model simulation, the process characteristics of this part of the region cannot be covered.

[0050] Therefore, the initial simulation model is a simulation model that matches most chips. That is to say, the initial simulation model is not the simulation model that best matches all chips on the same semiconductor device, and the test data of all chips on the same semiconductor device is not similar to the simulation data of the initial simulation model.

[0051] For example, there may be a situation where the similarity between the test data of the chips in the central region of the wafer and the simulation data of the initial simulation model is large, and the similarity between the test data of the chips in the edge region of the wafer and the simulation data of the initial simulation model is small.

[0052] Based on this, in the embodiments of the present invention, the semiconductor device will be divided into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model. The similarity between the test data and the simulation data of the chips in different regions is different.

[0053] In an alternative example, the chips with a relatively low similarity between the test data and the simulation data are all located in the edge region of the wafer. As shown in Figure 3 , the gray chips are the chips with a relatively low similarity. Then, the radius of the central region S1 can be determined based on the coordinates of these chips to determine the sizes of the central region S1 and the edge region S2. Based on this, dividing the substrate into at least two regions includes: dividing the substrate into a central region S1 and an edge region S2, where the similarity between the test data and the simulation data of the chips in the central region S1 is greater than that of the chips in the edge region S2.

[0054] It should be noted that during the process of manufacturing semiconductor devices, the manufacturing process will normally fluctuate between different process corner conditions. Therefore, in order to cover the influence of the normal fluctuations in wafer production, in the embodiments of the present invention, semiconductor devices manufactured under different process corner conditions will be tested to obtain the test data of the semiconductor devices manufactured under different process corner conditions, and the semiconductor devices will be divided into at least two regions according to the similarity between the test data of the semiconductor devices manufactured under different process corner conditions and the simulation data of the initial simulation model under different process corner conditions.

[0055] In an alternative example, dividing the semiconductor device into at least two regions includes: dividing the semiconductor device into a central region and an edge region, where the similarity between the test data and the simulation data of the chips in the central region is greater than that of the chips in the edge region. Of course, the present invention is not limited to this. In some other examples, the semiconductor device can also be divided into three circular ring regions distributed from the inside outwards, which will not be elaborated here.

[0056] In an alternative example, the characteristic data at least includes the measured threshold voltage value, the measured equivalent current value, and the measured leakage current value of the transistor; the simulation data at least includes the simulated threshold voltage value, the simulated equivalent current value, and the simulated leakage current value of the transistor.

[0057] Based on this, determining the similarity between the test data of a semiconductor device manufactured under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition includes:

[0058] Determining the similarity between the test data of the semiconductor device manufactured under the process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition based on at least the similarity between the measured threshold voltage value and the simulated threshold voltage value, the similarity between the measured equivalent current value and the simulated equivalent current value, and the similarity between the measured leakage current value and the simulated leakage current value determined under any process corner condition.

[0059] The similarity between the test data of the semiconductor device fabricated under the process corner condition and the simulation data under the corresponding process corner condition of the initial simulation model can be determined according to the sum or average of the similarity between the measured threshold voltage and the simulated threshold voltage, the similarity between the measured equivalent current and the simulated equivalent current, and the similarity between the measured leakage current and the simulated leakage current.

[0060] 203: Obtain the adjusted values of the simulation parameters of the initial simulation model according to the test data of the chips in different regions, and obtain the optimal simulation models corresponding to the chips in different regions respectively, so as to simulate the chips in different regions based on the optimal simulation models.

[0061] After dividing the semiconductor device into at least two regions, analyze the test data of the chips in each region to determine the adjusted values of the simulation parameters of the initial simulation model. Then, adjust the simulation parameters of the initial simulation model according to the adjusted values of the simulation parameters in each region to obtain the optimal simulation models corresponding to the chips in each region respectively. Among them, the adjusted simulation parameters can be SPICE model device characteristic parameters such as mobility correction, source-drain channel current correction, and threshold voltage drift. It should be noted that the similarity between the simulation data of the optimal simulation model and the test data of the chips in the corresponding region is relatively large, such as greater than the similarity between the simulation data of the initial simulation model and the test data of the chips in this region.

[0062] In an optional example, after dividing the semiconductor device into a central region and an edge region, the corresponding central optimal simulation model can be determined according to the test data of the chips in the central region, and the corresponding edge optimal simulation model can be determined according to the test data of the chips in the edge region, so as to simulate the chips in the central region based on the central optimal simulation model and simulate the chips in the edge region based on the edge optimal simulation model, thereby improving the accuracy of the simulation by the simulation model.

[0063] As another optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a chip classification method for classifying chips according to the optimal simulation models corresponding to different chips. As Figure 4 shown, Figure 4 is a flowchart of the chip classification method provided by an embodiment of the present invention. The chip classification method includes:

[0064] S401: Obtain the measurement data of the measurement structure in the chip, and the measurement data includes the performance parameters of the measurement structure;

[0065] In some alternative examples, the measurement structure is disposed inside the chip. For example, the measurement structure is some key structures inside the chip, and the key structures include devices such as a processor, an I / O interface, a memory, or a capacitor, or each functional module inside the processor. Among them, the performance parameters of the key structures can be obtained by measuring the signals of the paths between the key structures. And the specific paths between the key structures can be obtained by sampling. In addition, the measurement data of the measurement structure inside the chip can be obtained through an ATE measurement station, and the measurement data includes the operating frequency or operating temperature of the measurement structure, etc.

[0066] S402: Determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the optimal simulation models corresponding to the chips in different regions on the same semiconductor device are different;

[0067] Among them, the semiconductor device includes a wafer on which multiple chips are fabricated. Determining the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip includes: performing simulation according to the optimal simulation model corresponding to the chip to obtain actual simulation data; determining the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the actual simulation data and the measurement data. Among them, the performance parameters of the chip include a first performance parameter and a second performance parameter.

[0068] In some alternative examples, the first performance parameter is the operating frequency, and the second performance parameter is the operating voltage. Of course, the present invention is not limited thereto. In some other alternative examples, the first performance parameter can also be the operating voltage, and the second performance parameter can also be the operating frequency.

[0069] In some alternative examples, after obtaining the performance parameters of the measurement structure inside the chip, such as the operating frequency, simulation can be performed based on the optimal simulation model corresponding to the chip to obtain the first performance parameter of the chip, such as the operating frequency, and the second performance parameter of the chip, such as the operating voltage, when the measurement structure is at the above-mentioned operating frequency. Then, the functional relationship between the first performance parameter of the chip, such as the operating frequency, and the operating frequency of the measurement structure, and the functional relationship between the second performance parameter of the chip, such as the operating voltage, and the operating frequency of the measurement structure can be obtained.

[0070] Since the optimal simulation models corresponding to the chips in different regions on the same semiconductor device, such as a wafer, are different, before simulation, it is necessary to first determine which region of the wafer the chip comes from, and then determine the optimal simulation model corresponding to the chip according to the correspondence between the different regions of the wafer and the different optimal simulation models. Among them, the division of the wafer region and the establishment of the correspondence between the wafer region and the optimal simulation model refer to the embodiments of the above-mentioned simulation model determination method, which will not be elaborated here.

[0071] In some alternative examples, if the chip is from the central region of the wafer, the simulation model corresponding to the chip is the best simulation model corresponding to the central region. In some other alternative examples, if the chip is from the edge region of the wafer, the simulation model corresponding to the chip is the best simulation model corresponding to the edge region.

[0072] S403: Determine the functional relationship between the first performance parameter and the second performance parameter according to the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure.

[0073] In some alternative examples, based on the functional relationship between the first performance parameter of the chip, such as the operating frequency, and the operating frequency of the measurement structure, and the functional relationship between the second performance parameter of the chip, such as the operating voltage, and the operating frequency of the measurement structure, the functional relationship between the first performance parameter of the chip, such as the operating frequency, and the second performance parameter of the chip, such as the operating voltage, can be obtained.

[0074] S404: Determine the target value of the second performance parameter according to the target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter.

[0075] To reduce the influence of process errors during chip manufacturing and achieve the best balance between the performance and power consumption of the chip, the performance parameters of the chip, such as the operating frequency or the operating voltage, are usually adjusted to adjust the operating voltage to the minimum voltage that maintains the preset operating frequency, or adjust the operating frequency to the maximum frequency that maintains the preset operating voltage.

[0076] In some alternative examples, the target value of the second performance parameter, such as the operating voltage, can be determined according to the target value of the first performance parameter, such as the operating frequency, and the functional relationship between the first performance parameter, such as the operating frequency, and the second performance parameter, such as the operating voltage, and the second performance parameter of the chip, such as the operating voltage, can be adjusted according to the target value of the second performance parameter, such as the operating voltage, to adjust the operating voltage of the chip to the minimum voltage that maintains the preset operating frequency.

[0077] S405: Classify the chip according to the actual value of the performance parameter of the adjusted chip.

[0078] After adjusting the second performance parameter of the chip, define the required frequency requirements according to the OPN specification, conduct functional verification and electrical parameter tests (such as FT test), test the actual values of the performance parameters of the adjusted chip, such as the actual value of the operating frequency, and calculate the voltage required by the processor core and the power consumption of the chip when reaching these actual values. Then judge whether the frequency, voltage and power consumption meet the OPN specification requirements. If they meet, fuse the FUSE and burn information such as OPN and chip ID. If they do not meet, downgrade the OPN specification for the next round of testing. Based on this, the chips can be divided into different OPN grades, so as to realize the classification of chips.

[0079] In the embodiment of the present invention, because the best simulation model with higher simulation accuracy is adopted, the classification accuracy of the chips is higher, which is more conducive to improving the passing rate of the chips.

[0080] As another optional implementation of the disclosed content of the embodiment of the present invention, the embodiment of the present invention provides a simulation model determination device, such as Figure 5 shown Figure 5 is a schematic structural diagram of a simulation model determination device provided by an embodiment of the present invention. The simulation model determination device includes:

[0081] A first acquisition unit 50, configured to acquire test data of semiconductor devices fabricated under various process corner conditions. The semiconductor devices include wafers fabricated with multiple chips, and the test data includes test data of the chips;

[0082] A first processing unit 51, configured to divide the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model. The similarity between the test data and the simulation data of the chips in different regions is different;

[0083] A second processing unit 52, configured to obtain the best simulation models corresponding to the chips in different regions according to the adjustment values of the simulation parameters of the initial simulation model determined according to the test data of the chips in different regions, so as to simulate the chips in different regions based on the best simulation models.

[0084] In some optional examples, the test data of the chips includes the characteristic data of preset devices in the chips, and the preset devices include transistors;

[0085] The characteristic data at least includes the measured value of the threshold voltage of the transistor, the measured value of the equivalent current, and the measured value of the leakage current; the simulation data at least includes the simulated value of the threshold voltage of the transistor, the simulated value of the equivalent current, and the simulated value of the leakage current.

[0086] In some optional examples, the first processing unit 51 divides the semiconductor devices into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, including:

[0087] Based on the similarity between the test data of semiconductor devices fabricated under various process corner conditions and the simulation data of the initial simulation model under the corresponding process corner conditions, the semiconductor devices are divided into at least two regions.

[0088] In some alternative examples, the first processing unit 51 determines the similarity between the test data of a semiconductor device fabricated under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition, including:

[0089] Determine the similarity between the test data of the semiconductor device fabricated under the process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition based on at least the similarity between the measured threshold voltage value and the simulated threshold voltage value, the similarity between the measured equivalent current value and the simulated equivalent current value, and the similarity between the measured leakage current value and the simulated leakage current value determined under any process corner condition.

[0090] In some alternative examples, the first processing unit 51 divides the semiconductor device into at least two regions, including:

[0091] Divide the semiconductor device into a central region and an edge region, where the similarity between the test data and the simulation data of the chips in the central region is greater than that of the chips in the edge region.

[0092] As another alternative implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a chip classification device, as Figure 6 shown, Figure 6 is a schematic structural diagram of a chip classification device provided by an embodiment of the present invention. The chip classification device includes:

[0093] An acquisition unit 60, configured to acquire measurement data of a measurement structure in a chip, where the measurement data includes performance parameters of the measurement structure;

[0094] A third processing unit 61, configured to determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the optimal simulation models corresponding to chips in different regions on the same semiconductor device are different;

[0095] A fourth processing unit 62, configured to determine the functional relationship between the first performance parameter and the second performance parameter according to the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure;

[0096] A fifth processing unit 63, configured to determine the target value of the second performance parameter according to the target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter;

[0097] Classification unit 64 is configured to classify the chip according to the actual value of the performance parameter of the adjusted chip.

[0098] In some alternative examples, the third processing unit 61 determines the functional relationship between the performance parameter of the chip and the performance parameter of the measurement structure according to the best simulation model corresponding to the chip, including: performing simulation according to the best simulation model corresponding to the chip to obtain actual simulation data; determining the functional relationship between the performance parameter of the chip and the performance parameter of the measurement structure according to the actual simulation data and the measurement data.

[0099] In some alternative examples, the first performance parameter is the operating frequency and the second performance parameter is the operating voltage.

[0100] As another alternative implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide an electronic device, which includes:

[0101] A memory that stores at least one set of instructions;

[0102] A processor that executes at least one set of instructions to execute the simulation parameter determination method provided in any of the above embodiments, or the chip classification method provided in any of the above embodiments.

[0103] As another alternative implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a readable storage medium that stores at least one set of instructions, and the at least one set of instructions is used to cause the execution of the simulation parameter determination method provided in any of the above embodiments, or the chip classification method provided in any of the above embodiments.

[0104] The above describes multiple embodiment solutions provided by the embodiments of the present invention. The alternative ways described in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend a variety of possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0105] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for determining a simulation model, characterized in that, it includes: Obtain test data of semiconductor devices fabricated under various process corner conditions. The semiconductor devices include wafers fabricated with multiple chips, and the test data includes the test data of the chips; According to the similarity between the test data and the simulation data of the initial simulation model, divide the semiconductor devices into at least two regions. The semiconductor device characteristics of different regions on the same semiconductor device are different, and the similarity between the test data of chips in different regions and the simulation data is different; According to the adjusted values of the simulation parameters of the initial simulation model determined from the test data of the chips in different regions, obtain the best simulation models corresponding to the chips in different regions respectively, so as to simulate the chips in different regions based on the best simulation models. The best simulation models corresponding to the chips in different regions on the same semiconductor device are different.

2. The method for determining a simulation model according to claim 1, characterized in that, The test data of the chip includes the characteristic data of preset devices in the chip, and the preset devices include transistors; The characteristic data at least includes the measured value of the threshold voltage of the transistor, the measured value of the equivalent current, and the measured value of the leakage current; the simulation data at least includes the simulated value of the threshold voltage of the transistor, the simulated value of the equivalent current, and the simulated value of the leakage current.

3. The method for determining a simulation model according to claim 2, characterized in that, The step of dividing the semiconductor device into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model includes: Dividing the semiconductor device into at least two regions according to the similarity between the test data of the semiconductor devices fabricated under various process corner conditions and the simulation data of the initial simulation model under various process corner conditions.

4. The method for determining a simulation model according to claim 3, characterized in that, Determining the similarity between the test data of a semiconductor device fabricated under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition includes: Determining the similarity between the test data of the semiconductor device fabricated under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition at least according to the similarity between the measured value of the threshold voltage and the simulated value of the threshold voltage, the similarity between the measured value of the equivalent current and the simulated value of the equivalent current, and the similarity between the measured value of the leakage current and the simulated value of the leakage current determined under any process corner condition.

5. The method for determining a simulation model according to claim 1, characterized in that, The step of dividing the semiconductor device into at least two regions includes: Dividing the semiconductor device into a central region and an edge region, and the similarity between the test data of the chips in the central region and the simulation data is greater than the similarity between the test data of the chips in the edge region and the simulation data.

6. A method for classifying chips, characterized in that, it includes: Obtain the measurement data of the measurement structure in the chip, and the measurement data includes the performance parameters of the measurement structure; Determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the semiconductor device characteristics of different regions on the same semiconductor device are different, and the optimal simulation models corresponding to the chips in different regions on the same semiconductor device are different. The optimal simulation model is obtained by adjusting the simulation parameters of the initial simulation model based on the simulation parameter adjustment values of each region, and the simulation parameter adjustment values are obtained by analyzing the test data of the chips in each region. Determine the functional relationship between the first performance parameter and the second performance parameter according to the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure. Determine the target value of the second performance parameter according to the target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter. Classify the chip according to the actual value of the performance parameters of the adjusted chip.

7. The chip classification method according to claim 6, wherein, the determining the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the optimal simulation model corresponding to the chip includes: Performing simulation according to the optimal simulation model corresponding to the chip to obtain actual simulation data; Determine the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the measurement data and the actual simulation data.

8. The chip classification method according to claim 6, wherein, the first performance parameter is the operating frequency, and the second performance parameter is the operating voltage.

9. A simulation parameter determination device, wherein, it includes: A first acquisition unit for acquiring test data of semiconductor devices fabricated under various process corner conditions. The semiconductor devices include wafers on which multiple chips are fabricated, and the test data includes the test data of the chips. A first processing unit for dividing the semiconductor device into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model. The semiconductor device characteristics of different regions on the same semiconductor device are different, and the similarity between the test data of the chips in different regions and the simulation data is different. A second processing unit for obtaining the optimal simulation models corresponding to the chips in different regions respectively according to the simulation parameter adjustment values of the initial simulation model determined from the test data of the chips in different regions, so as to perform simulation on the chips in different regions based on the optimal simulation models. The optimal simulation models corresponding to the chips in different regions on the same semiconductor device are different.

10. The simulation parameter determination device according to claim 9, wherein, the test data of the chip includes the characteristic data of preset devices in the chip, and the preset devices include transistors. The characteristic data at least includes the measured threshold voltage value, equivalent current value, and leakage current value of the transistor; the simulation data at least includes the simulated threshold voltage value, equivalent current value, and leakage current value of the transistor.

11. The simulation parameter determination device according to claim 10, wherein, the first processing unit divides the semiconductor device into at least two regions according to the similarity between the test data and the simulation data of the initial simulation model, including: dividing the semiconductor device into at least two regions according to the similarity between the test data of the semiconductor device fabricated under each process corner condition and the simulation data of the initial simulation model under each process corner condition.

12. The simulation parameter determination device according to claim 11, wherein, the first processing unit determines the similarity between the test data of the semiconductor device fabricated under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition, including: determining the similarity between the test data of the semiconductor device fabricated under any process corner condition and the simulation data of the initial simulation model under the corresponding process corner condition based at least on the similarity between the measured threshold voltage value and the simulated threshold voltage value, the similarity between the equivalent current measurement value and the equivalent current simulation value, and the similarity between the leakage current measurement value and the leakage current simulation value determined under any process corner condition.

13. The simulation parameter determination device according to claim 9, wherein, the first processing unit divides the semiconductor device into at least two regions, including: dividing the semiconductor device into a central region and an edge region, and the similarity between the test data of the chip in the central region and the simulation data is greater than the similarity between the test data of the chip in the edge region and the simulation data.

14. A chip classification device, wherein, it includes: a second acquisition unit, configured to acquire measurement data of a measurement structure in the chip, and the measurement data includes performance parameters of the measurement structure; a third processing unit, configured to determine a functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure according to the best simulation model corresponding to the chip; the performance parameters of the chip include a first performance parameter and a second performance parameter; the semiconductor device characteristics of different regions on the same semiconductor device are different, and the best simulation models corresponding to the chips in different regions on the same semiconductor device are different. The best simulation model is obtained by adjusting the simulation parameters of the initial simulation model based on the simulation parameter adjustment values, and the simulation parameter adjustment values are obtained by analyzing the test data of the chips in each region; a fourth processing unit, configured to determine a functional relationship between the first performance parameter and the second performance parameter according to the functional relationship between the performance parameters of the chip and the performance parameters of the measurement structure; a fifth processing unit, configured to determine a target value of the second performance parameter according to the target value of the first performance parameter and the functional relationship between the first performance parameter and the second performance parameter, and adjust the second performance parameter of the chip according to the target value of the second performance parameter. A classification unit for classifying the chip according to the actual value of the adjusted performance parameter of the chip.

15. The chip classification device according to claim 14, wherein, the function relationship between the performance parameter of the chip and the performance parameter of the measurement structure determined by the third processing unit according to the optimal simulation model corresponding to the chip includes: performing simulation according to the optimal simulation model corresponding to the chip to obtain actual simulation data; determining the function relationship between the performance parameter of the chip and the performance parameter of the measurement structure according to the measurement data and the actual simulation data.

16. The chip classification device according to claim 14, wherein, the first performance parameter is the operating frequency, and the second performance parameter is the operating voltage.

17. An electronic device, wherein, comprising: a memory storing at least one set of instructions; a processor that executes the at least one set of instructions to execute the simulation model determination method according to any one of claims 1 to 5, or the chip classification method according to any one of claims 6 to 8.

18. A readable storage medium, wherein, the readable storage medium stores at least one set of instructions, and the at least one set of instructions is used to cause execution of the simulation model determination method according to any one of claims 1 to 5, or the chip classification method according to any one of claims 6 to 8.

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