A method for preparing a NiGe / n-Ge Schottky diode

Abstract

The application relates to a preparation method of a NiGe / n-Ge Schottky diode. The method comprises the following steps: taking a Ge sheet as a substrate and pre-treating; growing an isolation layer on the Ge sheet, performing photoetching to form a pattern, and then performing photoetching once; sequentially evaporating Al and Ni, and then removing the metal not in the pattern; annealing, removing the excessive Ni, and evaporating positive and negative electrodes. The method can effectively relieve the Fermi level pinning effect, reduce the NiGe / n-Ge Schottky barrier height, and make the NiGe maintain thermal stability at 400 DEG C to 600 DEG C.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of silicon-based materials and devices, and particularly relates to a preparation method of a NiGe / n-Ge Schottky diode. BACKGROUND

[0002] Germanium (Ge) is considered as a promising channel material in next generation high mobility complementary metal-oxide-semiconductor (CMOS) devices due to its ultra-high electron and hole mobility. However, Fermi level pinning near the valence band of Ge increases the difficulty of adjusting the barrier height between metal and germanium by selecting metals with different work functions. At the same time, metal germanides are also compatible with self-alignment process and become good source / drain contacts, interconnection materials. Among them, NiGe is considered as the most promising metal germanide due to its low resistivity, low formation temperature and low substrate consumption rate. However, NiGe will appear agglomeration phenomenon when the annealing temperature reaches 400℃ or above, which seriously affects the performance of the device.

[0003] It is proposed at home and abroad to use an interlayer to adjust the metal / Ge contact barrier height. For example, J.-Y. Jason Lin et al. proposed to use a TiO2 interface layer to reduce the metal / n-Ge Schottky barrier height, R.R. Lieten et al. proposed to use a Ge3N4 interface layer to suppress the Fermi level pinning of metal / n-Ge, Liu et al. proposed that a fluorinated graphene interlayer can effectively alleviate the Fermi level pinning of Ti / n-Ge, and Masaharu Kobayashi et al. proposed to use an ultrathin Si3N4 interlayer to modulate the Schottky barrier height of metal / germanium.

[0004] There are also reports of using an interlayer to improve the thermal stability of NiGe. Shiyang Zhu et al. proposed to use a Ti interlayer to make NiGe remain thermally stable at 450 to 550℃, Jae-Wook Lee et al. proposed to use a Zr interlayer to improve the thermal stability of NiGe to 550℃, and Geon-Ho Shin et al. proposed to use a Co interlayer to make NiGe remain thermally stable at 450 to 570℃.

[0005] However, in the prior art, no one has achieved the thermal stability of NiGe at 400 to 600℃ while alleviating the Fermi level pinning effect and reducing the Schottky barrier height of NiGe / n-Ge. Therefore, the development of germanium-based devices still faces great challenges. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a preparation method of a NiGe / n-Ge Schottky diode, so as to overcome the defects of Fermi level pinning effect and low thermal stability of germanium-based devices in the prior art.

[0007] This invention also provides a method for fabricating a NiGe / n-Ge Schottky diode, comprising:

[0008] (1) Use Ge wafers as substrates and pretreat them;

[0009] (2) A long isolation layer is grown on the Ge wafer pretreated in step (1), the pattern is photolithographically etched, and then photolithography is performed again;

[0010] (3) After photolithography, Al and Ni are deposited sequentially by vapor deposition. The thickness of Al is 0.8-1.1 nm and the thickness of Ni is 8-12 nm. Then, the metals not in the pattern are removed.

[0011] (4) After removing the metal that is not in the pattern, anneal it, then remove the excess Ni, and vapor deposit the positive and negative electrodes.

[0012] Preferably, the Ge sheet in step (1) is an n-type (110) Ge sheet with a resistivity of 0.05-0.25 Ωcm.

[0013] Preferably, the pretreatment in step (1) is as follows: cleaning the Ge wafer with cyclically diluted HF to remove the native oxide layer on the surface, wherein the HF concentration is 0.5-1.5%.

[0014] Preferably, in step (2), the isolation layer is SiO2 with a thickness of 90-110 nm.

[0015] Preferably, the method used for the long isolation layer in step (2) is ion-enhanced chemical vapor deposition.

[0016] Preferably, in step (2), photolithography is performed by etching the exposed isolation layer with CF4 gas.

[0017] Preferably, in step (3), Al and Ni are deposited by electron beam evaporation.

[0018] Preferably, the removal of metal outside the pattern in step (3) is performed using a lift-off process.

[0019] Preferably, the annealing process parameters in step (4) are: annealing at 300℃-600℃ for 25-35s in N2 atmosphere. The N2 used is 99.999% high-purity N2.

[0020] Preferably, in step (4), excess Ni is removed by using dilute hydrochloric acid with a concentration of 8-12%.

[0021] Preferably, electron beam evaporation is used in step (4) for vapor deposition.

[0022] Preferably, in step (4), the positive and negative electrodes are Al, and the thickness of Al is 110-120 nm.

[0023] The application also provides the Ni / Al / n-Ge Schottky diode prepared by the method.

[0024] The application also provides application of the Ni / Al / n-Ge Schottky diode prepared by the method in a switching power supply, a frequency converter or a driver.

[0025] Beneficial effects

[0026] The application inserts a 1nm Al interlayer into a NiGe / n-Ge SBD to form a Ni / Al / n-Ge sandwich structure, which can effectively relieve Fermi level pinning effect, reduce the height of a NiGe / n-Ge Schottky barrier and make NiGe maintain thermal stability at 400-600 DEG C, thereby inhibiting agglomeration of NiGe and providing a new idea for development of a Ge-based MOSFET source / drain contact in the future. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The figure is a process flow chart and a NiGe / n-Ge SBD structure chart with an Al interlayer.

[0028] Figure 2 The figure is an XTEM chart of modulation of Ni / n-Ge at 450 DEG C by different thicknesses of Al interlayers, wherein a) the thickness of Al is 0nm; b) the thickness of Al is 1nm; c) the thickness of Al is 3nm; and d) the thickness of Al is 5nm.

[0029] Figure 3 The figure is an Rq change trend chart of Ni / (1nm)Al / Ge and Ni / Ge after different annealing temperatures. S

[0030] Figure 4 The figure is an Rq change trend chart of Ni / (1nm)Al / Ge and Ni / Ge after different annealing temperatures.

[0031] Figure 5 The figure is an XTEM test chart (a) and an EDX chart (b) of a sample with a 1nm Al interlayer after annealing at 400 DEG C.

[0032] Figure 6 The figure is an I-V characteristic chart of SBDs after different annealing temperatures, wherein a) is Ni / Ge and b) is Ni / Al / Ge.

[0033] Figure 7 The figure is a sheet resistance change chart of a sample in Comparative Example 1 under different annealing temperatures.

[0034] ​Figure 8 Figure 1 is a graph showing the surface root mean square roughness variation of the sample in Inventive Example 1 at different annealing temperatures.

[0035] Figure 9 Figure 2 is a TEM image of Ni / Ti(lnm) / Ge at different annealing temperatures in Inventive Example 1, wherein (a) the annealing temperature is 300°C; (b) the annealing temperature is 400°C; and (c) the annealing temperature is 450°C. DETAILED DESCRIPTION

[0036] The application will be further described in connection with the following specific examples. It should be understood that these examples are for illustration only and are not intended to limit the scope of the application. Furthermore, it should be understood that various modifications and changes can be made to the application by those skilled in the art upon reading the contents of this specification. Such equivalent forms are intended to fall within the scope of the appended claims.

[0037] Example 1

[0038] This example provides a method for preparing a NiGe / n-Ge Schottky diode, comprising:

[0039] (1) Using an n-type (110) Ge wafer with a resistivity of 0.05-0.25 Ωcm as a substrate, first clean the Ge wafer with cyclic dilution of HF (1%) to remove the native oxide layer on the surface;

[0040] (2) Then use plasma-enhanced chemical vapor deposition to grow 100 nm of SiO2 on the Ge as an isolation layer, then photoetch a pattern, etch the exposed SiO2 with CF4 gas, and then photoetch again;

[0041] (3) After photoetching again, use electron beam evaporation (the electron beam evaporation equipment used in this application is QBOX-450. Within 20 minutes after cleaning the Ge wafer, the Ge wafer needs to be attached to the rotating substrate of the electron beam evaporation system with high-temperature heat-conducting glue, and vacuum pumping is started. When the vacuum degree reaches 5E-4 Pa, the evaporation voltage, evaporation current, plating rate, and film thickness are set, as shown in the following table) to evaporate 1 nm of Al and 10 nm of Ni in sequence, and the metal lift-off process is used to remove the metal outside the pattern;

[0042] Material Vacuum (Pa) Evaporation voltage Evaporation current Coating rate Set film thickness Al 5.00E-04 9.05 mV 180 mA 0.2 A / S 10A Ni 5.00E-04 9.05 mV 150 mA 2 A / S 100A

[0043] (4) Then rapidly heat anneal at 350°C, 400°C, 450°C, 500°C, 550°C, and 600°C for 30 seconds in a 99.999% high-purity N2 atmosphere, then remove the excess Ni with 10% dilute hydrochloric acid, and finally evaporate 150 nm of Al as a positive and negative electrode by electron beam evaporation.

[0044] According to the above method, no 1 nm Al insertion layer, the rest are the same as the above method, as a control group.

[0045] Figure 3 The test method is: four-probe resistance measurement, measured at room temperature, four equally spaced metal probes arranged in a straight line are pressed on the surface of the sample, the current is passed between the first and fourth probes, and the voltage is measured between the second and third probes.

[0046] Figure 4 The test method is: atomic force microscope to measure the root mean square roughness of the surface, measured at room temperature and pressure, using tapping mode, the probe type is RTESP-300 silicon probe, the characteristic frequency is about 300kHZ, and the atomic force microscope is a Multimode8 atomic force microscope produced by Bruker company.

[0047] Figure 5 The test method is: energy dispersive X-ray spectroscopy measurement, which requires that the sample be measured in vacuum.

[0048] The samples annealed at 350℃, 400℃, and 450℃ were tested using a semiconductor parameter analyzer (KEITHLEY4200) under dark conditions at 300K, and the I-V characteristic curves were obtained as shown in Figure 6 .

[0049] According to the thermionic emission model, the SBD forward bias current I can be determined as:

[0050]

[0051] In the formula, q is the electronic charge (1.6×10 -19 C), V is the applied bias voltage, k is the Boltzmann constant (k=1.38×10 -23 J / K), T is the absolute temperature T=t+273℃ (t is the ambient temperature, unit: ℃), R s is the series resistance, n is the ideal factor, and the saturation current I0 can be obtained from the curve of lnI and (V-IR s ) at V=0, I0 is:

[0052]

[0053] Where A is the effective area of contact (4×10 -8 m 2 ), A ** is the Richard constant, which is about 50Acm -2 K -2 for n-type Ge, ф B is the Schottky barrier, ф BFor:

[0054]

[0055] The Schottky barrier height can be calculated and is shown in Table 1. It is found that the Fermi level pinning can be effectively relieved and the Schottky barrier height can be reduced by using 1 nm Al interlayer in Ni / n-Ge SBDs.

[0056] Table 1 Schottky barrier height of Ni / Ge and Ni / (1 nm)Al / Ge SBDs

[0057] Annealing temperature With 1 nm Al interlayer Without 1 nm Al interlayer 350℃ 0.35 ev 0.38 ev 400℃ 0.35 ev 0.38 ev 450℃ 0.32 ev 0.37 ev

[0058] Figure 2 It is shown that the sample without Al interlayer has a serious agglomeration phenomenon, the sample with 1 nm Al interlayer forms a continuous and uniform NiGe film, and the interface between NiGe and Ge substrate is flat, the sample surface is smooth to inhibit the agglomeration phenomenon, and the samples with 3 nm and 5 nm Al interlayer block the reaction of Ni and Ge.

[0059] Figure 3 and Figure 4 It is shown that the R s and R q trend Figure 1 Therefore, it is considered that the use of 1 nm Al interlayer to modulate Ni / Ge can inhibit high-temperature agglomeration and maintain thermal stability at 400-600°C.

[0060] Figure 5 It is shown that at this time, Al atoms are distributed on the surface of the sample, and the Al interlayer is converted into a cap layer. The atomic distribution of Ni and Ge in the about 25 nm thick NiGe film is uniform and about 1:1, and a single NiGe phase is formed.

[0061] Comparative Example 1

[0062] According to Example 1, the 1 nm Al in Example 1 is modified to 1 nm Ti, the annealing temperature is 300°C, 400°C, 450°C, and the rest is the same as Example 1.

[0063] It can be seen from Figure 6 and Figure 7 that when 1 nm Ti is used as an interlayer, NiGe will increase sharply at an annealing temperature greater than 400°C, and the thermal stability is poor.

[0064] Figure 8 It is shown that the NiGe / Ge interface is not flat after 1 nm Ti is annealed at 450°C, which will affect the device performance.

Claims

1. A method for fabricating a NiGe / n-Ge Schottky diode, comprising: (1) Use Ge wafer as a substrate and pre-treat it; (2) A long isolation layer is formed on the Ge wafer pretreated in step (1), the pattern is lithographically etched, and then lithographically etched again; wherein, the isolation layer is SiO2, the thickness of SiO2 is 90-110nm; the method used for the long isolation layer is ion-enhanced chemical vapor deposition; (3) After photolithography, Al and Ni are deposited sequentially by vapor deposition. The thickness of Al is 0.8-1.1 nm and the thickness of Ni is 8-12 nm. Then, the metals not in the pattern are removed. (4) After removing the metal not in the pattern, anneal to form a continuous and uniform NiGe film, and the interface between NiGe and Ge substrate is flat. Then remove the excess Ni and evaporate the positive and negative electrodes. The annealing process parameters are: annealing at 300℃-600℃ for 25-35s with N2 atmosphere.

2. The method according to claim 1, characterized in that, In step (1), the Ge sheet is an n-type (110) Ge sheet with a resistivity of 0.05-0.25 Ωcm.

3. The method according to claim 1, characterized in that, The pretreatment in step (1) is as follows: the Ge wafer is cleaned with HF diluted in a cycle to remove the native oxide layer on the surface, wherein the HF concentration is 0.5-1.5%.

4. The method according to claim 1, characterized in that, In step (2), photolithography involves etching the exposed isolation layer with CF4 gas.

5. The method according to claim 1, characterized in that, In step (3), Al and Ni are deposited by electron beam evaporation; metals not within the pattern are removed by lift-off process.

6. The method according to claim 1, characterized in that, In step (4), excess Ni is removed by dilute hydrochloric acid; electron beam evaporation is used for vapor deposition; the positive and negative electrodes are Al, and the thickness of Al is 110-120 nm.

7. A NiGe / n-Ge Schottky diode prepared by the method described in claim 1.

8. An application of a NiGe / n-Ge Schottky diode prepared by the method described in claim 1 in a switching power supply, frequency converter, or driver.

Images