A method of forming a contact hole in a semiconductor device, a capacitor manufacturing method

Abstract

This disclosure provides a method for forming contact holes in a semiconductor device and a method for manufacturing a capacitor. The method for forming contact holes in a semiconductor device may include, but is not limited to, at least one of the following steps: providing a semiconductor substrate and forming at least one stack on the semiconductor substrate; then forming a mask layer with a contact hole pattern over the entire stack; etching the stack based on the mask layer with the contact hole pattern to form contact holes on the stack; before removing the mask layer, forming a protective film on the inner sidewalls of the contact holes to protect the inner sidewalls of the contact holes; and removing the protective film simultaneously with removing the mask layer. This disclosure can protect the inner sidewalls of the contact holes from damage by the plasma gas used for etching during the removal of the mask layer, effectively preventing excessive bending within the contact holes. Therefore, this disclosure can significantly improve the yield of semiconductor devices, particularly semiconductor capacitors.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device processing technology, and more specifically, this disclosure can provide a method for forming contact holes in a semiconductor device and a method for manufacturing a capacitor. Background Technology

[0002] As semiconductor devices become increasingly integrated, a large aspect ratio is often required for the formed contact holes, with capacitor node holes in semiconductor capacitors being the most representative example. When forming capacitor node holes by etching, two conditions must be met: (1) adjacent capacitor node holes must be separated, and (2) the electrodes deposited in subsequent processes must be able to contact the underlying pads. However, when forming capacitor node holes, bending is often unavoidable. Moreover, the degree of bending will increase in subsequent processes, leading to a significant decrease in semiconductor device yield.

[0003] Therefore, how to effectively reduce the degree of bending on the capacitor node hole has become a technical problem that urgently needs to be solved and a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the problems existing in the processing technology of current semiconductor devices, this disclosure provides a method for forming contact holes in semiconductor devices and a method for manufacturing capacitors.

[0005] To achieve the above-mentioned technical objectives, this disclosure provides a method for forming contact holes in a semiconductor device. This method may include, but is not limited to, at least one of the following steps.

[0006] A semiconductor substrate is provided, and at least one stack is formed on the semiconductor substrate. A mask layer with a contact hole pattern is then formed over the entire stack, and the stack is etched based on the mask layer with the contact hole pattern to form contact holes on the stack. Before removing the mask layer, a protective film is formed on the inner sidewalls of the contact holes to protect the inner sidewalls of the contact holes. The protective film formed above is then removed simultaneously with the removal of the mask layer.

[0007] To achieve the above-mentioned technical objectives, this disclosure also provides a method for manufacturing a semiconductor capacitor, which may include, but is not limited to, the method for forming contact holes in a semiconductor device as described in any embodiment of this disclosure. The contact holes may be capacitor node holes.

[0008] The beneficial effects of this disclosure are as follows: This disclosure can protect the inner wall of the contact hole from damage by the etching plasma gas during the mask layer removal process, thereby preventing increased bending within the contact hole. Therefore, while meeting the miniaturization requirements of semiconductor devices, this disclosure can significantly improve the yield of semiconductor devices, especially semiconductor capacitors. For the entire semiconductor device fabrication process, this disclosure does not require a radical overhaul of existing processes. Moreover, the processing time of semiconductor capacitors based on this disclosure is almost the same as that of conventional processes, and the processing cost is also almost the same as that of conventional processes. Therefore, this disclosure has a wide range of applications. Attached Figure Description

[0009] Figure 1 A schematic diagram of the cross-sectional structure of a device after a stack is formed on a semiconductor substrate is shown in one or more embodiments of the present disclosure.

[0010] Figure 2 This illustration shows a schematic cross-sectional structure of a device after a mask layer and a photoresist layer have been formed on a stack in one or more embodiments of the present disclosure.

[0011] Figure 3 A schematic diagram of the cross-sectional structure of a device after a photomask is disposed above a photoresist layer is shown in one or more embodiments of the present disclosure.

[0012] Figure 4 A schematic diagram of the cross-sectional structure of the device after the patterned photoresist layer forms a contact hole pattern is shown in one or more embodiments of this disclosure.

[0013] Figure 5 A schematic diagram of the cross-sectional structure of the device after etching the mask layer using a patterned photoresist layer as a mask is shown in one or more embodiments of this disclosure.

[0014] Figure 6 A schematic diagram of the cross-sectional structure of a device after forming contact holes based on a mask layer etching stack with contact hole patterns, according to one or more embodiments of this disclosure, is shown.

[0015] Figure 7 A schematic diagram of the cross-sectional structure of the device after a protective film is formed on the inner wall of the contact hole is shown in one or more embodiments of this disclosure.

[0016] Figure 8 A schematic diagram of the cross-sectional structure of the device after removing the mask layer and the protective film in one or more embodiments of this disclosure is shown.

[0017] Figure 9 A schematic diagram of the cross-sectional structure of the device after the lower electrode is formed in the capacitor node hole in one or more embodiments of this disclosure is shown (the arrow points to an enlarged schematic diagram inside the circle).

[0018] Figure 10 A schematic diagram of the cross-sectional structure of the device with the upper support layer and upper molding layer etched in one or more embodiments of this disclosure is shown (the arrow points to an enlarged schematic diagram within the circle).

[0019] Figure 11 A schematic diagram of the cross-sectional structure of the device after removing the upper molding layer is shown in one or more embodiments of this disclosure (the arrow points to an enlarged schematic diagram within the circle).

[0020] Figure 12 A schematic diagram of the cross-sectional structure of the device with the etched lower support layer and lower molding layer in one or more embodiments of this disclosure is shown (the arrow points to an enlarged schematic diagram within the circle).

[0021] Figure 13 A schematic diagram of the cross-sectional structure of the capacitor storage electrode and its support structure formed in one or more embodiments of this disclosure is shown (the arrow points to an enlarged schematic diagram within the circle).

[0022] Figure 14 A schematic diagram of the cross-sectional structure of a device with a large bending contact hole formed using conventional methods is shown.

[0023] In the picture,

[0024] 100. Semiconductor substrate.

[0025] 101. Solder pad.

[0026] 102. Lower electrode.

[0027] 103. Dielectric layer.

[0028] 104. Upper electrode.

[0029] 200. Lower molding layer.

[0030] 300. Lower support layer.

[0031] 400. Upper molding layer.

[0032] 500. Upper support layer.

[0033] 600, Mask layer.

[0034] 700, photoresist layer.

[0035] 800, photomask.

[0036] 900, protective film.

[0037] 9000, Depression. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0041] This disclosure provides a method for forming contact holes in a semiconductor device, which can reduce the degree of contact hole bending and improve the performance of the semiconductor device. This disclosure uses a capacitor as an example for detailed explanation; the contact hole can be a capacitor node hole, and the capacitor can be, for example, a Dynamic Random Access Memory (DRAM). Of course, this disclosure can also be used in semiconductor devices such as logic control chips; that is, the contact hole forming method provided by this disclosure can be used in a variety of applications. The specific description of the method for forming contact holes in a semiconductor device is as follows.

[0042] Understandably, Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, containing multiple memory cells arranged in a matrix structure. Each memory cell mainly consists of a transistor and a capacitor controlled by the transistor, and the memory cells are electrically connected through word lines and bit lines. Data is input from the bit lines and then transferred to the capacitor through the transistor, or data stored in the capacitor is output through the transistor and bit lines. The capacitance of the capacitor is one of the most important factors determining the characteristics of DRAM. Therefore, maximizing the capacity is crucial in the development of DRAM. This disclosure effectively increases the aspect ratio of the capacitor node apertures, thereby significantly increasing the capacity of the DRAM.

[0043] like Figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). Taking a dynamic random access memory (DRAM) as an example, the semiconductor substrate 100 may have structures such as an active region, an interlayer dielectric layer, bit lines, bit line node contacts, word lines, memory node contacts, pads, and sidewalls. The bit line material is at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The bit line node contacts may be made of the same material as the bit lines. The structures disposed on the active region and the positions and connections between these structures can be wisely selected from existing designs, and will not be described further in this disclosure.

[0044] like Figure 1 As shown, a stacked structure can be formed on a semiconductor substrate 100. Forming the stacked structure on the semiconductor substrate 100 includes: providing at least one molding layer and at least one support layer on the semiconductor substrate 100, wherein the molding layer and the support layer can form a stack. This disclosure can form a stack consisting of at least one lower molding layer 200 and at least one lower support layer 300, and a stack consisting of at least one upper molding layer 400 and at least one upper support layer 500. The lower support layer 300 and the upper support layer 500 can be used to form support members, and the lower support layer 300 and the upper support layer 500 can be made of relatively hard oxides or nitrides to support electrodes in a capacitor structure. The lower molding layer 200 and the upper molding layer 400 can be removed in subsequent processes. The materials forming the lower molding layer 200 and the upper molding layer 400 may be, for example, one of the following: flowable oxide (FOX), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorinated silicate glass (FSG), plasma-enhanced oxide (PEOX), and high-density plasma CVD (HDP-CVD) oxide.

[0045] like Figure 2 The mask layer 600 and photoresist layer 700 are sequentially formed on the stack. The mask layer 600 may be, for example, a hard mask layer. The photoresist layer 700 may be, for example, a positive photoresist layer or a negative photoresist layer, and the present disclosure allows for reasonable selection and use according to actual conditions.

[0046] like Figure 3 As shown, a photomask 800 is disposed above the photoresist layer 700, and the photomask 800 has a contact hole pattern to be formed. The materials constituting the photomask 800 may include, but are not limited to, quartz glass, metallic chromium and photosensitive adhesive. Forming the contact hole pattern on the photomask 800 is a conventional process, and will not be described in detail in this disclosure.

[0047] like Figure 4 As shown, the photoresist layer 700 is patterned using a photomask 800 with contact hole patterns. During the patterning process, the contact hole patterns on the photomask 800 are transferred onto the photoresist layer 700, exposing the mask layer 600 disposed beneath the photoresist layer 700. The patterning process includes, but is not limited to, pre-baking, exposure, development, and post-baking processes, which are specifically implemented through photolithography processes and will not be described in detail in this disclosure.

[0048] like Figure 5 As shown, using the patterned photoresist layer 700 as a mask, the mask layer 600 is etched to transfer the contact hole pattern onto the mask layer 600. Then, the patterned photoresist layer 700 is removed, thus forming a mask layer 600 with contact hole patterns on the stack.

[0049] like Figure 6 As shown, the mask layer 600 with contact hole patterns is etched as shown in the above stack to form contact holes on the stack. That is, this disclosure allows the etching of the upper support layer 500, upper molding layer 400, lower support layer 300, and lower molding layer 200 using the mask layer 600 with contact hole patterns as a mask; this etching process can be, for example, dry etching. It is understood that there will inevitably be bending on the inner sidewalls of the formed contact holes, and one of the main objectives of this disclosure is to prevent this bending from becoming excessive. When applied to semiconductor capacitors, this disclosure can prevent the bending on the inner sidewalls of the capacitor node holes from becoming excessive.

[0050] Taking the formation of a semiconductor capacitor as an example, this step is achieved through a storage node etch process to obtain storage node holes. Multiple storage node holes are arranged alternately and repeatedly, for example, to form a honeycomb pattern.

[0051] like Figure 7The protective film 900 is formed on the inner wall of the contact hole, thereby protecting the inner wall of the contact hole from damage. Forming the protective film 900 on the inner wall of the contact hole includes performing an ashing process to utilize oxygen plasma generated during the ashing process to form silicon dioxide with silicon atoms within the contact hole, i.e., forming a silicon dioxide layer attached to the inner wall of the contact hole, which serves as the protective film 900. Based on the protective film 900, this disclosure can prevent the size of the recess 9000 in the contact hole from increasing, i.e., prevent the degree of bending within the contact hole from increasing.

[0052] Understandably, silicon atoms are inevitably formed in the processes preceding this step, and extensive experiments have shown that this disclosure can form a protective film 900 that effectively protects the inner wall of the contact hole. It is evident that this disclosure cleverly utilizes an ashing process to oxidize silicon atoms into silicon dioxide to obtain a silicon dioxide protective film. Furthermore, the thickness of the protective film 900 is less than the thickness of the mask layer 600, so that the protective film 900 is removed as much as possible when the mask layer 600 is removed.

[0053] like Figure 8 The process involves removing the mask layer 600 and simultaneously removing the protective film 900. Dry etching using plasma gas is employed during the removal of the mask layer 600. Due to the presence of the protective film 900, this disclosure protects the inner wall of the contact hole from damage by the plasma gas, preventing an increase in the degree of bending within the contact hole. In other words, this disclosure ensures that the size of the recessed portion 9000 on the contact hole does not increase, effectively separating adjacent capacitor node holes. Figure 14 Compared to the bending within the capacitor node hole formed in the previous method (recessed portion 9001 shown in the figure), the degree of bending within the contact hole formed in this disclosure is significantly reduced.

[0054] Generally, the protective film 900 can be completely removed during the mask layer 600 removal process of this disclosure. If any protective film 900 remains, this disclosure can also remove it through a cleaning process. It is understood that after removing the mask layer 600, this disclosure may further include performing a cleaning process to remove residual materials such as the protective film within the contact holes. The cleaning process may include, for example, a pre-cleaning process before electrode deposition.

[0055] It is understood that this disclosure can provide a capacitor manufacturing method, including a method for forming contact holes in a semiconductor device in any embodiment of this disclosure, wherein the contact holes are specifically capacitor node holes.

[0056] like Figure 1As shown, prior to forming the stack, this disclosure allows for the formation of a plurality of spaced-apart pads 101 on a semiconductor substrate 100. The material forming the pads 101 can be tungsten or cobalt, or at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). During the capacitor formation process, this disclosure allows for the formation of a nitride layer on the semiconductor substrate 100, with each pad located within the nitride layer.

[0057] like Figure 6 As shown, capacitor node holes are formed by etching the stack of layers based on the mask layer 600 with contact hole patterns, and each pad 101 is exposed after the capacitor node holes are formed.

[0058] like Figure 9 As shown, a lower electrode 102 is formed within the capacitor node hole. The material forming the lower electrode can be at least one of a metal, a conductive metal oxide, or doped polycrystalline silicon, such as a high-melting-point metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive noble metal oxide (e.g., PtO, RuO2, or IrO2), and / or a conductive oxide (e.g., SrRuO3, RuO3, CaRuO3).

[0059] like Figure 10 As shown, the upper support layer 500 and the upper molding layer 400 are etched. This disclosure allows for dry etching of the upper support layer 500 based on a provided support mask (not shown), exposing the upper molding layer 400. Therefore, this disclosure enables the formation of etching paths for etching the upper molding layer 400.

[0060] like Figure 11 As shown, the upper molding layer 400 is removed by wet etching. Based on the etching path formed by etching the upper support layer 500, the upper molding layer 400 can then be removed by wet etching. The etching solution used for wet etching can be, for example, a mixture of hydrofluoric acid and water or ammonium fluoride and water.

[0061] like Figure 12As shown, the etching path is deepened. This disclosure can also deepen the etching path by dry etching the lower support layer 300 based on a support mask, exposing the lower molding layer 200. The lower molding layer 200 can then be removed by wet etching, where the etching solution can be, for example, a mixture of hydrofluoric acid and water or ammonium fluoride and water. The support mask used is then removed.

[0062] like Figure 13 As shown, after removing the lower molding layer 200, a dielectric layer 103 and an upper electrode 104 are formed inside the capacitor node hole. Specifically, the dielectric layer 103 and the upper electrode 104 are deposited into the capacitor node hole. The dielectric layer 103 is formed along the bottom wall and inner sidewall of the lower electrode 102, and the upper electrode 104 is formed along the bottom wall and inner sidewall of the dielectric layer 103. The material forming the upper electrode can be at least one of a metal, a conductive metal oxide, or doped polycrystalline silicon, such as a high-melting-point metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive noble metal oxide (e.g., PtO, RuO2, or IrO2), and / or a conductive oxide (e.g., SrRuO3, RuO3, CaRuO3).

[0063] Based on the above method, this disclosure is able to form a semiconductor structure with a smaller bending contact hole, or in other words, the recess 9000 on the semiconductor structure provided by this disclosure is smaller in size.

[0064] like Figure 13 As shown, taking a semiconductor capacitor as an example, the semiconductor device provided in this disclosure includes, but is not limited to, a semiconductor substrate 100, bonding pads 101, a support member, a lower electrode 102, a dielectric layer 103, and an upper electrode 104. The support member may include an upper support member and a lower support member. A nitride layer is formed on the semiconductor substrate 100, and each bonding pad 101 is located in the nitride layer. Each lower electrode 102 is respectively disposed on and in contact with each bonding pad 101. The number of support members in this disclosure can be multiple, and these support members are at different heights to effectively support the electrodes. This disclosure can provide a dynamic random access memory, which may include the semiconductor structure in any embodiment of this disclosure. This disclosure can also provide an electronic device, which includes the dynamic random access memory in any embodiment of this disclosure. The electronic device may include, but is not limited to, smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0065] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0066] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for forming contact holes in a semiconductor device, characterized in that, include: A semiconductor substrate is provided, and a stack is formed on the semiconductor substrate; A mask layer with a contact hole pattern is formed on the stack; The stack is etched based on the mask layer with the contact hole pattern to form contact holes on the stack; A protective film is formed on the inner wall of the contact hole; The protective film is used to protect the contact hole so that the curvature of the inner side of the contact hole does not increase during the removal of the mask layer; the thickness of the protective film is less than the thickness of the mask layer; The protective film is removed simultaneously with the mask layer; The formation of a protective film on the inner wall of the contact hole includes: An ashing process is performed to utilize the oxygen plasma generated by the ashing process to form a silicon dioxide layer attached to the inner wall of the contact hole with silicon atoms in the contact hole, serving as the protective film.

2. The method for forming a contact hole in a semiconductor device according to claim 1, characterized in that, After removing the mask layer, the process also includes: Perform a cleaning process to remove any protective film residue inside the contact holes.

3. The method for forming a contact hole in a semiconductor device according to claim 1, characterized in that, The mask layer having a contact hole pattern formed on the stack includes: A mask layer and a photoresist layer are sequentially formed on the stacked layers; The photoresist layer is patterned using a photomask with contact hole patterns; Using a patterned photoresist layer as a mask, the mask layer is etched to transfer the contact hole pattern onto the mask layer; Remove the patterned photoresist layer.

4. The method for forming a contact hole in a semiconductor device according to claim 1, characterized in that, The formation of the stack on the semiconductor substrate includes: At least one molding layer and at least one support layer are disposed on the semiconductor substrate, the molding layer and the support layer forming the stack.

5. A method for manufacturing a capacitor, characterized in that, The method includes the method of forming a contact hole in a semiconductor device as described in any one of claims 1 to 4, wherein the contact hole is a capacitor node hole.

6. The capacitor manufacturing method according to claim 5, characterized in that, Also includes: Multiple spaced bonding pads are formed on a semiconductor substrate before the stack is formed; After forming the capacitor node holes, each solder pad is exposed.

7. The capacitor manufacturing method according to claim 6, characterized in that, Also includes: A lower electrode is formed within the capacitor node hole; The stack is etched to form a support for supporting the lower electrode.

8. The capacitor manufacturing method according to claim 7, characterized in that, Also includes: A dielectric layer and an upper electrode are deposited into the capacitor node hole. The dielectric layer is formed along the bottom wall and inner sidewall of the lower electrode, and the upper electrode is formed along the bottom wall and inner sidewall of the dielectric layer.

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