Semiconductor packaging glass substrate, semiconductor packaging substrate, and semiconductor device

Abstract

This embodiment relates to a semiconductor packaging glass substrate, a semiconductor packaging substrate, a semiconductor device, and the like. The semiconductor packaging glass substrate includes: i) a glass substrate having a first surface and a second surface facing each other; ii) a plurality of core through-holes extending through the glass substrate in a thickness direction; and iii) a core layer located on the surface of the core through-holes, including a core seed layer that serves as a seed crystal for forming a conductive layer or a core distribution layer that serves as a conductive layer. On the first surface of the glass substrate, a stress difference P between stress measured on a blank line (a straight line connecting locations without the core through-holes) and stress measured on a through-hole line (a straight line connecting locations with the core through-holes) according to Formula 1: P = Vp-Np is 1.5 MPa or less. In Formula 1, Vp is the difference between the maximum and minimum stress values measured on the through-hole line, and Np is the difference between the maximum and minimum stress values measured on the blank line.

Description

[0001] This application is a divisional application of the patent application with application number 2020800114222, application date March 27, 2020, and invention name “Packaging glass substrate for semiconductors, packaging substrate for semiconductors, and semiconductor devices”. Technical Field

[0002] This embodiment relates to a semiconductor packaging glass substrate, a semiconductor packaging substrate, and a semiconductor device.

[0003] Cross-references with related applications

[0004] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 826,122, filed on March 29, 2019, and U.S. Provisional Patent Application No. 62 / 826,144, filed on March 29, 2019, the disclosures of which are hereby incorporated by reference in their entireties. Background Art

[0005] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers in a state that can be used in actual products is called the back-end (BE) process, which includes the packaging process.

[0006] The four core technologies of the semiconductor industry that have enabled the recent rapid growth of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is advancing in various forms, such as line widths in the nanometer unit below micrometers, cells exceeding 10 million, high-speed operation, and the release of large amounts of heat. However, this technology lacks the technical support to fully package these semiconductors. Therefore, the electrical performance of semiconductors sometimes depends on the packaging technology and corresponding electrical connections rather than the performance of the semiconductor technology itself.

[0007] Package substrates are made of ceramic or resin. Ceramic substrates, due to their high resistance and dielectric constant, make it difficult to mount high-performance, high-frequency semiconductor components. Resin substrates can mount relatively high-performance, high-frequency semiconductor components, but they have limitations in reducing wiring pitch.

[0008] Recently, research is underway to use silicon or glass as substrates for high-end packaging. By forming through-holes in silicon or glass substrates and applying conductive materials to these through-holes, the wiring length between components and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0009] Related prior art documents include Korean Patent Publication No. 10-2019-0008103, Korean Patent Publication No. 10-2016-0114710, and Korean Patent Authorization No. 10-1468680. Summary of the Invention

[0010] Problems to be solved by the invention

[0011] The present embodiment aims to provide a semiconductor packaging glass substrate, a semiconductor packaging substrate, a semiconductor device, and the like, which can be used to manufacture a more integrated semiconductor device by applying a stress-adjustable glass substrate.

[0012] Means used to solve problems

[0013] To achieve the above object, a semiconductor encapsulation glass substrate according to one embodiment includes: a glass substrate having a first surface and a second surface facing each other; and a plurality of core through holes penetrating the glass substrate in a thickness direction.

[0014] The blank line is a straight line connecting positions where the core through-hole is not formed on the first surface of the glass substrate.

[0015] The through-hole line is a straight line connecting positions where the core through-holes are formed on the first surface of the glass substrate.

[0016] Assuming that P is the stress difference value measured on the same glass substrate, the above P is a value based on the first formula, and the above P is 1.5 MPa or less,

[0017] Formula 1: P = Vp-Np

[0018] In formula 1,

[0019] Vp is the difference between the maximum and minimum stress values measured on the through-hole line.

[0020] Np is the difference between the maximum and minimum stress values measured on the blank line.

[0021] The value of Vp may be 2.5 MPa or less.

[0022] The value of Np may be 1.0 MPa or less.

[0023] Based on a unit area (1 cm×1 cm) of the glass substrate, 100 to 3000 core through holes may be provided.

[0024] Assuming that K is the stress difference ratio measured on the same surface of the same glass substrate, the above K is a value based on the second formula, and the above K can be 6 or less.

[0025] Formula 2: K = Lp / La

[0026] In formula 2,

[0027] The above Lp is the difference between the maximum and minimum stress values measured on the target line.

[0028] The above-mentioned La is an average value of stress measured on the above-mentioned target line.

[0029] The target line may be a blank line, and the stress difference ratio K of the semiconductor encapsulation glass substrate may be 2 or less.

[0030] The target line may be a via line, and the stress difference ratio K of the semiconductor package glass substrate may be 6 or less.

[0031] Based on a unit area (1 cm×1 cm) of the glass substrate, 100 to 3000 core through holes may be provided.

[0032] To achieve the above-mentioned object, according to another embodiment, a semiconductor packaging glass substrate includes: a glass substrate having a first surface and a second surface facing each other, and a plurality of core through holes penetrating the glass substrate in the thickness direction; a through hole line is a straight line formed by connecting positions where the core through holes are formed on the first surface of the glass substrate, Vp is the difference between the maximum and minimum stress values measured on the through hole line, and the Vp value of the glass substrate is greater than or equal to 0.2 MPa and less than or equal to 2.5 MPa. The core through hole includes: a first opening portion connected to the first surface, a second opening portion connected to the second surface, and a minimum inner diameter portion, the minimum inner diameter portion being the region with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion, and when the total length of the core through hole is defined as 100%, the minimum inner diameter portion is located at a position between 45% and 55% with respect to the first opening portion.

[0033] In order to achieve the above-mentioned purpose, according to another embodiment, a semiconductor packaging glass substrate includes: a glass substrate having a first surface and a second surface facing each other, and a plurality of core through holes penetrating the above-mentioned glass substrate in the thickness direction; a blank line is a straight line formed by connecting positions on the first surface of the above-mentioned glass substrate where the above-mentioned core through holes are not formed, Np is the difference between the maximum value and the minimum value of the stress measured on the above-mentioned blank line, and the value of the above-mentioned Np is greater than 0.2 MPa and less than 1.0 MPa, and the above-mentioned core through hole includes: a first opening portion connected to the above-mentioned first surface, a second opening portion connected to the above-mentioned second surface, and a minimum inner diameter portion, the above-mentioned minimum inner diameter portion is the area with the narrowest inner diameter in the entire core through hole connecting the above-mentioned first opening portion and the above-mentioned second opening portion, and when the total length of the above-mentioned core through hole is defined as 100%, the above-mentioned minimum inner diameter portion is located at a position between 45% and 55% with the above-mentioned first opening portion as a reference.

[0034] In order to achieve the above-mentioned purpose, according to another embodiment, a semiconductor packaging substrate includes: a glass substrate for semiconductor packaging as described above, and a core layer located on the surface of the above-mentioned core through hole; the above-mentioned core layer includes a core seed layer that becomes a seed crystal for forming a conductive layer or a core distribution layer as a conductive layer.

[0035] In order to achieve the above-mentioned purpose, a semiconductor device according to another embodiment includes: a semiconductor element portion, including one or more semiconductor elements; a packaging substrate, electrically connected to the above-mentioned semiconductor element portion; and a motherboard, electrically connected to the above-mentioned packaging substrate, transmitting external electrical signals to the above-mentioned semiconductor elements and connecting the above-mentioned semiconductor elements and the external electrical signals, and the above-mentioned packaging substrate is the packaging substrate described above.

[0036] Effects of the Invention

[0037] The semiconductor encapsulation glass substrate, semiconductor encapsulation substrate, and semiconductor device of this embodiment transmit electrical signals over the shortest possible distance by connecting the semiconductor element and the motherboard more closely, thereby significantly improving electrical characteristics such as signal transmission speed.

[0038] In addition, since the glass substrate used as the core of the substrate itself is an insulator, there is almost no possibility of parasitic elements occurring compared to the existing silicon core, which can further simplify the insulating film processing process and can be applied to high-speed circuits.

[0039] Furthermore, compared to the manufacture of silicon circular wafers, glass substrates are manufactured in the form of large panels, so mass production is relatively easy and economic efficiency can be further improved.

[0040] In this embodiment, a glass substrate with adjusted stress is used, so that even if a core through hole is formed, excellent mechanical properties can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 In the figure, part (a) is a schematic diagram showing a glass substrate having a core through hole applied in an embodiment of the present invention as viewed from the top, and part (b) is a schematic diagram illustrating a cross section of the core through hole.

[0042] Figure 2 Schematic diagram illustrating the stress measurement method of the present invention, wherein part (a) shows the stress measurement path of the through-hole line, and part (b) shows the stress measurement path of the blank line.

[0043] Figure 3 FIG. 1 is a schematic diagram illustrating a cross section of a semiconductor device according to an embodiment of the present invention.

[0044] Figure 4FIG. 1 is a schematic diagram illustrating a cross section of a package substrate according to another embodiment of the present invention.

[0045] Figure 5 and Figure 6 Each of them is a detailed schematic diagram illustrating a portion of a cross section of a package substrate according to an embodiment of the present invention (a circle indicates a shape viewed from the top or bottom).

[0046] Figures 7 to 9 FIG. 1 is a flow chart illustrating a cross-sectional view of a process for manufacturing a package substrate according to an embodiment. DETAILED DESCRIPTION

[0047] Below, embodiments of the present invention are described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in a variety of different embodiments and is not limited to the embodiments described herein. Throughout the text, the same reference numerals represent similar parts.

[0048] In this specification, the term "combination thereof" included in the Markush-type description refers to a mixture or combination of one or more components selected from the group consisting of multiple components of the Markush-type description, thereby indicating that one or more components selected from the group consisting of the above multiple components are included.

[0049] In this specification, unless otherwise specified, terms such as "first," "second," or "A," "B," etc. are used to distinguish the same terms from each other. Also, a singular expression may include a plural expression as long as it represents a meaning that is completely different from the context.

[0050] In the present specification, the “~” group may mean that a compound equivalent to “~” or a derivative of “~” is included in the compound.

[0051] In this specification, "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer sandwiched between A and B, and is not limited to the meaning that B is located on A in direct contact with the surface of A.

[0052] In this specification, the meaning of A being connected to B means that A and B are directly connected or connected through other constituent elements between A and B, and unless otherwise specified, the interpretation is not limited to A and B being directly connected.

[0053] In this specification, unless otherwise specified, an expression in the singular may be construed as including a meaning in the singular or plural as read from the context.

[0054] During the development of a more integrated semiconductor device capable of delivering high performance in a thinner form factor, the inventors recognized that not only the components themselves but also the packaging itself is a significant factor in improving performance. Furthermore, the inventors determined that, unlike conventional interposers and organic substrates, which use a two- or more-layered core as a packaging substrate on a motherboard, by using a single glass core and controlling the shape of the through-holes and the conductive layer formed thereon, the packaging substrate can be made thinner and contribute to improved electrical characteristics of the semiconductor device.

[0055] When forming a core through-hole in a thin glass substrate, localized stress concentration is likely to occur during processing, potentially weakening mechanical properties. This is a major factor in reducing workability during the complex packaging substrate manufacturing process. This embodiment provides a packaging substrate that utilizes a glass substrate with controlled stress concentration.

[0056] Figure 1 In the figure, part (a) is a schematic diagram of a glass substrate having a core through hole applicable in an embodiment of the present invention observed from the top, and part (b) is a schematic diagram illustrating a cross section of the core through hole. Figure 2 Schematic diagram illustrating the stress measurement method of the present invention, wherein (a) shows the stress measurement path of the through-hole line, and (b) shows the stress measurement path of the blank line. Figure 3 FIG. 1 is a schematic diagram illustrating a cross section of a semiconductor device according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating a cross section of a package substrate according to another embodiment of the present invention. Figure 5 and Figure 6 Detailed schematic diagrams illustrating a portion of a cross section of a package substrate according to an embodiment of the present invention (circles indicate shapes viewed from the top or bottom). Figure 1 and Figure 2 For a more detailed description of the semiconductor package substrate, refer to Figures 3 to 6 The package substrate and the semiconductor device are described in more detail.

[0057] To achieve the above-mentioned purpose, the semiconductor package substrate 215 according to the present embodiment includes a glass substrate 21 , a core through hole 23 , and a core layer 22 .

[0058] The glass substrate 21 has a first surface 213 and a second surface 214 facing each other.

[0059] The core through hole 23 penetrates the glass substrate in the thickness direction, and a plurality of core through holes are arranged on the glass substrate.

[0060] A core seed layer or core distribution pattern 241 is provided on the core layer 22 .

[0061] The core seed layer is located on the surface of the core through-hole and becomes a seed for forming the conductive layer.

[0062] The core distribution pattern 241 is a conductive layer located on the surface of the core through-hole.

[0063] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0064] The thickness of the glass substrate 21 may be 1,000 μm or less. The thickness of the glass substrate 21 may be 100 μm to 1,000 μm, or may be 100 μm to 700 μm. The thickness of the glass substrate 21 may be 100 μm to 500 μm.

[0065] Forming a thinner package substrate is beneficial for more efficient transmission of electrical signals. However, since the glass substrate also needs to play the role of supporting the semiconductor element, it is preferably of the above thickness.

[0066] The thickness of the glass substrate refers to the thickness of the glass substrate itself minus the thickness of the conductive layer on the glass substrate.

[0067] The core through hole 23 may be formed by removing a predetermined region of the glass substrate 21 , and specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0068] When forming the core through hole 23 , a method of forming a defect (stain) on the surface of the glass substrate by laser or the like and then performing chemical etching or laser etching may be used, but the present invention is not limited thereto.

[0069] The stress of the glass substrate 21 can be measured on the blank lines and the through-hole lines.

[0070] The blank line is a straight line connecting positions where the core through-holes 23 are not formed on the first surface 213. The through-hole line is a straight line connecting positions where the core through-holes 23 are formed on the first surface 213.

[0071] The stress difference P is expressed by the first formula.

[0072] The stress difference value P of the glass substrate 21 is 1.5 MPa or less.

[0073] Formula 1: P = Vp-Np

[0074] In Formula 1, Vp is the difference between the maximum and minimum stress values measured on the via line, and Np is the difference between the maximum and minimum stress values measured on the blank line.

[0075] The P value of the glass substrate may be 1.35 MPa or less. The P value of the glass substrate may be 1.2 MPa or less, or may be 1.1 MPa or less. The P value of the glass substrate may be 0.01 MPa or more. The P value of the glass substrate may be 0.1 MPa or more.

[0076] When the glass substrate having the above stress difference value P is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0077] The Vp value of the glass substrate may be 2.5 MPa or less. The Vp value of the glass substrate may be 2.3 MPa or less, and the above Vp value may be 2.0 MPa or less. The Vp value of the glass substrate may be 1.8 MPa or less. The Vp value of the glass substrate may be 0.2 MPa or more. The Vp value of the glass substrate may be 0.4 MPa or more.

[0078] When a glass substrate having a difference Vp between the maximum and minimum stress values measured at a through-hole line within the above range is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0079] The Np value of the glass substrate may be 1.0 MPa or less. The Np value of the glass substrate may be 0.9 MPa or less, or 0.8 MPa or less. The Np value of the glass substrate may be 0.1 MPa or more. The Np value of the glass substrate may be 0.2 MPa or more.

[0080] When a glass substrate having a difference Np between the maximum and minimum stress values measured on a blank line within the above range is applied to a semiconductor package substrate, a package substrate having more stable mechanical properties can be manufactured.

[0081] The stress difference ratio K is expressed by the second formula.

[0082] The target line is one selected from a blank line that is a straight line connecting positions where no core through-holes are formed, or a through-hole line that is a straight line connecting positions where core through-holes are formed.

[0083] The stress difference ratio K of the glass substrate may be 6 or less.

[0084] Formula 2: K = Lp / La

[0085] In Formula 2, K is the stress difference ratio measured on the same surface of the same glass substrate, Lp is the difference between the maximum and minimum stress values measured on the target line, and La is the average value of the stress measured on the target line.

[0086] The K value of the glass substrate may be 5 or less. The K value of the glass substrate may be 4.5 or less, or 4 or less. When a glass substrate having such a K value is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0087] The stress difference ratio measured at the blank line is represented by Kn.

[0088] The stress difference ratio Kn on the blank line may be less than 2. The stress difference ratio Kn on the blank line may be less than 1.8. The stress difference ratio Kn on the blank line may be greater than 0.3. The stress difference ratio Kn on the blank line may be greater than 0.5.

[0089] The stress difference ratio measured at the via line is represented by Kv.

[0090] The stress difference ratio Kv at the via line may be 6 or less. The stress difference ratio Kv at the via line may be 5 or less. The stress difference ratio Kv at the via line may be 4.5 or less, or may be 3 or less. The stress difference ratio Kv at the via line may be 0.5 or more. The stress difference ratio Kv at the via line may be 1.0 or more, or may be 1.5 or more.

[0091] When a glass substrate having the above Kn and Kv is applied to a semiconductor package substrate, a package substrate having more stable mechanical and physical properties can be manufactured.

[0092] The stress is analyzed by using a birefringence two-dimensional evaluation device. Specifically, a WPA-200 device manufactured by NPM (Nippon Pulse Korea Co., LTD) can be used as a birefringence two-dimensional distribution evaluation device.

[0093] For example, when using the probe along Figure 2 When reading data on a glass substrate using the stress measurement path shown in , measured values such as birefringence are input to the above-mentioned device, and then the stress in the measurement path is expressed in pressure units (e.g., MPa) through a predetermined calculation process.

[0094] At this time, the stress can be measured by inputting the photoelastic coefficient and the thickness of the object to be measured. In the embodiment, 2.4 is used as the photoelastic coefficient value.

[0095] Based on the unit area (1 cm×1 cm) of the glass substrate 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the above spacing conditions are met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate can be improved.

[0096] The core through holes 23 may be provided at a pitch of 1.2 mm or less, or at a pitch of 0.12 mm to 1.2 mm, or at a pitch of 0.3 mm to 0.9 mm on the glass substrate 21. In this case, while maintaining the mechanical properties of the glass substrate at or above a predetermined level, it is advantageous to form a conductive layer, etc.

[0097] The core through hole 23 includes: a first opening portion 233, which is connected to the above-mentioned first surface; a second opening portion 234, which is connected to the second surface; and a minimum inner diameter portion 235, which is the area with the narrowest inner diameter in the entire core through hole connecting the above-mentioned first opening portion and the above-mentioned second opening portion.

[0098] The diameter CV1 of the first opening and the diameter CV2 of the second opening may be substantially different. The diameter CV1 of the first opening and the diameter CV2 of the second opening may be substantially the same.

[0099] The core through hole 23 may have an inner diameter smaller at any location on the inner diameter surface connecting the first opening and the second opening than at other locations, and this portion is referred to as a minimum inner diameter.

[0100] The minimum inner diameter portion may be located at the first opening portion or the second opening portion, in which case the core through hole may be cylindrical or (trimmed) triangular pyramidal core through hole. In this case, the diameter CV3 of the minimum inner diameter portion corresponds to the smaller diameter between the first opening portion and the second opening portion.

[0101] The minimum inner diameter portion may be located between the first opening and the second opening, in which case the core through hole may be a barrel-shaped core through hole. In this case, the diameter CV3 of the minimum inner diameter portion may be smaller than the larger diameter of the first opening and the second opening.

[0102] The first surface opening diameter and the second surface opening diameter may be relatively constant across the entire glass substrate 21. Furthermore, the inner diameter (minimum inner diameter) of the core through hole at its narrowest portion may be relatively constant across the entire glass substrate 21.

[0103] The average diameter of the minimum inner diameter may be 50 μm to 95 μm.

[0104] The above minimum inner diameter can satisfy the condition of the following formula (3).

[0105] Formula 3: 0.83 × D 90 ≤D 50 ≤1.25×D 10

[0106] In the above formula 3, D 50 D is the value corresponding to 50% in the diameter distribution of the smallest inner diameter.90 D is the value corresponding to 90% of the diameter distribution at the minimum inner diameter. 10 This is a value corresponding to 10% in the diameter distribution of the smallest inner diameter.

[0107] The minimum inner diameter may have an average diameter of 55 μm to 85 μm, or may have an average diameter of 60 μm to 70 μm.

[0108] The above minimum inner diameter can satisfy the conditions of the following formula 3-1.

[0109] Formula 3-1: 0.88 × D 90 ≤D 50 ≤1.18×D 10

[0110] In the above formula 3-1, D 50 D is the value corresponding to 50% in the diameter distribution of the smallest inner diameter. 90 D is the value corresponding to 90% of the diameter distribution at the minimum inner diameter. 10 This is a value corresponding to 10% in the diameter distribution of the smallest inner diameter.

[0111] The average diameter of the target openings, which is the larger diameter of the first surface opening diameter and the second surface opening diameter, may be 70 μm to 120 μm.

[0112] The target opening, which is the larger diameter of the first surface opening diameter and the second surface opening diameter, may satisfy the condition of the following formula 4.

[0113] Formula 4: 0.9 × D 90 ≤D 50 ≤1.1×D 10

[0114] In the above formula 4, D 50 D is the value corresponding to 50% of the diameter distribution of the target opening. 90 D is the value corresponding to 90% of the diameter distribution of the target opening. 10 This is a value corresponding to 10% in the diameter distribution of the target openings.

[0115] The average diameter of the target openings, which is the larger diameter of the first surface opening diameter and the second surface opening diameter, may be 80 μm to 105 μm.

[0116] The target opening, which is the larger diameter of the first surface opening diameter and the second surface opening diameter, may satisfy the condition of the following formula 4-1.

[0117] Formula 4-1: 0.92×D 90 ≤D 50≤1.08×D 10

[0118] In the above formula 4-1, D 50 D is the value corresponding to 50% of the diameter distribution of the target opening. 90 D is the value corresponding to 90% of the diameter distribution of the target opening. 10 This is a value corresponding to 10% in the diameter distribution of the target openings.

[0119] In the core through hole, the average diameter of the target opening, which is the larger diameter of the first surface opening diameter that is the diameter of the opening that contacts the first surface and the second surface opening diameter that is the diameter of the opening that contacts the second surface, may be greater than the value D corresponding to 50% of the diameter distribution of the target openings. 50 Large value.

[0120] As for the diameter distribution described above, the prepared sample was divided into 9 areas (3×3), and samples were taken from 5 areas: upper left, lower left, center, upper right and lower right. After cutting, the cross-section was observed under a microscope to measure the diameter, and the above-mentioned diameter distribution was evaluated based on this diameter.

[0121] When the total length G21 of the core through hole is defined as 100%, the position of the minimum inner diameter portion can be located at a position G23 between 40% and 60% of the reference, or between 45% and 55% of the reference, based on the first opening portion. As described above, when the minimum inner diameter portion is located at the above position based on the total length of the core through hole, the conductive layer design and conductive layer formation process of the package substrate can be more easily implemented.

[0122] The angle Ca1 between the inner diameter of the minimum inner diameter portion and the inner diameter surface of the first opening and the angle Ca2 between the inner diameter of the minimum inner diameter portion and the inner diameter surface of the second opening can have a ratio of 1:0.7 to 1.3. In this case, the difference in angle between the inner diameter surface of the core through hole from the first opening and the inner diameter surface of the core through hole from the second opening is minimal, so that subsequent plating steps, etc., can be performed more smoothly.

[0123] The angle is evaluated as an angle relative to an imaginary reference line perpendicular to the first surface or the second surface, and is evaluated as an absolute value regardless of direction (the same applies hereinafter).

[0124] The larger of the angles Ca1 connecting the inner diameter of the minimum inner diameter portion and the inner diameter surface of the first opening and Ca2 connecting the inner diameter of the minimum inner diameter portion and the inner diameter surface of the second opening may be 8 degrees or less, or 0.1 to 8 degrees, or 0.5 to 6.5 degrees. These angles can further improve the efficiency of subsequent processes such as plating.

[0125] The thickness of the conductive layer measured at the larger diameter of the first surface opening diameter CV1 and the second surface opening diameter CV2 may be equal to or greater than the thickness of the conductive layer formed on the portion CV3 having the smallest inner diameter in the core through hole.

[0126] The semiconductor device 100 and the package substrate 20 will be described in more detail.

[0127] In one embodiment, a semiconductor device 100 includes: a semiconductor element portion 30, one or more semiconductor elements 32, 34, and 36; a packaging substrate 20 electrically connected to the semiconductor elements; and a motherboard 10 electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor elements and connecting the semiconductor elements to the external electrical signals.

[0128] A package substrate 20 according to another embodiment includes a core layer 22 and an upper layer 26 .

[0129] The core layer 22 includes the semiconductor package substrate 215 described above.

[0130] The semiconductor element portion 30 is a component mounted on a semiconductor device and is mounted on the package substrate 20 via connection electrodes and the like. Specifically, examples of the semiconductor element portion 30 include computing elements such as a CPU and a GPU (first element 32, second element 34), and storage elements such as a memory chip (third element 36). However, any semiconductor element mounted on a semiconductor device is applicable without limitation.

[0131] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0132] The package substrate 20 includes a core layer 22 and an upper layer 26 located on one surface of the core layer.

[0133] The package substrate 20 may selectively further include a lower layer 29 located below the core layer.

[0134] The core layer 22 includes a glass substrate 21, a plurality of core through holes 23 penetrating the glass substrate in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate or the core through holes, including a conductive layer, at least a portion of which electrically connects the conductive layer on the first surface and the conductive layer on the second surface through the core through holes.

[0135] The glass substrate 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the entire glass substrate has a predetermined thickness.

[0136] A core through hole 23 penetrating the first surface and the second surface is located in the glass substrate 21 .

[0137] Traditionally, semiconductor device packaging substrates have employed a stacked structure of silicon and organic substrates. Due to the properties of semiconductors, silicon substrates can exhibit parasitic elements when used in high-speed circuits, leading to relatively high power losses. Furthermore, organic substrates require larger areas to form more complex patterns, but this is inconsistent with the trend toward ultra-miniaturized electronic device manufacturing. Forming complex patterns within a predetermined size requires substantial pattern miniaturization, but this is limited by the properties of materials such as polymers used for organic substrates.

[0138] In this embodiment, as a method for solving the above-mentioned problems, a glass substrate 21 is used as a support for the core layer 22. In addition, a core through hole 23 formed through the glass substrate is also used together with the glass substrate, thereby providing a package substrate 20 with shorter current length, more compact size, faster response, and less loss characteristics.

[0139] The core distribution layer 24 includes a core distribution pattern 241 and a core insulating layer 223 .

[0140] The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass substrate through core through-holes.

[0141] The core insulating layer 223 surrounds the core distribution pattern 241 .

[0142] A conductive layer is formed inside the core layer 22 through the core through-hole to serve as an electrical path across the glass substrate 21, thereby connecting the upper and lower parts of the glass substrate at a relatively short distance, which can have faster electrical signal transmission and low loss characteristics.

[0143] The core distribution pattern 241 is a pattern for electrically connecting the first surface 213 and the second surface 214 of the glass substrate through the core through-hole 23 .

[0144] The core distribution pattern 241 includes a first surface distribution pattern 241 a , a second surface distribution pattern 241 c , and a core through hole distribution pattern 241 b .

[0145] The first surface distribution pattern 241a is a conductive layer located on at least a portion of the first surface 213. The second surface distribution pattern 241c is a conductive layer located on at least a portion of the second surface 214. The core via distribution pattern 241b is a conductive layer that electrically connects the first surface distribution pattern and the second surface distribution pattern via the core via 23.

[0146] For example, the conductive layer may be a copper-plated layer, but the present invention is not limited thereto.

[0147] The glass substrate 21 plays an intermediate role and / or mediating role in connecting the semiconductor element of the semiconductor element portion 30 and the motherboard 10 to the upper and lower parts, respectively. The core through hole 23 serves as a path for transmitting their electrical signals, thereby achieving smooth signal transmission.

[0148] The thickness of the conductive layer measured at the larger diameter of the first surface opening diameter and the second surface opening diameter may be equal to or greater than the thickness of the conductive layer formed at a portion having the smallest inner diameter in the core through-hole.

[0149] The core distribution layer 24 is a conductive layer formed on a glass substrate, and its adhesion test value according to ASTM D3359 (Cross Cut Adhesion Test) can meet 4B or higher. For example, the adhesion test value of the core distribution layer 24 can meet 5B or higher. Furthermore, the conductive layer serving as the core distribution layer 24 can have an adhesion strength of 3N / cm or higher, or 4.5N / cm or higher, to the glass substrate. When the above adhesion strength is met, sufficient adhesion between the substrate and the conductive layer is achieved for use as a packaging substrate.

[0150] The upper layer 26 is located on the first surface 213 .

[0151] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer. The uppermost layer 26 may be protected by a cover layer 60 having an opening formed therein for direct contact of the connection electrodes of the semiconductor element.

[0152] The upper distribution layer 25 includes an upper insulating layer 253 on the first surface and an upper distribution pattern 251 which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24. The upper distribution pattern 251 is embedded in the upper insulating layer.

[0153] The upper insulating layer 253 may be any insulating layer suitable for use with a semiconductor element or a package substrate. For example, epoxy resin containing a filler may be used, but the present invention is not limited thereto.

[0154] The above-mentioned insulator layer can be formed by forming a coating and curing it, or can be formed by laminating an insulator film formed in an uncured or semi-cured state on the above-mentioned core layer and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the above-mentioned insulator is embedded in the space inside the core through-hole, so that the process can be carried out efficiently. In addition, even if multiple insulator layers are stacked for application, it may be substantially difficult to distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 can be made of the same insulating material, in which case their boundaries may be substantially indistinguishable.

[0155] The upper distribution pattern 251 is a conductive layer located within the upper insulating layer 253 in a predetermined shape and can be formed, for example, by a build-up layer method. Specifically, after forming an insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating. Unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer. Unnecessary portions are again removed, and then a conductive layer is formed by a method such as plating. This process is repeated to form the upper distribution pattern 251 having a conductive layer formed in a desired pattern in the vertical or horizontal direction.

[0156] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30 and is therefore formed to include a fine pattern in at least a portion thereof to facilitate smooth transmission of electrical signals between the core layer 22 and the semiconductor element portion 30 and to fully accommodate the required complex pattern. In this case, the fine pattern refers to a pattern having a width and spacing of less than approximately 4 μm, or a pattern having a width and spacing of less than approximately 3.5 μm, or a pattern having a width and spacing of less than approximately 3 μm, or a pattern having a width and spacing of less than approximately 2.5 μm, or a pattern having a width and spacing of approximately 1 μm to approximately 2.3 μm. The above-mentioned spacing may be the spacing between adjacent fine patterns (the same description of the fine pattern will be given below).

[0157] In order to form the upper distribution pattern 251 including a fine pattern, at least two or more methods are applied in this embodiment.

[0158] As one method, glass is used as the packaging substrate material of the glass substrate 21. The glass substrate 21 can have a relatively flat surface with a surface roughness Ra of 10 angstroms or less, thereby minimizing the influence of the surface morphology of the support substrate on the formation of fine patterns.

[0159] Another method lies in the characteristics of the above-mentioned insulator. The above-mentioned insulator is usually applied with a filler component together with a resin, and the above-mentioned filler can be inorganic particles such as silica particles. When inorganic particles are applied as fillers to the insulator, the size of the inorganic particles may affect whether a fine pattern can be formed. In this embodiment, the insulator applicable is a granular filler with an average diameter of about 150nm or less, specifically, including a granular filler with an average diameter of about 1nm to about 100nm. The above-mentioned characteristics keep the physical properties required by the insulator above the specified level, and minimize the influence of the insulator itself on the formation of a conductive layer with a width of microns, and also help to form a fine pattern with excellent adhesion on its surface with a fine surface morphology.

[0160] The upper connection layer 27 includes an upper connection pattern 272 and an upper connection electrode 271 .

[0161] At least a portion of the upper connection pattern 272 is electrically connected to the upper distribution pattern 251 , and the upper connection pattern 272 is located on the upper insulating layer 253 . The upper connection electrode 271 electrically connects the semiconductor element portion 30 and the upper connection pattern 272 .

[0162] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in such a manner that at least a portion thereof is exposed on the upper insulating layer. For example, when the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by a method such as plating. For example, when the upper connection pattern is embedded in such a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching, or the like.

[0163] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above allows for electrical connection of more components even in a narrow area, thereby facilitating smoother electrical signal connections between components or with the outside world and enabling a more integrated package.

[0164] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 through a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball or the like.

[0165] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution layer, namely the second surface distribution pattern 241c, located on at least a portion of the second surface 214 of the core layer 22, or the motherboard 10 can be electrically connected via board connectors such as solder balls. Furthermore, the second surface distribution pattern 241c can be connected to the motherboard 10 via a lower layer 29 located below the core layer 22.

[0166] The lower layer 29 includes a lower distribution layer 291 and a lower connection layer 292 .

[0167] The lower distribution layer 291 includes a lower insulating layer 291 b and a lower distribution pattern 291 a .

[0168] The lower insulating layer 291b is at least partially in contact with the second surface 214. The lower distribution pattern 291a is embedded (buried) in the lower insulating layer and has a predetermined pattern. At least a portion of the lower distribution pattern 291a is electrically connected to the core distribution layer.

[0169] Lower connection layer 292 may further include lower connection electrode 292a and / or lower connection pattern 292b. Lower connection electrode 292a is electrically connected to the lower connection pattern. At least a portion of lower connection pattern 292b is electrically connected to the lower distribution pattern, and at least a portion of lower connection pattern 292b is exposed on one side of the lower insulating layer.

[0170] Unlike the upper connection pattern 272 , the lower connection pattern 292 b may be formed as a non-fine pattern having a width greater than that of the fine pattern. In this case, electrical signals may be more efficiently transmitted to the portion connected to the motherboard 10 .

[0171] One of the features of the present invention is that, except for the glass substrate 21 , substantially no additional substrate is used in the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 .

[0172] Conventionally, an interposer and an organic substrate were stacked together to connect the component and the motherboard. This multi-stage approach is adopted for at least two reasons: one is the dimensional issues that arise when directly bonding the component's fine pattern to the motherboard, and another is the potential for wiring damage during the bonding process or when the semiconductor device is driven due to differences in thermal expansion coefficients. In this embodiment, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element is used, and a fine pattern with dimensions sufficiently fine to accommodate component mounting is formed on the first surface and upper layers of the glass substrate, thereby resolving these issues.

[0173] The semiconductor device 100 has a very thin package substrate 20, which can reduce the overall thickness of the semiconductor device, and by applying a fine pattern, the desired electrical connection pattern can be arranged even in a smaller area. Specifically, the thickness of the package substrate can be about 2000 μm or less, or about 1500 μm or less, or about 900 μm. In addition, the thickness of the package substrate can be about 120 μm or more, or about 150 μm or more. Through the features described above, the package substrate can stably connect the components and the motherboard electrically and structurally with a relatively thin thickness, and can further contribute to the miniaturization and thinning of the semiconductor device.

[0174] A method of preparing a package substrate according to another embodiment will be described.

[0175] The method for preparing a packaging substrate of the present embodiment includes the following steps to prepare the packaging substrate as described above: a preparation step of forming defects at predetermined positions on the first surface and the second surface of a glass substrate; an etching step of applying an etching liquid to the glass substrate on which the defects are formed to prepare a glass substrate having a core through-hole; a core layer preparation step of forming a core distribution layer as a conductive layer by plating the surface of the glass substrate having the core through-hole formed to prepare a core layer; and an upper layer preparation step of forming an upper distribution layer as a conductive layer surrounded by an insulating layer on one side of the core layer.

[0176] At this time, the shape of the defect is formed in consideration of the shape of the core through hole to be formed. By forming the core through hole in the etching step through the defect, it is possible to have excellent workability compared to forming a through hole in the organic substrate using a drill alone.

[0177] The core layer preparation step may include: a pretreatment process of forming an organic-inorganic composite primer layer including nanoparticles having an amino group on the surface of the glass substrate having the core through hole formed thereon to prepare a pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0178] The core layer preparation step may include: a pretreatment process of preparing a pretreated glass substrate by forming a metal-containing primer layer on the surface of the glass substrate having the core through hole formed thereon by sputtering; and a plating process of plating a metal layer on the pretreated glass substrate.

[0179] When forming the above-mentioned primer layer, dissimilar metals such as titanium, chromium, and nickel can be sputtered together with copper or alone. In this case, the adhesion between the glass and the metal is improved by the surface morphology of the glass and the anchoring effect of the interaction between the metal particles. Thereafter, it can act as a seed crystal in the plating process.

[0180] An insulating layer forming step may be further included between the core layer preparing step and the upper layer preparing step.

[0181] The insulating layer forming step may be a step of forming the core insulating layer by placing an insulating film on the core layer and then performing reduced pressure lamination.

[0182] The method of preparing the package substrate will be described in more detail.

[0183] 1) Preparation step (glass defect formation process): A glass substrate 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface in order to form a core through hole. The above-mentioned glass can be a glass substrate suitable for a substrate of an electronic device, for example, an alkali-free glass substrate, etc., but the present invention is not limited thereto. As commercially available products, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. When forming the above-mentioned defect (groove), methods such as mechanical etching and laser irradiation can be used.

[0184] 2) Etching Step (Core Through-Hole Forming Step): A core through-hole 23 is formed on the glass substrate 21a having the defect 21b (groove) formed therein through a physical or chemical etching process. During the etching process, the core through-hole is formed in the defect portion of the glass substrate 21a while the surface of the glass substrate 21a is etched simultaneously. To prevent this etching of the glass surface, a mask film or the like may be applied. However, given the complexity of applying and removing the mask film, the glass substrate with the defect itself may be etched. In this case, the thickness of the glass substrate with the core through-hole may be slightly thinner than the original glass substrate.

[0185] Chemical etching can be performed by placing the grooved glass substrate in a bath containing hydrofluoric acid and / or nitric acid and applying ultrasonic treatment. In this case, the hydrofluoric acid concentration can be 0.5M or more, or 1.1M or more. The hydrofluoric acid concentration can be 3M or less, or 2M or less. The nitric acid concentration can be 0.5M or more, or 1M or more. The nitric acid concentration can be 2M or less. The ultrasonic treatment can be performed at a frequency of 40 Hz to 120 Hz, or at a frequency of 60 Hz to 100 Hz.

[0186] When these conditions are applied, a glass substrate having improved workability while reducing residual stress on a glass substrate in which a core through-hole is formed can be prepared.

[0187] 3-1) Core layer preparation step: forming a conductive layer (core distribution layer 21d) on a glass substrate. Typically, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0188] The glass surface (including the surface of the glass substrate and the surface of the core through-hole) and the copper metal surface have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods: dry method and wet method.

[0189] The dry method is a method that applies sputtering, that is, a method in which a seed layer 21c is formed on the glass surface and the inner diameter of the core through-hole by sputtering a metal. When forming the seed layer, a dissimilar metal such as titanium, chromium, or nickel can be sputtered together with copper, etc. In this case, it is believed that the adhesion between the glass and the metal is improved due to the anchoring effect of the interaction between the surface morphology of the glass and the metal particles.

[0190] Wet method is the method for carrying out primer treatment, is by carrying out pre-treatment with the compound with the functional group such as amine etc. and forms the method for primer layer 21c.According to required adhesion degree, after carrying out pre-treatment with silane coupling agent, can carry out primer treatment with compound or particle with amine functional group.As mentioned above, the support substrate of present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, preferably being suitable for average diameter is the nanoparticle below 150nm, for example, has the particle of amino group and is preferably used as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion improver made by the CZ series etc. of MEC company.

[0191] In the seed layer / primer layer 21c, the conductive layer can be selectively formed into a metal layer, with or without removing portions where a conductive layer is not required. Furthermore, the seed layer / primer layer can selectively process portions where a conductive layer is required or not required to form a conductive layer into an activated or inactivated state for metal plating, allowing subsequent steps to proceed. For example, the activation or inactivation treatment can be performed using light irradiation with a laser having a predetermined wavelength, a chemical treatment, or the like. While the metal layer can be formed using a copper plating method suitable for manufacturing semiconductor devices, the present invention is not limited thereto.

[0192] During the metal plating, the thickness of the conductive layer formed can be controlled by adjusting various variables such as the concentration of the plating solution, the plating time, and the type of applicable additives.

[0193] When part of the core distribution layer is not needed, it can be removed, or the seed layer can be partially removed or inactivated and then metal plating can be performed to form a conductive layer in a predetermined pattern, thereby forming the etching layer 21e of the core distribution layer.

[0194] 3-2) Insulation Layer Formation Step: After forming the core distribution layer, which serves as the conductive layer, the core through-holes may be subjected to an insulation layer formation step in which the empty spaces are filled with an insulation layer. In this case, the insulation layer may be a thin film, for example, applied by a method such as vacuum lamination of a thin film. This vacuum lamination method allows the insulation layer to be fully embedded in the empty spaces within the core through-holes, forming a core insulation layer free of voids.

[0195] 4) Upper layer preparation step: This step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or stacking insulating films. Simply put, it is preferred to use a stacking insulating film method. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in the layer where no conductive layer is formed inside the core through hole, etc. At least a portion of the above-mentioned upper insulating layer is also in direct contact with the glass substrate, so a layer with sufficient adhesion is suitable. Specifically, the above-mentioned glass substrate and the above-mentioned upper insulating layer preferably have a characteristic of satisfying 4B or above in the adhesion test value according to ASTMD3359.

[0196] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the conductive layer. The blind holes 23b are formed in the insulating layer, with the conductive layer adjacent thereto, and then subjected to a plating process. The blind holes can be formed by dry etching methods such as laser etching and plasma etching, or by wet etching methods using a mask layer and an etching solution.

[0197] 5) Step of forming the upper connection layer and the covering layer: The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer 23f of the insulating layer on the insulating layer 23e, and then forming a conductive layer 23g thereon, and then forming an etching layer 23h of the conductive layer. However, it can also be formed by selectively forming only the conductive layer without using an etching method. The covering layer can be formed so that an opening (not shown in the figure) is formed at a position corresponding to the upper connection electrode, so that the upper connection electrode is exposed and directly connected to the element connection part or the terminal of the element.

[0198] 6) Lower connection layer and covering layer forming step: The lower distribution layer and / or lower connection layer can be formed by a method similar to the upper connection layer and covering layer forming step described above, and a covering layer (not shown in the figure) can be selectively formed.

[0199] Hereinafter, the present invention will be described in more detail by way of specific examples. The following examples are merely examples for helping to understand the present invention, and the scope of the present invention is not limited thereto.

[0200] <Example 1-Preparation of a substrate having a core through-hole>

[0201] 1) Preparation step (glass defect forming process): Prepare a glass substrate 21a having a flat first surface and a flat second surface, and form defects 21b (grooves) at predetermined positions on the glass surface in order to form a core through hole. At this time, as the number of defects mentioned above, the number of defects per 1 cm is 21. 2 225 or 1024 of the above defects are formed. Borosilicate glass is suitable as the above glass. The above defects (grooves) are formed by mechanical etching or laser irradiation.

[0202] 2) Etching step (core through-hole forming step): In the glass substrate 21a having the defect 21b (groove) formed therein, a core through-hole 23 is formed by a physical or chemical etching process. The etching is performed by placing the glass substrate in an etching bath filled with 2M hydrofluoric acid (HF), 1.1M nitric acid (HNO3), and deionized water and applying ultrasonic waves at 80 Hz and 100% power.

[0203] Furthermore, the core through hole is formed to include: a first opening portion connected to the first surface; a second opening portion connected to the second surface; and a minimum inner diameter portion, which is the area with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion.

[0204] <Example 2-Preparation of a Substrate with a Core Through-hole>

[0205] A substrate was prepared in the same manner as in Example 1 except that the ultrasonic power was changed to 80%.

[0206] <Example 3-Preparation of a substrate having a core through-hole>

[0207] The substrate was prepared in the same manner as in Example 1 above, except that the etching was performed by placing the glass substrate in an etching bath filled with 1.1 M hydrofluoric acid (HF), 1.1 M nitric acid (HNO3) and deionized water and applying ultrasonic waves at 80 Hz and 100% power.

[0208] <Example 4-Preparation of a Substrate with a Core Through-Hole>

[0209] A substrate was prepared in the same manner as in Example 3 except that the ultrasonic power was changed to 80% during etching.

[0210] <Experimental Example – Stress Measurement of Glass Substrate>

[0211] The stress is analyzed by using a birefringence two-dimensional evaluation device. As a birefringence two-dimensional distribution evaluation device, a WPA-200 device manufactured by NPM (Nippon Pulse Korea Co., LTD) can be used.

[0212] The stress of the blank lines and through-hole lines of four glass substrate samples was measured by changing the position more than four times. The average diameter of the opening of the glass substrate sample was 100 μm, the average diameter of the minimum inner diameter was 75 μm, and the average thickness was about 300 μm. 2 ) forms approximately 225 or 1024 core through holes.

[0213] Specifically, when the probe is used along Figure 2 When reading data on a glass substrate using the stress measurement path shown in the figure, measured values such as birefringence are input to the device described above. Then, through a predetermined calculation process, the stress in the measurement path is expressed in pressure units (e.g., MPa). A value of 2.4 is used as the photoelastic coefficient, and 300 μm is used as the thickness.

[0214] The averages of the measurement results are shown in Tables 1 and 2 below, respectively. The Vp, Np, P values and the like evaluated using the averages are also shown in Tables 1 and 2 below, respectively.

[0215] <Preparation Example - Preparation of Package Substrate>

[0216] 3-1) Core layer preparation step: A conductive layer (core distribution layer 21d) is formed on a glass substrate. The conductive layer may be a metal layer including copper. A titanium-containing sputtering layer is formed and copper plating is performed.

[0217] 3-2) Insulation Layer Formation Step: After forming the core distribution layer serving as the conductive layer, the insulating layer is then filled with an insulating layer to form the void space. The insulating layer may be a film-formed insulating layer, which may be applied by laminating the film-formed insulating layer under reduced pressure.

[0218] 4) Upper Layer Preparation Step: An upper distribution layer comprising an upper insulating layer and an upper distribution pattern is formed on the core layer. The upper insulating layer is formed by stacking insulating films, which are laminated and cured. At least a portion of the upper insulating layer is in direct contact with the glass substrate, so a layer with sufficient adhesion is suitable. Specifically, the glass substrate and the upper insulating layer preferably have adhesion properties that meet 4B or higher according to ASTM D3359.

[0219] The upper distribution pattern is formed by repeatedly forming the aforementioned insulating layer 23a, forming a conductive layer 23c in a predetermined pattern, and etching away unnecessary portions to form an etched layer 23d of the conductive layer. Blind holes 23b are formed in the insulating layer with the conductive layer formed adjacent thereto, followed by a plating process. The package substrate is prepared by forming the blind holes using dry etching methods such as laser etching and plasma etching, as well as wet etching using a mask layer and an etching solution.

[0220] The samples suitable for preparation were all formed into packaging substrates in an undamaged state.

[0221] Table 1

[0222]

[0223]

[0224] Table 2

[0225]

[0226]

[0227] Referring to Tables 1 and 2 above, glass substrates with the aforementioned residual stresses in both the blank lines and the via lines are sufficiently processable for use as package substrates. The smaller the stress difference, the more stable the subsequent process steps, and at the levels confirmed above, they all exhibit suitable processability. Although the data is not clearly shown above, samples in which cracks were formed and then etched in a strong acid environment without ultrasonic application exhibited damage during sputtering or insulating layer formation, confirming the need for simultaneous ultrasonic application during etching.

[0228] As described above, although the preferred embodiments of the present invention have been described in detail, it should be understood that the scope of the present invention is not limited to the above embodiments, and various changes or modifications by those skilled in the art using the basic concepts of the present invention defined in the claims fall within the scope of the present invention.

[0229] Description of Reference Numerals

[0230] 100: Semiconductor device 10: Motherboard

[0231] 30: Semiconductor element portion 32: First semiconductor element

[0232] 34: Second semiconductor element 36: Third semiconductor element

[0233] 20: Package substrate 22: Core layer

[0234] 223: core insulating layer 21, 21a: glass substrate

[0235] 213: First surface 214: Second surface

[0236] 215: semiconductor package substrate 23: core through hole

[0237] 233: First opening 234: Second opening

[0238] 235: Minimum inner diameter portion 24: Core distribution layer

[0239] 241: Core distribution pattern 241a: First surface distribution pattern

[0240] 241b: core through-hole distribution pattern 241c: second surface distribution pattern

[0241] 26: Upper layer 25: Upper distribution layer

[0242] 251: Upper distribution pattern 252: Blind hole

[0243] 253: Upper insulation layer 27: Upper connection layer

[0244] 271: Upper surface connection electrode 272: Upper surface connection pattern

[0245] 29: Lower layer 291: Lower distribution layer

[0246] 291a: Lower distribution pattern 291b: Lower insulation layer

[0247] 292: bottom connection layer 292a: bottom connection electrode

[0248] 292b: bottom connection pattern 50: connection part

[0249] 51: Component connection part 52: Board connection part

[0250] 60: Covering layer 21b: Glass defect

[0251] 21c: Seed layer, primer layer 21d: Core distribution layer

[0252] 21e: Etching layer of core distribution layer 23a: Insulation layer

[0253] 23b: blind hole 23c: conductive layer

[0254] 23d: Etching layer of conductive layer 23e: Insulating layer

[0255] 23f: Etching layer of insulating layer 23g: Conductive layer

[0256] 23h: Etching layer of the conductive layer.

Claims

1. A semiconductor encapsulation glass substrate, characterized in that: include: A glass substrate having a first surface and a second surface facing each other, and a plurality of core through holes penetrating the glass substrate in a thickness direction; The through hole line is a straight line formed by connecting the positions where the core through holes are formed on the first surface of the glass substrate. Vp is the difference between the maximum and minimum stress values measured on the through-hole line. The Vp value of the glass substrate is 0.2 MPa or more and 2.5 MPa or less. The core through hole includes: The first opening is in contact with the first surface. The second opening is in contact with the second surface, and The minimum inner diameter portion is the area with the narrowest inner diameter in the entire core through hole connecting the first opening and the second opening. When the total length of the core through hole is defined as 100%, the minimum inner diameter portion is located at a position between 45% and 55% with respect to the first opening.

2. The semiconductor encapsulation glass substrate according to claim 1, wherein: The core through holes are provided on the glass substrate at a pitch of 1.2 mm or less.

3. The semiconductor encapsulation glass substrate according to claim 1, wherein: The average diameter of the minimum inner diameter portion is 50 μm to 95 μm.

4. The semiconductor encapsulation glass substrate according to claim 1, wherein The blank line is a straight line formed by connecting positions where the core through-hole is not formed on the first surface of the glass substrate. Np is the difference between the maximum and minimum stress values measured on the blank line. The value of Np is 1.0 MPa or less.

5. A semiconductor encapsulation glass substrate, characterized in that: include: A glass substrate having a first surface and a second surface facing each other, and a plurality of core through holes penetrating the glass substrate in a thickness direction; The blank line is a straight line formed by connecting positions where the core through-hole is not formed on the first surface of the glass substrate. Np is the difference between the maximum and minimum stress values measured on the blank line. The value of Np is 0.2 MPa or more and 1.0 MPa or less. The core through hole includes: The first opening is in contact with the first surface. The second opening is in contact with the second surface, and The minimum inner diameter portion is the area with the narrowest inner diameter in the entire core through hole connecting the first opening and the second opening. When the total length of the core through hole is defined as 100%, the minimum inner diameter portion is located at a position between 45% and 55% with respect to the first opening.

6. The semiconductor encapsulation glass substrate according to claim 5, wherein: The average diameter of the target openings, whichever has the larger diameter between the first opening and the second opening, is 70 μm to 120 μm.

7. The semiconductor encapsulation glass substrate according to claim 5, wherein: The glass substrate has a thickness of 100 μm to 1000 μm.

8. A semiconductor package substrate, characterized in that: include: The semiconductor encapsulation glass substrate according to claim 1 or claim 5, and a core layer, located on the surface of the core through hole; The core layer includes a core seed layer that becomes a seed for forming a conductive layer or a core distribution layer that becomes a conductive layer.

9. A semiconductor device, characterized in that: include: The semiconductor device portion includes one or more semiconductor devices. a package substrate electrically connected to the semiconductor element portion, and a motherboard electrically connected to the package substrate, transmitting external electrical signals to the semiconductor element and connecting the semiconductor element to the external electrical signals; The package substrate is the semiconductor package substrate according to claim 8.

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