Three-dimensional storage device and method for manufacturing the same

Abstract

The present invention discloses a three-dimensional memory device and a manufacturing method thereof, comprising a substrate and a memory stacking structure. The memory stacking structure is arranged on the substrate, and comprises a plurality of stacking units stacked in order from bottom to top in a stepped shape, wherein each stacking unit has a step slope, and the step slope of any stacking unit arranged at the bottom is greater than the step slope of any stacking unit arranged at the top. Thus, the structural integrity of the three-dimensional memory device can be optimized, thereby improving the component performance thereof.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a three-dimensional storage device and a manufacturing method thereof. Background Art

[0002] In modern electronic products, memory plays an indispensable and important role. In addition to storing user data, memory is also responsible for storing the program code executed by the central processing unit and the information that needs to be temporarily saved during the operation process. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). Their data will disappear after power failure and must be re-entered when power is next supplied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in them still exists even if the power is cut off, so the valid data stored earlier can be directly read after power is restored.

[0003] NAND flash memory is currently the most widely used non-volatile memory due to its small size, low power consumption, fast writing speed and low manufacturing cost. With the advancement of semiconductor manufacturing technology, NAND flash memory has shifted from a planar structure to a three-dimensional (3D) stacking structure to achieve higher cell density per unit wafer area to meet the demand for higher storage capacity.

[0004] A three-dimensional NAND memory device generally includes a staircase structure formed on one or more sides of a memory stack structure to fan out each layer of wordline to electrically connect to an interconnect structure (e.g., a wordline contact plug). However, as the number of levels of the memory stack structure gradually increases, the related manufacturing process and device structure must be further improved to maintain good device performance under the premise of simplifying the manufacturing process. Summary of the invention

[0005] The present invention aims to provide a three-dimensional memory device and a method for manufacturing the same, which comprises a plurality of stacking units with inclined side walls stacked in sequence into a stepped structure, wherein the step slope of the side walls of each stacking unit gradually decreases with the stacking sequence from top to bottom, so that the insulating layer with poor hole filling ability can be more completely and evenly covered on each stacking unit, avoiding the formation of discontinuously covered film layers or faults to expose the conductor layer. Under this arrangement, the influence of the side erosion effect of the conductor layer on the insulating layer arranged above it can be effectively improved, the structural integrity of the insulating layer can be improved, the protective effect of the insulating layer on each conductor layer can be improved, and the performance of the three-dimensional memory device components can be improved.

[0006] An embodiment of the present invention provides a three-dimensional memory device, comprising a substrate and a memory stacking structure. The memory stacking structure is arranged on the substrate, and the memory stacking structure comprises a plurality of stacking units stacked in sequence from bottom to top in a stepped shape, wherein each of the stacking units has a step slope, and the step slope of any stacking unit arranged at the bottom is greater than the step slope of any stacking unit arranged at the top.

[0007] Another embodiment of the present invention provides a method for manufacturing a three-dimensional memory device, comprising the following steps. First, a substrate is provided, and then a memory stacking structure is formed on the substrate. The memory stacking structure comprises a plurality of stacking units stacked in sequence from bottom to top in a stepped shape, wherein each of the stacking units has a step slope, and the step slope of any stacking unit arranged at the bottom is greater than the step slope of any stacking unit arranged at the top. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 3 FIG. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment of the present invention, wherein:

[0010] Figure 1 is a top view schematic diagram of a three-dimensional storage device;

[0011] Figure 2 for Figure 1 A schematic cross-sectional view along the tangent line AA'; and

[0012] Figure 3 for Figure 2 A partially enlarged schematic diagram of .

[0013] Figure 4 FIG. 1 is a partially enlarged schematic diagram of a three-dimensional memory device according to another embodiment of the present invention.

[0014] Figure 5 FIG. 1 is a partially enlarged schematic diagram of a three-dimensional memory device according to another embodiment of the present invention.

[0015] Figures 6 to 11 The figure shows a schematic diagram of the steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention, wherein:

[0016] Figure 6 is a schematic top view of a three-dimensional memory device after a first etching process;

[0017] Figure 7 for Figure 6 Schematic diagram of the cross section along the tangent line A-A';

[0018] Figure 8 is a schematic top view of a three-dimensional memory device after a second etching process;

[0019] Fig. 9 for Figure 8 Schematic diagram of the cross section along the tangent line A-A';

[0020] Fig.10 is a schematic cross-sectional view of a three-dimensional memory device after a first etching process of a trim-etch process; and

[0021] Fig.11 It is a cross-sectional schematic diagram of a three-dimensional memory device after the second etching process of the trim-etch process.

[0022] The reference numerals are described as follows:

[0023] 100 Substrate

[0024] 110 cushion layer

[0025] 120 Conductor layer

[0026] 130 Dielectric layer

[0027] 140 Etch stop layer

[0028] 150 Storage stacking structure

[0029] 151 Dielectric layer

[0030] 151a First dielectric layer

[0031] 151b Second dielectric layer

[0032] 152, 154 stacking unit

[0033] 153 Conductor layer

[0034] 153a First conductor layer

[0035] 153b Second conductor layer

[0036] 160 channel structure

[0037] 161 Functional Layer

[0038] 163 Filling layer

[0039] 170 Insulation layer

[0040] 180 Interlayer dielectric layer

[0041] 181, 183 Word line contact plug

[0042] 251a First dielectric layer

[0043] 251b Second dielectric layer

[0044] 300 Three-dimensional storage devices

[0045] 351a First dielectric layer

[0046] 351b Second dielectric layer

[0047] 401 dielectric material layer

[0048] 401a, 401b top surface

[0049] 401c, 401d top surface

[0050] 401e, 401f top surface

[0051] 403 Conductive material layer

[0052] 405 Conductive-Dielectric Layer Pair

[0053] 410 first mask layer

[0054] 420 second mask layer

[0055] 430, 431 third mask layer

[0056] a1, a2 slope

[0057] A1 Step Slope

[0058] A2 Step Slope

[0059] A3 Step Slope

[0060] An step slope

[0061] B1 Step Slope

[0062] B2 Step Slope

[0063] B3 Step Slope

[0064] Bn Step Slope

[0065] R1 Zone 1

[0066] R2 Zone 2

[0067] θ1 First angle

[0068] θ2 Second angle DETAILED DESCRIPTION

[0069] In order to enable a person skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with the accompanying drawings. A person skilled in the art to which the present invention belongs can refer to the following embodiments and replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0070] Figures 1 to 3 FIG. 1 is a schematic diagram of a three-dimensional memory device 300 according to an embodiment of the present invention, wherein: Figure 1 is a top view schematic diagram of a three-dimensional memory device 300, Figure 2 is a cross-sectional schematic diagram of a three-dimensional memory device 300, and Figure 3 FIG. 3 is a partially enlarged schematic diagram of a three-dimensional memory device 300. First, please refer to Figure 1 and Figure 2 As shown, the three-dimensional memory device 300 includes a substrate 100 and a memory stack structure 150 disposed above the substrate 100. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials. A liner layer 110, a conductor layer 120, a dielectric layer 130, and an etching stop layer 140 stacked in sequence from bottom to top may be further disposed between the substrate 100 and the memory stack structure 150, as shown in FIG. Figure 2In one embodiment, the liner layer 110 and the dielectric layer 130 include, for example, a dielectric material such as silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON) or a combination thereof, preferably including silicon oxide; the conductor layer 120, for example, includes a conductive material, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), a metal conductive material such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), or a non-metallic conductive material such as polysilicon (poly silicon), doped silicon (doped silicon), metal silicide (silicide) or a combination thereof, preferably including tungsten; and the etching stop layer 140, for example, includes a material having an etching selectivity with the material of the conductor layer 120 and the dielectric layer 130, such as aluminum oxide (Al2O3). 2 O 3 ), but is not limited to this.

[0071] The substrate 100 further includes at least two regions, such as a first region R1 and a second region R2. The first region R1 is, for example, a memory array region, and the second region R2 is, for example, a wordline contact region. In one embodiment, the substrate 100 includes, for example, two second regions R2, which are respectively disposed on two opposite sides of the first region R1. Figure 1As shown, but not limited thereto. Those skilled in the art should easily understand that under actual device requirements, the first region and the second region may also be arranged in other forms. For example, in another embodiment, the second region (not shown) may also be selectively arranged around the first region to surround the first region. In addition, the three-dimensional memory device 300 further includes a plurality of channel structures 160, which are arranged in the first region R1 of the substrate 100. In one embodiment, each channel structure 160, for example, has a columnar shape (e.g., a cylindrical shape), and sequentially penetrates the storage stack structure 150, the etching stop layer 140, the dielectric layer 130, the conductor layer 120, and the liner layer 110 along a direction perpendicular to the surface of the substrate 100, and may directly contact the substrate 100. Specifically, each channel structure 160 includes a functional layer 161 arranged along the sidewall of the channel hole (not shown) and a filling layer 163 filling each of the channel holes. In one embodiment, the functional layer 161, for example, has a composite layer structure, such as, the composite layer structure, for example, includes an oxide-nitride-oxide (ONO, not shown) composite layer and a channel layer stacked in sequence on the sidewall of the channel hole, wherein the channel layer, for example, includes a semiconductor material, such as polysilicon; and the filling layer 163, for example, includes a dielectric material, such as silicon oxide, but is not limited to this.

[0072] On the other hand, the storage stack structure 150 includes a plurality of dielectric layers 151 and a plurality of conductor layers 153 alternately stacked along the direction, wherein each dielectric layer 151 includes, for example, the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, preferably includes the same dielectric material (such as silicon oxide) as the dielectric layer 130, and each conductor layer 153 includes, for example, the same conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, preferably includes the same conductive material (such as tungsten) as the conductor layer 120, but is not limited thereto. Specifically, any layer of the conductor layer 153 and the dielectric layer 151 thereon may together constitute a set of conductive-dielectric layer pairs (not shown), and each of the conductive-dielectric layer pairs extends from the second region R2 on one side of the first region R1 to the second region R2 on the other side, and has the same or different extension ranges as the adjacent conductive-dielectric layer pairs. In this embodiment, the conductive-dielectric layer pairs with the same extension range can respectively form a plurality of stacking units 152, 154 in the second regions R2 on both sides. Each stacking unit 152, 154 includes, for example, two pairs of conductive-dielectric layer pairs, that is, a first conductive layer 153a, a first dielectric layer 151a, a second conductive layer 153b, and a second dielectric layer 151b stacked in sequence from bottom to top. Figure 3It should be noted that, in this embodiment, the extension range of any stacking unit 152, 154 disposed at the bottom is greater than the extension range of any stacking unit 152, 154 disposed at the top, and a portion of the top surface of any stacking unit 152, 154 disposed at the bottom (i.e., a portion of the top surface of the second dielectric layer 151b) can be exposed from the stacking unit 152, 154 disposed at the top, so that the stacking units 152, 154 can be stacked in the two second regions R2 to form a stepped structure, and each stacking unit 152, 154 becomes each step of the stepped structure, as shown in FIG. Figure 2 shown.

[0073] It should also be noted that, in the present embodiment, each stacking unit 152 disposed on the same side exposes a portion of the top surface of the conductive-dielectric layer pairs of odd-numbered (counted from top to bottom) rows (i.e., a portion of the top surface of the second dielectric layer 151b), while each stacking unit 154 disposed on the other side exposes a portion of the top surface of the conductive-dielectric layer pairs of even-numbered rows (i.e., a portion of the top surface of the second dielectric layer 151b). In other words, each step of the stepped structure on both sides may have a step difference of a set of conductive-dielectric layer pairs, such as Figure 2 In addition, in the present embodiment, each stacking unit 152, 154 has a side wall inclined toward the second region R2, and the step slope of each side wall gradually decreases as the stacking units 152, 154 are stacked in sequence from top to bottom. For example, the stacking unit 152 at the top of the stacking sequence has a step slope A1, and the stacking units 152 below the stacking sequence have step slopes A2, A3, ... An, respectively, and the step slopes A2, A3, or An are smaller. In the step slope A1, and the step slope An is less than the step slope A3, and the step slope A3 is less than the step slope A2; similarly, the stacking unit 154 at the top of the stacking sequence has, for example, a step slope B1, and the stacking units 154 below it in the stacking sequence may have step slopes B2, B3...Bn, respectively, and the step slopes B2, B3 or Bn are less than the step slope B1, and the step slope Bn is less than the step slope B3, and the step slope B3 is less than the step slope B2, such as Figure 2 shown.

[0074] It should be noted that the step slope described in this embodiment is essentially a defined value. Figure 3As shown, the second conductor layer 153b and the first conductor layer 153a of each stacking unit 152, 154 may be affected by the etching process during the manufacturing process to form inclined sidewalls with different slopes, wherein in the same stacking unit 152, the second conductor layer 153b stacked on the upper layer and the first conductor layer 153a stacked on the lower layer have different second slopes a2 and first slopes a1 respectively due to the different degrees of influence of the etching process, and the slope a2 is smaller than the slope a1, and the step slope An of the stacking unit 152 is the average value of the slopes a2 and a1, but is not limited thereto. That is, the sidewall of the second conductor layer 153b has a second angle θ2 relative to the bottom surface of the second dielectric layer 151b, and the sidewall of the first conductor layer 153a has a first angle θ1 relative to the bottom surface of the first dielectric layer 151a, and the second angle θ2 is smaller than the first angle θ1. On the other hand, the first dielectric layer 151a and the second dielectric layer 151b are not affected by the etching process and may have side walls perpendicular to the surface of the substrate 100. However, depending on the etching selectivity in the etching process, the first dielectric layer 151a and the second dielectric layer 151b may selectively not overlap the side walls of the first conductor layer 153a and the second conductor layer 153b in the direction perpendicular to the surface of the substrate 100. In this way, the side walls of the first conductor layer 153a and the side walls of the second conductor layer 153b may be exposed from the first dielectric layer 151a and the second dielectric layer 151b, respectively. Figure 3 In another embodiment, the first dielectric layer 251a and the second dielectric layer 251b may also selectively completely overlap the sidewalls of the first conductor layer 153a and the second conductor layer 153b in the direction perpendicular to the surface of the substrate 100, so that the sidewalls of the first conductor layer 153a and the sidewalls of the second conductor layer 153b may be completely covered by the first dielectric layer 251a and the second dielectric layer 251b, respectively. Figure 4 Alternatively, in another embodiment, the first dielectric layer 351a and the second dielectric layer 351b may also selectively partially overlap the side walls of the first conductor layer 153a and the second conductor layer 153b in the direction perpendicular to the surface of the substrate 100, so that the side walls of the first conductor layer 153a and the side walls of the second conductor layer 153b may be partially covered by the first dielectric layer 351a and the second dielectric layer 351b, respectively. Figure 5 shown.

[0075] Then, Figures 1 to 3As shown, the three-dimensional memory device 300 further includes an insulating layer 170 and an interlayer dielectric layer 180 sequentially disposed above the substrate 100, and a plurality of word line contact plugs 181, 183 respectively passing through the interlayer dielectric layer 180, the insulating layer 170, and the second dielectric layer 151b of each stacking unit 152, 154 to directly contact and electrically connect with the second conductor layer 153b. Specifically, the insulating layer 170 conformally covers the storage stack structure 150, between the storage stack structure 150 and the interlayer dielectric layer 180, so as to directly contact the side walls of each stack unit 152, 154 (i.e., the first conductor layer 153a, the first dielectric layer 151a, the second conductor layer 153b, and the side walls of the second dielectric layer 151b), while the interlayer dielectric layer 180 comprehensively covers the substrate 100 and the storage stack structure 150, and has a flush surface with the insulating layer 170 covering the top surface of the storage stack structure 150, such as Figure 2 As shown. In one embodiment, the insulating layer 170 and the interlayer dielectric layer 180 may respectively include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. Preferably, the insulating layer 170, for example, includes a dielectric material with high density but poor hole filling ability, such as silicon nitride, to improve the protective effect of the insulating layer 170 on each conductor layer 153, and the interlayer dielectric layer 180, for example, includes a dielectric material different from the insulating layer 170, such as silicon oxide, but not limited thereto. The word line contact plugs 181, 183 may include a conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably tungsten, but not limited thereto.

[0076] Therefore, the three-dimensional memory device 300 of the present embodiment can intersect with each conductor layer 153 in the memory stack structure 150 through its channel structure 160, wherein the intersection of each channel structure 160 and each conductor layer 153 can become a memory cell of the three-dimensional memory device 300, and each conductor layer 153 can be used as a word line to electrically connect each word line contact plug 181, 183 to control the writing and reading of data of each of the memory cells. Since the storage stacking structure 150 of the present embodiment includes a plurality of stacking units 152, 154 with inclined side walls which are stacked in sequence into a stepped structure, each stacking unit 152 located on the same side exposes a portion of the top surface of the odd-numbered (counted from top to bottom) rows of conductive-dielectric layer pairs (including any conductive layer 153 and the dielectric layer 151 thereon), while each stacking unit 154 arranged on the other side exposes the even-numbered rows of the conductive-dielectric layer pairs, thereby facilitating electrical connection between the conductive layer 153 in each conductive-dielectric layer pair and each word line contact plug 181, 183. On the other hand, the step slope of each of the sidewalls of each stacking unit 152, 154 gradually decreases with the stacking sequence from top to bottom, so that the stacking units 152, 154 arranged at the top can have a relatively large step slope A1, while the stacking units 152, 154 arranged below it have relatively small step slopes A2, A3...An / B2, B3...Bn, respectively. In this way, it is beneficial to make the insulating layer 170 with poor hole filling ability more completely and evenly cover the storage stack structure 150, avoiding the formation of discontinuously covered film layers or faults to expose part of the conductor layer 153 or dielectric layer 151, especially the conductor layer 153 or dielectric layer 151 of the stacking units 152, 154 at the relatively lower stacking sequence. Under this setting, the protective effect of the insulating layer 170 on each conductor layer 153 can be effectively improved, so that the three-dimensional storage device 300 of this embodiment can obtain a more optimized structural integrity and improve its component performance.

[0077] In order to enable a person skilled in the art to implement the three-dimensional memory device 300 described in the above embodiment of the present invention, a method for manufacturing the three-dimensional memory device 300 is further described in detail below.

[0078] Please refer to Figures 6 to 11 , which is a schematic diagram of the steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. First, Figure 6 and Figure 7As shown, a substrate 100 is provided, and then a liner layer 110, a conductor layer 120, a dielectric layer 130, and an etch stop layer 140 are sequentially formed on the substrate 100. A plurality of dielectric material layers 401 and a plurality of conductive material layers 403 are also alternately stacked on the etch stop layer 140, and each dielectric material layer 401, for example, includes the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, preferably includes silicon oxide, and each conductive material layer 403, for example, includes the same conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, preferably includes tungsten, but is not limited thereto. Among them, any layer of conductive material layer 403 and the dielectric material layer 401 above it can together constitute a group of conductive-dielectric layer pairs 405, and each conductive-dielectric layer pair 405 is connected from one side of the first region R1 (such as in FIG. 1 ) in another direction parallel to the surface of the substrate 100. Figure 6 and Figure 7 The second region R2 of the right side (shown in FIG. 1 ) extends to the other side (shown in FIG. Figure 6 and Figure 7 Next, a plurality of channel structures 160 are formed in the first region R1 of the substrate 100, sequentially penetrating each set of conductive-dielectric layer pairs 405, the etching stop layer 140, and the dielectric layer 130, and directly contacting and electrically connecting to the conductive layer 120, as shown in FIG. Figure 6 and Figure 7 shown.

[0079] Then, a first mask layer (e.g., including a photoresist material) 410 is formed on the substrate 100 to cover the stacked dielectric material layer 401 and the conductive material layer 403, wherein the first mask layer 410 completely covers the first region R1 of the substrate and one side thereof (e.g., Figure 6 and Figure 7 and partially covers the second region R2 on the other side (as shown in FIG. Figure 6 and Figure 7 The second region R2 (left side as shown in the figure) is exposed to expose the dielectric material layer 401 formed on the second region R2 on the other side. Then, a first etching process is performed through the first mask layer 410, such as a dry etching process or a wet etching process, to remove a set of conductive-dielectric layer pairs 405 (including the dielectric material layer 401 and the conductive material layer 403) exposed in the second region R2 on the other side, so as to form a relatively low top surface 401a in the second region R2 on the other side, thereby forming the stacked unit described in the aforementioned embodiment, such as Figure 6 and Figure 7 Then, the first mask layer 410 is completely removed.

[0080] Please refer to Figure 8 and Fig. 9, a second mask layer (e.g., including a photoresist material) 420 is formed on the substrate 100 to fully cover the first region R1 of the substrate and the second region R2 on the other side thereof, and partially cover the second region R2 on the one side, thereby exposing the dielectric material layer 401 formed on the second region R2 on the one side. Next, a second etching process is performed through the second mask layer 420, such as a dry etching process or a wet etching process, to remove the two sets of conductive-dielectric layer pairs 405 exposed in the second region R2 on the one side, so as to form a lower top surface 401b on the second region R2 on the one side, as shown in FIG. Figure 8 and Fig. 9 Then, the second mask layer 420 is completely removed. Here, a step difference of a conductive-dielectric layer pair 405 may exist between the top surface 401b in the second region R2 on one side and the top surface 401a in the second region R2 on the other side, but the present invention is not limited thereto.

[0081] Please refer to Fig.10 As shown, a trim-etching process is performed. First, a third mask layer (for example, including a photoresist material) 430 is formed on the substrate 100 to fully cover the first region R1 of the substrate and partially cover each of the second regions R2 on both sides, thereby exposing a portion of the top surfaces 401a and 401b, respectively. Then, a first etching is performed through the third mask layer 430, and the dielectric material layer 401 and the conductive material layer 403 are etched downward from the exposed portions of the top surfaces 401a and 401b, respectively, thereby partially removing the two sets of conductive-dielectric layer pairs 405 to form lower top surfaces 401c and 401d, thereby respectively constituting the stacking units described in the aforementioned embodiments. Among them, the top surface 401d in the second region R2 on one side and the top surface 401c in the second region R2 on the other side may also have a step difference of a set of conductive-dielectric layer pairs 405, such as Fig.10 shown.

[0082] Next, the trimming step of the third mask layer 430 and the etching step of the conductive-dielectric layer pair 405 thereunder are cyclically performed, which may include but not be limited to the following steps. Fig.11 As shown, the third mask layer 430 is trimmed to form a third mask layer 431 to expose another portion of the top surfaces 401a and 401b again. Then, a second etching is performed through the third mask layer 431 to etch down the dielectric material layer 401 and the conductive material layer 403 from the exposed other portion of the top surfaces 401a and 401b, respectively, and then partially remove the two sets of conductive-dielectric layer pairs 405 to form lower top surfaces 401e and 401f. In this way, the trimming step and the etching step are repeated to form the following. Figure 1 and Figure 2 Then, an insulating layer 170, an interlayer dielectric layer 180, and word line contact plugs 181, 183 are sequentially formed on the memory stack structure 150, respectively passing through the interlayer dielectric layer 180, the insulating layer 170, and the second dielectric layer 151b of each stack unit 152, 154 of the memory stack structure 150 to directly contact and electrically connect with the second conductor layer 153b.

[0083] It should be particularly noted that the manufacturing process of this embodiment is performed before the trimming-etching manufacturing process, that is, the first etching process and the second etching process are first performed to remove the part of the conductive-dielectric layer pair 405 exposed in the second region R2 on the one side and the part of the conductive-dielectric layer pair 405 exposed in the second region R2 on the other side, respectively, so as to pre-form the step difference between the second regions R2 on both sides. In this way, in any etching of the trimming-etching manufacturing process, steps with a height difference of one group of conductive layer-dielectric 405 can be formed in the second regions R2 on both sides, but not limited to this. Therefore, the manufacturing process of this embodiment can achieve the purpose of fanning out each conductor layer 153 with a relatively small number of trimming-etching cycles, which can not only shorten the manufacturing time, but also reduce the initial thickness of the third mask layer 430 used in the trimming-etching process, so that a three-dimensional memory device 300 with a more complete structure and more optimized performance can be formed under the premise of simplifying the manufacturing process.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A three-dimensional storage device, characterized in that: include: substrate; as well as A storage stacking structure is arranged on the substrate, and the storage stacking structure includes a plurality of stacking units stacked in sequence in a stepped shape, wherein each of the stacking units has a step slope, and the absolute value of the step slope of any of the stacking units arranged below is smaller than the absolute value of the step slope of any of the stacking units arranged above, and each of the stacking units also includes a first conductor layer, a first dielectric layer, a second conductor layer, and a second dielectric layer stacked in sequence from bottom to top, wherein the first dielectric layer partially overlaps the side wall of the first conductor layer in a direction perpendicular to the substrate, and the side wall of the first dielectric layer is perpendicular to the substrate surface; the orthographic projection of the second conductor layer on the substrate all falls within the range of the orthographic projection of the first conductor layer on the substrate; and a portion of the top surface of any of the stacking units arranged below can be exposed from the stacking unit arranged above it.

2. The three-dimensional memory device according to claim 1, characterized in that: The sidewall of the first conductor layer has a first slope, the sidewall of the second conductor layer has a second slope, and the step slope of each stacking unit is an average of the first slope and the second slope.

3. The three-dimensional memory device according to claim 2, characterized in that: The second slope is smaller than the first slope.

4. The three-dimensional memory device according to claim 1 or 2, characterized in that: The side wall of the first conductor layer has a first angle greater than 90° relative to the bottom surface of the first dielectric layer, and the side wall of the second conductor layer has a second angle greater than 90° relative to the bottom surface of the second dielectric layer, wherein the second angle is smaller than the first angle.

5. The three-dimensional memory device according to claim 1 or 2, characterized in that: The first conductor layer and the second conductor layer include the same conductive material, and the first dielectric layer and the second dielectric layer include the same dielectric material.

6. The three-dimensional memory device according to claim 1 or 2, characterized in that: The second dielectric layer partially overlaps the sidewall of the second conductor layer in a direction perpendicular to the substrate.

7. The three-dimensional memory device according to claim 1 or 2, characterized in that: Also includes: An interlayer dielectric layer covering the storage stack structure; as well as A plurality of word line contact plugs pass through the interlayer dielectric layer and are respectively in direct contact with the second conductor layer in each of the stacking units.

8. The three-dimensional memory device according to claim 7, characterized in that: Also includes: An insulating layer is arranged between the storage stack structure and the interlayer dielectric layer, and the insulating layer directly contacts the side wall of the first conductor layer, the side wall of the first dielectric layer, the side wall of the second conductor layer, and the side wall of the second dielectric layer of each stack unit.

9. The three-dimensional memory device according to claim 1, characterized in that: It also includes a plurality of channel structures, which are arranged in the storage stack structure and penetrate the storage stack structure.

10. A method for manufacturing a three-dimensional memory device, characterized in that: include: providing a substrate; as well as A storage stacking structure is formed on the substrate, the storage stacking structure includes a plurality of stacking units stacked in sequence in a stepped shape, wherein each of the stacking units has a step slope, the absolute value of the step slope of any of the stacking units arranged below is smaller than the absolute value of the step slope of any of the stacking units arranged above, and each of the stacking units also includes a first conductor layer, a first dielectric layer, a second conductor layer, and a second dielectric layer stacked in sequence from bottom to top, the first dielectric layer partially overlaps the side wall of the first conductor layer in a direction perpendicular to the substrate, and the side wall of the first dielectric layer is perpendicular to the substrate surface; the orthographic projection of the second conductor layer on the substrate all falls within the range of the orthographic projection of the first conductor layer on the substrate; and a portion of the top surface of any of the stacking units arranged below can be exposed from the stacking unit arranged above it.

11. The method for manufacturing a three-dimensional memory device according to claim 10, characterized in that: The sidewall of the first conductive layer has a first slope, the sidewall of the second conductive layer has a second slope, and the step slope of each stacking unit is an average value of the first slope and the second slope.

12. The method for manufacturing a three-dimensional memory device according to claim 11, characterized in that: The second slope is smaller than the first slope.

13. The method for manufacturing a three-dimensional memory device according to claim 10 or 11, characterized in that: The side wall of the first conductor layer has a first angle greater than 90° relative to the bottom surface of the first dielectric layer, and the side wall of the second conductor layer has a second angle greater than 90° relative to the bottom surface of the second dielectric layer, wherein the second angle is smaller than the first angle.

14. The method for manufacturing a three-dimensional memory device according to claim 10, characterized in that: Forming a storage stack structure on the substrate includes: forming a plurality of conductive material layers and a plurality of dielectric material layers alternately stacked on the substrate; and A trimming-etching process is performed to partially remove the conductive material layer and the dielectric material layer to form the storage stack structure.

15. The method for manufacturing a three-dimensional memory device according to claim 14, characterized in that: The trim-etch process includes: forming a first mask layer on the alternately stacked conductive material layers and the dielectric material layers; Performing a first etching process through the first mask layer to partially remove the conductive material layer and the dielectric material layer; forming a second mask layer on the alternately stacked conductive material layers and the dielectric material layers; Performing a second etching process through the second mask layer to partially remove the conductive material layer and the dielectric material layer; and The first mask layer and the second mask layer are completely removed.

16. The method for manufacturing a three-dimensional memory device according to claim 14, characterized in that: The trimming-etching process comprises: forming a third mask layer on the alternately stacked conductive material layers and the dielectric material layers; Performing an etching process through the third mask layer to partially remove the conductive material layer and the dielectric material layer to form one of the stacked units, wherein the stacked unit includes at least two dielectric layers and at least two conductive layers; and The third mask layer is trimmed.

17. The method for manufacturing a three-dimensional memory device according to claim 10 or 11, characterized in that: Also includes: forming an insulating layer on the memory stack structure, wherein the insulating layer directly contacts the side wall of the first conductor layer, the side wall of the first dielectric layer, the side wall of the second conductor layer, and the side wall of the second dielectric layer of each of the stack units; forming an interlayer dielectric layer on the memory stack structure; as well as A plurality of word line contact plugs are formed on the substrate, passing through the interlayer dielectric layer and each of the stacking units, and directly contacting the second conductor layer in each of the stacking units.

18. The method for manufacturing a three-dimensional memory device according to claim 10, characterized in that: Also includes: A plurality of channel structures are formed in the storage stack structure and penetrate the storage stack structure.

Images