High performance phase locked loop for millimeter wave applications

Abstract

Embodiments of this disclosure relate to an advanced phase-locked loop (PLL) for millimeter-wave applications. The PLL includes an input comparator circuit that compares a reference signal with a frequency-division feedback signal to control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed and generates an oscillator control signal, causing the oscillator to generate the output signal. A frequency divider circuit divides the output signal by a divisor to generate a frequency-division feedback signal. The divisor generation circuit changes the divisor over time, thus ramping the output signal from a starting frequency to an ending frequency. When the frequency of the output signal is the starting ramp frequency, a modification circuit stores a first oscillator control signal with a value equal to the oscillator control signal. When the frequency of the output signal reaches the ending ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 130,440, filed December 24, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of phase-locked loops, and more particularly to phase-locked loops for generating chirps used in millimeter-wave radar applications. Background Technology

[0004] Radar systems, such as those used in automotive and industrial applications, operate by transmitting electromagnetic signals reflected by objects in their path. By detecting those electromagnetic signals reflected by objects, radar systems can determine the distance, speed, and angle of those objects.

[0005] Millimeter-wave (mmWave) radar is a special type of radar technology that uses short-wavelength electromagnetic waves. A complete millimeter-wave radar system includes transmit (TX) and receive (RX) radio frequency (RF) components, clock generation components, and digital components such as analog-to-digital converters (ADCs), microcontrollers (MCUs), and digital signal processors (DSPs).

[0006] As mentioned earlier, the basic concept of a radar system is to transmit electromagnetic signals reflected from objects in its path. In the signals used by millimeter-wave radar, the frequency of the transmitted electromagnetic signal increases linearly with time. This type of signal is called a "chirp".

[0007] Known phase-locked loops (PLLs) that can be used to generate chirps for millimeter-wave radar

[10] Figure 1As shown in the diagram, the PLL includes a phase-frequency detector and a charge pump circuit 11. The charge pump circuit 11 receives a reference signal REF and a frequency-divided feedback signal DIV, compares their phases, and generates a charge pump output signal IOUT based on this comparison. The charge pump output signal IOUT, after being filtered by a loop filter 12, is used to generate a control voltage to set the frequency of a voltage-controlled oscillator (VCO) 13, which generates an output signal FOUT for the PLL. A loop divider 14 divides the output signal FOUT by a time-varying value provided by a Σ-Δ modulator 15 to generate the frequency-divided feedback signal DIV. The phase-frequency detector and the charge pump 11 adjust the charge pump output signal IOUT such that the final frequency-divided feedback signal DIV is in phase with the reference signal REF, meaning that the frequency-divided feedback signal DIV is also equal to the reference signal REF in frequency. As explained, the divider value varies with time under the control of the Σ-Δ modulator 15, and the charge pump output signal IOUT also varies with time to keep the divider feedback signal DIV locked to the reference signal REF, as explained, where the result is a frequency ramp of the output signal FOUT. In order to perform a flyback (resetting the frequency of the output signal FOUT to its original value to start another chirp), the divider value will be reset to its initial value.

[0008] like Figure 2 The graph shows the chirp frequency as a function of time. The chirp is defined by the ramp period CHIRP_RAMP that occurs within the time interval t_ramp and the retrace period CHIRP_RETRACE that occurs within the time interval t_retrace. The ramp period is characterized by its start frequency F0 and end frequency F. f Together, these define the chirp bandwidth BW. The chirp slope during the ramp period represents the rate of frequency change. It can be seen that the sweepback period may be problematic because the frequency changes from the final frequency F... f A rapid descent back to the starting frequency F0 will cause overshoot. The bandwidth of this overshoot is determined by... Figure 2 F_OST represents this. Since overshoot increases the necessary duration of the flyback period (because the system needs to recover from the overshoot), it is necessary to eliminate the overshoot so that the duration of the flyback period can be reduced, thereby allowing for an increase in the duty cycle or duty cycle frequency. Additionally, it is desirable that the chirp during the ramp period be sufficiently linear, and that charge pump noise, Σ-Δ modulator noise, and reference signal noise are filtered out.

[0009] However, to increase the ramp slope, reduce the flyback time, and achieve good linearity, the bandwidth of PLL 10 should be increased; conversely, to filter out charge pump noise, Σ-Δ modulator noise, and reference signal noise, the bandwidth of PLL 10 should be reduced. These conflicting requirements render known PLLs for chirping generation (such as PLL 10) insufficient. Therefore, further development is needed. Summary of the Invention

[0010] This document discloses a phase-locked loop (PLL) including an input comparator circuit configured to compare a reference signal with a frequency-divided feedback signal and generate at least one charge pump control signal based on the comparison. The PLL also includes a charge pump configured to generate a charge pump output signal in response to the at least one charge pump control signal, a switch, and a loop filter. The loop filter is coupled to receive the charge pump output signal when the switch is closed and is configured to filter the charge pump output signal to generate an oscillator control signal. The oscillator is configured to generate an output signal in response to the oscillator control signal. A frequency divider circuit is configured to divide the output signal by a divisor to generate a frequency-divided feedback signal. A divisor generation circuit is configured to change the divisor over time such that the frequency of the frequency-divided feedback signal changes from a first frequency to a second frequency over time, wherein the frequency of the frequency-divided feedback signal has a first frequency causing the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency-divided feedback signal has a second frequency causing the frequency of the output signal to have an ending ramp frequency. The oscillator control signal modification circuitry stores a first oscillator control signal, wherein when the frequency of the output signal is the starting ramp frequency, the first oscillator control signal is equal to the value of the oscillator control signal. When the frequency of the output signal reaches the ending ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter, thereby reducing the frequency of the output signal to the starting ramp frequency.

[0011] This document discloses another phase-locked loop (PLL) including an input comparator circuit configured to compare a reference signal with a frequency-divided feedback signal and generate at least one charge pump control signal based thereon. The PLL also includes: a charge pump configured to generate a charge pump output signal in response to the at least one charge pump control signal; a loop filter coupled to receive the charge pump output signal and filter the charge pump output signal to generate an oscillator control signal; a voltage-controlled oscillator (VCO) configured to generate an output signal in response to the oscillator control signal; a frequency divider circuit configured to divide the output signal by a divisor to generate a frequency-divided feedback signal; and a divisor generation circuit. The divisor generation circuit is configured to: during the ramp period, change the divisor over time such that the frequency of the frequency division feedback signal changes from a first frequency to a second frequency over time, wherein the frequency of the frequency division feedback signal has a first frequency, causing the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency division feedback signal has a second frequency, causing the frequency of the output signal to have an end ramp frequency; and during the retrace period, change the divisor over time such that the frequency of the frequency division feedback signal returns from the second frequency to the first frequency over time according to a first-order exponential decay.

[0012] This document also discloses a radar device. The radar device includes a transmitter antenna, a synthesizer configured to generate an RF signal for transmission by the transmitter antenna, a receiver antenna configured to receive a reflected RF signal, and a mixer configured to receive the RF signal generated by the synthesizer and the reflected RF signal, and generate an intermediate frequency (IF) signal based thereon. The radar device also includes: an analog-to-digital converter configured to digitize the IF signal; and processing circuitry configured to determine the distance between the radar device and an external object reflecting the reflected RF signal based on the IF signal. The synthesizer includes any of the phase-locked loops described above, and an RF multiplier that receives the output signal and is configured to generate an RF signal based thereon. Attached Figure Description

[0013] Figure 1 This is a block diagram of a known phase-locked loop that can be used in millimeter-wave radar systems.

[0014] Figure 2 This is a graph showing the chirp, consisting of the ramp period and the backscan period, used in millimeter-wave radar systems.

[0015] Figure 3 This is a block diagram of the millimeter-wave radar system disclosed in this article.

[0016] Figure 4 This is what is disclosed in this article and can be used with Figure 3 A block diagram of a first embodiment of a phase-locked loop used in millimeter-wave radar systems.

[0017] Figure 5 yes Figure 4 A block diagram of a first embodiment of a phase-locked loop VCO control signal storage / recovery circuit.

[0018] Figure 6 yes Figure 4 A block diagram of a second embodiment of the phase-locked loop VCO control signal storage / recovery circuit.

[0019] Figure 7 When using Figure 4 When using a phase-locked loop, Figure 3 The chirping curve generated by the millimeter-wave radar system.

[0020] Figure 8 Using different backscan strategies Figure 3 A magnified view of the chirped retrace period generated by the millimeter-wave radar system.

[0021] Figure 9 This is what is disclosed in this article and can be used with Figure 3 A block diagram of a second embodiment of a phase-locked loop used in millimeter-wave radar systems.

[0022] Figure 10 When using Figure 9 When using a phase-locked loop, Figure 3 The two chirped curves generated by the millimeter-wave radar system.

[0023] Figure 11 This is a block diagram of the first embodiment of the frequency-locked loop disclosed herein.

[0024] Figure 12 This is a block diagram of the second embodiment of the frequency-locked loop disclosed herein. Detailed Implementation

[0025] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0026] Original Reference Figure 3The millimeter-wave radar system 20 is now described. The millimeter-wave radar system 20 includes a synthesizer 21, which includes a phase-locked loop (PLL) to generate a millimeter-wave chirp to be transmitted by a transmitter antenna 22. Note that the millimeter-wave chirp is also passed to a mixer 23. The chirp is transmitted outward from the transmitter antenna 22, which is in the path of a device incorporated into the millimeter-wave radar system (e.g., a vehicle or mobile industrial equipment), and the chirp is reflected from objects in the path of the device. The reflections are received by a receiver antenna 24, and the resulting signal is passed to the mixer 23, which mixes the output millimeter-wave chirp with the input reflections to form an intermediate frequency (IF) signal. The IF signal is filtered by a low-pass filter (LPF) 25 and digitized by an analog-to-digital converter (ADC) 26.

[0027] As those skilled in the art will understand, based on the known properties of the IF signal and the transmitted chirp, the physical distance to the reflected chirp can be mathematically calculated by the processing circuitry 27 that receives the digitized IF signal. In some cases, the velocity of the object can also be calculated by analyzing two separate IF signal pulses. If multiple receiving antennas are used, the angle between the object and the equipment incorporated into the millimeter-wave radar system 20 can be determined.

[0028] Especially in the vehicle and industrial applications of the millimeter-wave radar system 20, there is a need to combine the advantages of low PLL bandwidth in generating chirp (which effectively filters charge pump noise, Σ-Δ modulator noise, and reference signal noise) with the advantages of high PLL bandwidth (which provides good linearity, high ramp slope, and low retrace time). To achieve these effects from seemingly contradictory design requirements, a new PLL 30 has been designed for the synthesizer 21, and now the reference... Figure 4 To describe such a PLL 30.

[0029] PLL 30 includes a phase-frequency detector (PFD) 31, which receives a reference signal REF and a frequency-divided feedback signal DIV, and generates control signals UP and DN for charge pump 32 based on a comparison between the phases of REF and DIV. Charge pump 32 generates a charge pump output signal IOUT based on the control signals UP and DN, and the charge pump output signal IOUT is then selectively passed through a low-pass filter (LPF) 33 via switch S1 to generate a control signal VCONT for voltage-controlled oscillator (VCO) 34.

[0030] VCO 34 generates an output signal FOUT based on the control signal VCONT. Radio frequency (RF) multiplier 35 generates a chirp to be transmitted by transmitter antenna 22 based on the output signal FOUT.

[0031] The output signal FOUT also passes the division feedback signal DIV generated by the fixed divider 36 and the programmable divider 37. Note that the modulator 38 also receives the division feedback signal DIV and passes its output through the digital inverting / pre-emphasis filter 39 to provide input to the Σ-Δ modulator 40. The Σ-Δ modulator 40 controls the divisor used by the programmable divider 37 and can provide control signals to the charge pump 32 to help reduce quantization noise. For more details on eliminating Σ-Δ modulation quantization noise, see the article entitled “A 700-kHz Bandwidth Σ-Δ Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications” by Temporiti et al., published in IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, which is incorporated herein by reference in its entirety.

[0032] The charge pump output signal IOUT and therefore the control signal VCONT are designed to set the frequency of the output signal FOUT such that the phase (and therefore the frequency) of the frequency division feedback signal DIV is equal to the frequency of the reference signal REF. The digital inverting / pre-emphasis filter 39 adds appropriate pre-emphasis to the output from the modulator 38, causing the Σ-Δ modulator 40 to divisor the programmable frequency divider 37, which in turn forces the PFD 31 to increase the frequency of the output signal FOUT, thereby generating a ramp of the chirped frequency during the ramp period. This allows the bandwidth of the chirped frequency to remain low, minimizing noise.

[0033] To determine the transfer function of the digital inverting / pre-emphasis filter 39, a model of the PLL 30 is generated in the Laplace domain and then transformed to the Z domain. Based on the model of the PLL 30 in the Z domain, the transfer function of the digital inverting / pre-emphasis filter 39 can be appropriately determined as will be understood by those skilled in the art.

[0034] Note the presence of circuit 29, which stores the value of the VCO control signal VCONT at the start of the ramp period (e.g., the value of VCONT that causes the frequency of FOUT to be generated as F0). At the end of the ramp period (at the start of the chirped flyback period), the loop is opened by disconnecting switch S1 (which can be performed by circuit 29), and circuit 29 restores the stored value of VCONT (e.g., by forcing the stored value of VCONT onto the output of LPF 33), causing the ramp to drop rapidly back to F0. The loop is then closed by closing switch S1, and the output signal FOUT is allowed to stabilize before the start of the next ramp period. This technique provides overshoot-free fast flyback, helps eliminate the possibility of cycle slipping caused by a large negative slope of the FOUT frequency during flyback, and helps improve chirping during the ramp period.

[0035] like Figure 5 The diagram shows one possible configuration of circuit 29. Circuit 29 may include counter 29a, digital processing block 29b (e.g., a microcontroller or microprocessor utilizing a lookup table), and voltage digital-to-analog converter (DAC) 29c. During the initial configuration phase with switch S1 open, counter 29a measures the frequency of FOUT, while digital processing block 29b forces different voltages through LPF 33 via voltage DAC 29c to produce different VCONT values. Thus, digital processing block 29b forms a lookup table of DAC codes, where each DAC code corresponds to the FOUT frequency generated by applying that DAC code to voltage DAC 29c (thus resulting in different VCONT values, and therefore different FOUT frequencies for each DAC code). Switch S1 is then closed so that counter 29a measures the FOUT frequency generated as F0 at the start of the ramp period. Thus, digital processing block 29b now knows which DAC code to force onto voltage DAC 29c at the end of the ramp period (start of the flyback period). Additionally, counter 29a can measure the frequency F as... f The generated FOUT frequency.

[0036] In order to utilize this configuration of circuit 29, once the lookup table is established in the configuration phase and the DAC code for retracement is determined, the millimeter-wave radar system 20 and PLL 30 are activated and switch S1 is closed.

[0037] At the end of the ramp period (at the beginning of the chirped scan period), this can be achieved, for example, by measuring the frequency of FOUT using counter 29a and reaching the frequency F determined during the calibration phase. fThe loop is then opened by disconnecting switch S1 (under the control of circuit 29, specifically digital processing block 29b), and digital processing block 29b forces the previously determined retrace DAC code onto the input of voltage DAC 29c. The output of voltage DAC 29c is passed through LPF 33 to generate the value of VCONT for VCO34 to use to start the retrace, causing the chirp to drop rapidly back to F0. The loop is then closed by closing switch S1 (under the control of circuit 29), and the output signal FOUT is allowed to stabilize before the next ramp begins.

[0038] like Figure 6 The diagram shows another possible configuration of circuit 29'. Circuit 29' may include an analog-to-digital converter (ADC) 29a' that digitizes the charge pump output IOUT (resulting in FOUT at frequency F0) at the start of the ramp period, and then, optionally by means of the digital processing circuitry 29b that controls switch S1 as described above, outputs the digital value to a digital-to-analog converter (DAC) 20b' at the end of the ramp period (once switch S1 has been opened). DAC 20b' converts the digital value back to an analog current and forces the current at the LPF 33 input to generate the value of VCONT for VCO 34 to use to begin a flyback, resulting in a rapid drop in the chirp back to F0. The loop is then closed by closing switch S1, and the output signal FOUT is allowed to stabilize before the start of the next ramp period. Note that, for this embodiment, with... Figure 5 In contrast to other embodiments, the value of F0 can be redefined periodically or sequentially, thereby helping to provide accurate tracking of the chirp over a temperature range.

[0039] The performance provided by PLL 30 can Figure 7 As seen in the data, it achieves a scanback time of 2.75 μs, a ramp time of 10 μs, linearity within ±0.25%, overshoot of less than 1 MHz, and a bandwidth of approximately 200 kHz. This performance is unattainable in existing technology designs, thus providing unparalleled performance for the millimeter-wave system 20.

[0040] In some cases, it may be desirable to sacrifice a small amount of accuracy and robustness in the PLL 30 in exchange for a lower-cost PLL that consumes less area but still achieves good enough performance for millimeter-wave systems 20. (Reference) Figure 8 Note that during the scanback period (the time interval is shown as t_reset), the chirping frequency increases from its high value F. fThe chirp frequency drops to its low value F0. If the divisor is simply reset to its initial value as in existing systems, the resulting downslope of the chirp frequency (shown as "slope reset") will result in undesirable overshoot. Another approach is to change the slope of the downslope of the chirp frequency during the flyback period (shown as two-point reset). While this does reduce overshoot, the amount of overshoot is still undesirable. It has been found, and will now be described herein, that overshoot is eliminated when the slope of the downslope of the chirp frequency during the flyback period decreases exponentially in a first-order manner.

[0041] Now for reference Figure 9 The phase-locked loop (PLL) 30' incorporating this function is described below. PLL 30' includes a phase-frequency detector and a charge pump 51, which receives a reference signal REF and a frequency-divided feedback signal DIV, compares their phases, and generates a charge pump output signal IOUT based on this comparison. After being filtered by a loop filter 52, the charge pump output signal IOUT is used to set the frequency of a voltage-controlled oscillator (VCO) 53, which generates an output signal FOUT from the PLL. The output signal FOUT is fed to an RF multiplier 54, which in turn generates an RF signal for transmission by the transmitter antenna 22. A loop divider 55 divides the output signal FOUT by a time-varying value provided by a Σ-Δ modulator 62 to generate the frequency-divided feedback signal DIV. The phase-frequency detector and charge pump 51 adjust the charge pump output signal IOUT so that, ultimately, the frequency-divided feedback signal DIV is in phase with the reference signal REF, meaning that the frequency-divided feedback signal DIV is also equal in frequency to the reference signal REF. Since the frequency divider value changes with time under the control of the ∑-Δ modulator 62, as explained, the charge pump output signal IOUT also changes with time to keep the frequency division feedback signal DIV locked to the reference signal REF, as explained, where the result is the output signal FOUT ramp.

[0042] The generation of the input to the Σ-Δ modulator 62 is now described. During the ramp period t_ramp, the output of the ramp generator 60 is selected by the multiplexer 61 and provided to the input of the Σ-Δ modulator 62 to increase the divisor of the Σ-Δ modulator 62 over time to achieve the desired ramp of the chirped frequency during the ramp period.

[0043] During the retrace period t_retrace, the reset counter 56 (meaning it counts from its starting value to the desired ending value and is reset back to its starting value once the ending value is reached) provides output to the lookup table 57. In some cases, the lookup table may have a low-precision portion (e.g., the first 3 / 4 of an entry might be 6 bits) and a high-precision portion (e.g., the last 1 / 4 of an entry might be 10 bits). Based on the count value received from the reset counter 56, the lookup table 57 outputs the value stored at the appropriate table entry to the interpolation circuit 58, which then passes the interpolated result to function block 59, which implements function N. L +BW*Fd(x), where N L It is the lowest frequency of the ramp, BW = F f -F0(F f Fd(x) is the highest frequency of the ramp, and Fd(x) is the output of lookup table 57 after interpolation by interpolation circuit 58. The output of functional block 59 (mathematically, Fd(x)) is selected by multiplexer 61 during retrace and passed to Σ-Δ modulator 62 as input to achieve a chirped slope with first-order exponential decay.

[0044] In some cases, the processing of interpolation block 58 effectively "preserves" each sample over a time period, thereby increasing the time period during which that sample affects the output of Σ-Δ modulator 62. This can increase the retrace time required by the application.

[0045] Multiplexer 61 is controlled by control block 66, which selects either the output of ramp generator 60 or the output of function block 59 based on the output of each. The reset counter is also reset by control block 66 based on the outputs of ramp generator 60 and function block 59.

[0046] The output signal FOUT can be Figure 10 As seen in the image, without significant overshoot, note the controlled exponential decay of the output signal FOUT frequency during the flyback period. Note the height linearity during the ramp phase. In this embodiment, the flyback time is 3.5 μs, and the overshoot is less than 0.25 MHz.

[0047] Please note that, although Figure 3 and Figure 9 The two embodiments have been described with reference to a chirped ramp from low frequency to high frequency and a chirped sweepback from high frequency to low frequency, but either embodiment can be clearly arranged to perform the opposite operation, wherein the chirped ramp is from high frequency to low frequency and the chirped sweepback is from low frequency to high frequency.

[0048] Although the above embodiments 30 and 30' have been described as being arranged as phase-locked loops, it should be understood that both embodiments 30 and 30' can be arranged as frequency-locked loops.

[0049] In such Figure 11 In the case of the frequency-locked loop (FLL) 30” shown, it has the same characteristics as Figure 4 The PLL 30 has the same design and operation, except that the phase-frequency detector 31 has been replaced by a frequency detector 31". Instead of generating control signals UP and DN based on whether the phases of the reference signal REF and the frequency-division feedback signal DIV match, the frequency detector 31" generates control signals UP and DN based on whether the frequencies of the reference signal REF and the frequency-division feedback signal DIV match. Those skilled in the art will understand that if two signals match in phase, they match in frequency, but if two signals match in frequency, they do not necessarily match in phase.

[0050] In such Figure 12 In the case of the FLL 30”’ shown, it has the same Figure 9 The design and operation are the same as PLL 30', except that the phase frequency detector and charge pump 51 have been replaced with a frequency detector and charge pump 51"'. Instead of generating the charge pump output signal IOUT based on whether the phase of the reference signal REF matches the phase of the frequency division feedback signal DIV, the frequency detector and charge pump 51"' generates the charge pump output signal based on whether the frequency of the reference signal REF matches the frequency of the frequency division feedback signal DIV.

[0051] The above-described frequency-locked loop embodiments are useful in some applications that do not require a phase-locked loop or in some applications where frequency locking alone is sufficient.

[0052] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure as disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A phase-locked loop, comprising: An input comparator circuit is configured to compare a reference signal with a frequency division feedback signal and generate at least one charge pump control signal based on the comparison. A charge pump is configured to generate a charge pump output signal in response to the at least one charge pump control signal; switch; A loop filter is coupled to receive the charge pump output signal when the switch is closed, and the loop filter is configured to filter the charge pump output signal to generate an oscillator control signal; An oscillator is configured to generate an output signal in response to an oscillator control signal; A frequency divider circuit is configured to divide the output signal by a divisor to generate the frequency division feedback signal. A divisor generation circuit is configured to change the divisor over time, such that the frequency of the frequency division feedback signal changes from a first frequency to a second frequency over time, wherein the frequency of the frequency division feedback signal having the first frequency causes the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency division feedback signal having the second frequency causes the frequency of the output signal to have an ending ramp frequency; and An oscillator control signal modification circuit device stores a first oscillator control signal, wherein when the frequency of the output signal is the initial ramp frequency, the first oscillator control signal is equal to the value of the oscillator control signal; When the frequency of the output signal reaches the end ramp frequency, the oscillator control signal modification circuit is configured to disconnect the switch and apply the stored first oscillator control signal to the loop filter, thereby changing the frequency of the output signal to the start ramp frequency.

2. The phase-locked loop of claim 1, wherein the input comparison circuit includes a phase-frequency detector; and wherein the phase-frequency detector is configured to: compare the phase of the reference signal with the phase of the frequency-division feedback signal, and generate the charge pump control signal based on whether the phase of the reference signal leads the phase of the frequency-division feedback signal or whether the phase of the frequency-division feedback signal leads the phase of the reference signal.

3. The phase-locked loop according to claim 1, wherein the frequency divider circuit device includes a fixed frequency divider circuit, the fixed frequency divider circuit receiving the output signal, dividing the output signal by a fixed divisor, and transmitting the output signal after being divided by the fixed divisor to a programmable divisor; and wherein the programmable divisor divides the output signal by a programmable divisor generated by the divisor generation circuit device, such that the frequency of the frequency division feedback signal decreases from the first frequency to the second frequency over time.

4. The phase-locked loop according to claim 1, wherein the divisor generation circuit device includes a Σ-Δ modulator.

5. The phase-locked loop of claim 4, wherein the divisor generation circuit further comprises a modulator that generates an input signal that is passed through a pre-emphasis filter before being provided as an input to the Σ-Δ modulator.

6. The phase-locked loop according to claim 1, wherein the oscillator control signal modification circuit device comprises: A counter is configured to generate a count representing the frequency of the output signal; A digital processing block is configured to receive input from the counter; as well as A digital-to-analog converter is configured to generate a stored first oscillator control signal and apply the stored first oscillator control signal to the loop filter; During the configuration phase, the digital processing block applies different input codes to the digital-to-analog converter until the frequency of the output signal equals the starting ramp frequency, and stores the input codes from the different input codes that cause the frequency of the output signal to equal the starting ramp frequency; and During operation, when the switch is turned off, the digital processing block applies the stored input code to the digital-to-analog converter.

7. The phase-locked loop according to claim 1, wherein the oscillator control signal modification circuit device comprises: An analog-to-digital converter is configured to digitize and store an oscillator control signal whose frequency is equal to the initial ramp frequency when the frequency of the output signal is equal to the initial ramp frequency. as well as A digital-to-analog converter is configured to convert a stored oscillator control signal back to an analog signal when the frequency of the output signal is equal to the end ramp frequency, and to apply the oscillator control signal whose frequency is equal to the start ramp frequency at that point.

8. The phase-locked loop according to claim 1, wherein the loop filter comprises a low-pass filter.

9. The phase-locked loop of claim 1, further comprising an RF multiplier, the RF multiplier receiving the output signal and configured to generate an RF signal based on the output signal.

10. The phase-locked loop of claim 1, wherein the input comparison circuit includes a frequency detector; and wherein the frequency detector is configured to compare the frequency of the reference signal with the frequency of the frequency-divided feedback signal, and to generate the charge pump control signal based on whether the frequency of the reference signal is greater than the frequency of the frequency-divided feedback signal, or whether the frequency of the frequency-divided feedback signal is greater than the frequency of the reference signal.

11. A radar device, comprising: Transmitter antenna; A synthesizer is configured to generate an RF signal for transmission by the transmitter antenna; The receiver antenna is configured to receive reflected RF signals; A mixer is configured to receive the RF signal generated by the synthesizer and the reflected RF signal, and to generate an intermediate frequency signal based on the RF signal and the reflected RF signal; An analog-to-digital converter is configured to digitize the intermediate frequency signal; as well as The processing circuitry is configured to determine, based on the intermediate frequency signal, the distance between the radar device and an external object that reflects the reflected RF signal; The synthesizer said therein includes: Phase-locked loop, including: An input comparator circuit is configured to compare a reference signal with a frequency division feedback signal and generate at least one charge pump control signal based on the comparison. A charge pump is configured to generate a charge pump output signal in response to the at least one charge pump control signal; switch; A loop filter is coupled to receive the charge pump output signal when the switch is closed, and filters the charge pump output signal to generate a voltage-controlled oscillator (VCO) control signal. A voltage-controlled oscillator (VCO) is configured to generate an output signal in response to a VCO control signal; A frequency divider circuit is configured to divide the output signal by a divisor to generate the frequency division feedback signal. A divisor generation circuit is configured to change the divisor over time, such that the frequency of the frequency division feedback signal changes from a first frequency to a second frequency over time, wherein the frequency of the frequency division feedback signal having the first frequency causes the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency division feedback signal having the second frequency causes the frequency of the output signal to have an ending ramp frequency; and VCO control signal modification circuit device, storing a first VCO control signal, wherein when the frequency of the output signal is the initial ramp frequency, the first VCO control signal is equal to the value of the VCO control signal; When the frequency of the output signal reaches the end ramp frequency, the VCO control signal modification circuit disconnects the switch and applies the stored first VCO control signal to the loop filter, thereby changing the frequency of the output signal to the start ramp frequency; and An RF multiplier receives the output signal and is configured to generate the RF signal based on the output signal.

12. The radar device of claim 11, wherein the input comparison circuit includes a phase frequency detector; and wherein the phase frequency detector is configured to: compare the phase of the reference signal with the phase of the frequency-division feedback signal, and generate the charge pump control signal based on whether the phase of the reference signal leads the phase of the frequency-division feedback signal or whether the phase of the frequency-division feedback signal leads the phase of the reference signal.

13. The radar device of claim 11, wherein the frequency divider circuit device includes a fixed frequency divider circuit, the fixed frequency divider circuit receiving the output signal, dividing the output signal by a fixed divisor, and transmitting the output signal after being divided by the fixed divisor to a programmable divisor; and wherein the programmable divisor divides the output signal by a programmable divisor generated by the divisor generation circuit device, such that the frequency of the frequency division feedback signal decreases from the first frequency to the second frequency over time.

14. The radar device of claim 11, wherein the divisor generation circuit includes a Σ-Δ modulator.

15. The radar device of claim 14, wherein the divisor generation circuitry further comprises a modulator that generates an input signal which is passed through a pre-emphasis filter before being provided as an input to the Σ-Δ modulator.

16. The radar device according to claim 11, wherein the VCO control signal modification circuit device comprises: A counter is configured to generate a count representing the frequency of the output signal; A digital processing block is configured to receive input from the counter; as well as A digital-to-analog converter is configured to generate a stored first VCO control signal and apply the stored first VCO control signal to the loop filter; During the configuration phase, the digital processing block applies different input codes to the digital-to-analog converter until the frequency of the output signal equals the starting ramp frequency, and stores the input codes from the different input codes that cause the frequency of the output signal to equal the starting ramp frequency; and During operation, when the switch is turned off, the digital processing block applies the stored input code to the digital-to-analog converter.

17. The radar device according to claim 11, wherein the VCO control signal modification circuit device comprises: An analog-to-digital converter is configured to digitize and store an oscillator control signal whose frequency is equal to the initial ramp frequency when the frequency of the output signal is equal to the initial ramp frequency. as well as A digital-to-analog converter is configured to convert a stored VCO control signal back to an analog signal when the frequency of the output signal is equal to the end ramp frequency, and to apply an oscillator control signal whose frequency at the output signal is equal to the start ramp frequency.

18. A phase-locked loop, comprising: An input comparator circuit is configured to compare a reference signal with a frequency division feedback signal and generate at least one charge pump control signal based on the comparison. A charge pump is configured to generate a charge pump output signal in response to the at least one charge pump control signal; A loop filter is coupled to receive the charge pump output signal and filters the charge pump output signal to generate an oscillator control signal; A voltage-controlled oscillator (VCO) is configured to generate an output signal in response to a control signal for the oscillator; A frequency divider circuit is configured to divide the output signal by a divisor to generate a frequency division feedback signal. as well as The divisor generating circuit device is configured as follows: During the ramp period, the divisor is changed over time, causing the frequency of the frequency division feedback signal to change from a first frequency to a second frequency over time, wherein the frequency of the frequency division feedback signal having the first frequency causes the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency division feedback signal having the second frequency causes the frequency of the output signal to have an end ramp frequency. as well as During the retrace period, the divisor is changed over time, causing the frequency of the frequency division feedback signal to decay exponentially from the second frequency back to the first frequency over time.

19. The phase-locked loop according to claim 18, wherein the divisor generation circuit device comprises: A multiplexer having an output that provides an input to a Σ-Δ modulator, the Σ-Δ modulator generating control signals for the frequency divider circuitry; A ramp generator generates a ramp signal and provides the ramp signal to the multiplexer; The counter can be reset; The lookup table receives the current count from the resettable counter and outputs table entries based on the current count; An interpolation circuit interpolates the table entries received from the lookup table; as well as An exponential function circuit generates a Σ-Δ modulator input. If the Σ-Δ modulator input is fed as an input to the Σ-Δ modulator, it will cause the divisor to change, so that the frequency of the output signal decays over time from the end ramp frequency to the start ramp frequency according to a first-order exponential function. The multiplexer selects the ramp signal for output during the ramp period and selects the Σ-Δ modulator input for output during the retrace period.

20. The phase-locked loop of claim 19, wherein the input comparison circuit includes a phase-frequency detector; and wherein the phase-frequency detector is configured to: compare the phase of the reference signal with the phase of the frequency-division feedback signal, and generate the charge pump control signal based on whether the phase of the reference signal leads the phase of the frequency-division feedback signal or whether the phase of the frequency-division feedback signal leads the phase of the reference signal.

21. The phase-locked loop of claim 18, wherein the loop filter comprises a low-pass filter.

22. The phase-locked loop of claim 18, further comprising an RF multiplier that receives the output signal and is configured to generate an RF signal based on the output signal.

23. A radar device, comprising: Transmitter antenna; A synthesizer is configured to generate an RF signal for transmission by the transmitter antenna; The receiver antenna is configured to receive reflected RF signals; A mixer is configured to receive the RF signal generated by the synthesizer and the reflected RF signal, and to generate an intermediate frequency signal based on the RF signal and the reflected RF signal; An analog-to-digital converter is configured to digitize the intermediate frequency signal; as well as The processing circuitry is configured to determine, based on the intermediate frequency signal, the distance between the radar device and an external object that reflects the reflected RF signal; The synthesizer said therein includes: Phase-locked loop, including: An input comparator circuit is configured to compare a reference signal with a frequency division feedback signal and generate at least one charge pump control signal based on the comparison. A charge pump is configured to generate a charge pump output signal in response to the at least one charge pump control signal; A loop filter is coupled to receive the charge pump output signal and filters the charge pump output signal to generate an oscillator control signal; A controlled oscillator (VCO) is configured to generate an output signal in response to an oscillator control signal; A frequency divider circuit arrangement is configured to divide the output signal by a divisor to generate the frequency division feedback signal; and The divisor generating circuit device is configured as follows: During the ramp period, the divisor is changed over time, causing the frequency of the frequency-divided feedback signal to change from a first frequency to a second frequency over time, wherein the frequency of the frequency-divided feedback signal having the first frequency causes the frequency of the output signal to have an initial ramp frequency, and the frequency of the frequency-divided feedback signal having the second frequency causes the frequency of the output signal to have an ending ramp frequency; and During the retrace period, the divisor is changed over time, such that the frequency of the frequency-divided feedback signal decays exponentially from the second frequency back to the first frequency over time; and An RF multiplier receives the output signal and is configured to generate the RF signal based on the output signal.

24. The radar device of claim 23, wherein the input comparison circuit includes a phase frequency detector; and wherein the phase frequency detector is configured to: compare the phase of the reference signal with the phase of the frequency-division feedback signal, and generate the charge pump control signal based on whether the phase of the reference signal leads the phase of the frequency-division feedback signal or whether the phase of the frequency-division feedback signal leads the phase of the reference signal.

25. The radar device according to claim 23, wherein the divisor generation circuit comprises: A multiplexer having an output that provides an input to a Σ-Δ modulator, the Σ-Δ modulator generating control signals for the frequency divider circuitry; A ramp generator generates a ramp signal and provides the ramp signal to the multiplexer; The counter can be reset; The lookup table receives the current count from the resettable counter and outputs table entries based on the current count; An interpolation circuit interpolates the table entries received from the lookup table; as well as An exponential function circuit generates a Σ-Δ modulator input. If the Σ-Δ modulator input is fed as an input to the Σ-Δ modulator, it will cause the divisor to change, so that the frequency of the output signal decays over time from the end ramp frequency to the start ramp frequency according to a first-order exponential function. The multiplexer selects the ramp signal for output during the ramp period and selects the Σ-Δ modulator input for output during the retrace period.

26. The radar device of claim 23, wherein the loop filter comprises a low-pass filter.

27. A method for millimeter-wave applications, comprising: At least one charge pump control signal is generated based on the reference signal and the frequency division feedback signal; A charge pump output signal is generated in response to the at least one charge pump control signal; When the switch is closed, the output signal of the charge pump is filtered to generate an oscillator control signal; An output signal is generated in response to the oscillator control signal; The output signal is divided by a divisor to generate the frequency-divided feedback signal; The divisor is changed so that the frequency of the frequency division feedback signal changes from a first frequency to a second frequency over time; When the frequency of the output signal is at the initial ramp frequency, a first oscillator control signal with a value equal to that of the oscillator control signal is determined; as well as When the frequency of the output signal reaches the end ramp frequency, the first oscillator control signal is applied to the filter, thereby changing the frequency of the output signal to the start ramp frequency.

28. The method of claim 27, wherein determining the first oscillator control signal comprises: Generate a count representing the frequency of the output signal; Generate the first oscillator control signal and apply the first oscillator control signal to the filter; During the configuration phase, different input codes are used until the frequency of the output signal equals the starting ramp frequency, and the input code from the different input codes that causes the frequency of the output signal to equal the starting ramp frequency is determined; and The determined input code is used to generate the first oscillator control signal.

29. The method of claim 27, wherein determining the first oscillator control signal comprises: When the frequency of the output signal is equal to the starting ramp frequency, the oscillator control signal whose frequency is equal to the starting ramp frequency at that point is digitized and stored. as well as When the frequency of the output signal is equal to the end ramp frequency, the stored oscillator control signal is converted back to an analog signal, and the oscillator control signal at which the frequency of the output signal is equal to the start ramp frequency is applied.

30. The method of claim 27, further comprising: The frequency of the reference signal is compared with the frequency of the frequency-divided feedback signal, and the charge pump control signal is generated based on whether the frequency of the reference signal is greater than the frequency of the frequency-divided feedback signal, or whether the frequency of the frequency-divided feedback signal is greater than the frequency of the reference signal.

31. The method of claim 27, wherein the divisor is changed in the following manner: A Σ-Δ modulator is used to generate control signals for the frequency divider circuit. A ramp signal is generated and provided to a multiplexer; Receive the current count from the resettable counter, and output a lookup table entry from the lookup table based on the current count; Interpolate the table entries received from the lookup table; Generate a Σ-Δ modulator input. If the Σ-Δ modulator input is fed as an input to the Σ-Δ modulator, it will cause the divisor to change, such that the frequency of the output signal decays over time from the end ramp frequency to the start ramp frequency according to a first-order exponential function. as well as The multiplexer selects the ramp signal for output during the ramp period and selects the Σ-Δ modulator input for output during the retrace period.

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