Current-steering comparator and capacitor control method

Abstract

The current-steering comparator includes an amplifier circuit, a bias circuit, a latch circuit, and a detection circuit. The amplifier circuit is used to compare a first input signal and a second input signal during a comparison period to output a first signal and a second signal. The bias circuit is used to bias the amplifier circuit using an adjustable capacitor during the comparison period. The latch circuit is used to generate a first output signal and a second output signal according to the first signal and the second signal during the comparison period. The detection circuit is used to detect the first output signal and the second output signal according to a preset frequency signal to generate a control signal to adjust the adjustable capacitor.

Description

Technical Field

[0001] The present invention relates to a comparator circuit, and more particularly to a current-steering comparator with dynamic bias and a capacitance control method. Background Art

[0002] Comparator circuits are often used in quantizers to convert analog signals into digital signals. In order to achieve high resolution, the comparator circuit needs to have better noise performance. In order to achieve high conversion rate, the comparator circuit needs to have faster operating speed. However, in existing comparator circuits, the noise performance is often opposite to the operating speed. Furthermore, due to process / voltage / temperature variations, the level of the internal node of the comparator circuit is not easy to accurately control, making it more difficult to master the performance of the comparator circuit. Summary of the invention

[0003] In some embodiments, the current-steering comparator includes an amplifier circuit, a bias circuit, a latch circuit, and a detection circuit. The amplifier circuit is used to compare a first input signal and a second input signal during a comparison period to output a first signal and a second signal. The bias circuit is used to bias the amplifier circuit using an adjustable capacitor during the comparison period. The latch circuit is used to generate a first output signal and a second output signal according to the first signal and the second signal during the comparison period. The detection circuit is used to detect the first output signal and the second output signal according to a preset frequency signal to generate a control signal to adjust the adjustable capacitor.

[0004] In some embodiments, a capacitance control method includes the following operations: biasing an amplifier circuit of a current-steering comparator during a comparison period by a bias circuit having an adjustable capacitor, wherein the amplifier circuit compares a first input signal and a second input signal during the comparison period to output a first signal and a second signal, and a latch circuit in the current-steering comparator generates a first output signal and a second output signal according to the first signal and the second signal during the comparison period; and detecting the first output signal and the second output signal according to a preset frequency signal to generate a control signal to adjust the adjustable capacitance.

[0005] The features, implementation and effects of the present invention will be described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a current-steering comparator according to some embodiments of the present invention;

[0007] Figure 2 According to some embodiments of the present invention, Figure 1 Schematic diagram of the capacitor array circuit in ;

[0008] Figure 3A According to some embodiments of the present invention, Figure 1 A schematic diagram of the detection circuit in FIG.

[0009] Figure 3B According to some embodiments of the present invention, Figure 1 A schematic diagram of the waveform of the frequency signal and the preset frequency signal; and

[0010] Figure 4 The figure is a flow chart showing a capacitance control detection method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0011] All words used herein have their usual meanings. The definitions of the above words in commonly used dictionaries, including any examples of words discussed herein, are for illustrative purposes only and should not limit the scope and meaning of the present invention. Similarly, the present invention is not limited to the various embodiments shown in this specification.

[0012] As used herein, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive component to process signals.

[0013] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, third, etc. are used to describe and identify each component. Therefore, the first component in this document can also be referred to as the second component without departing from the original intention of the case. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

[0014] Figure 1 FIG. 1 is a schematic diagram of a current steering comparator 100 according to some embodiments of the present invention. In some embodiments, the current steering comparator 100 can be applied to various circuit systems (for example, but not limited to, a digital-to-analog converter circuit system and an analog-to-digital converter circuit system).

[0015] The current-steering comparator 100 includes an amplifier circuit 110, a latch circuit 120, a bias circuit 130, and a detection circuit 140. The amplifier circuit 110 is used to compare the input signal IN1 and the input signal IN2 during the comparison period to generate a signal S1 and a signal S2. The latch circuit 120 is used to generate an output signal SO1 and an output signal SO2 according to the signal S1 and the signal S2 during the comparison period. The bias circuit 130 has an adjustable capacitor C tail , which can be used to reduce the noise of the amplifier circuit 110. The bias circuit 130 is used to use the adjustable capacitor C during the comparison period. tail Bias amplifier circuit 110. In some embodiments, the aforementioned comparison period may be a period when the clock signal CLK is at a high level.

[0016] In detail, the amplifier circuit 110 may include an input pair circuit 112 and a reset circuit 114. The input pair circuit 112 is used to compare the input signal IN1 and the input signal IN2 during the comparison period to output a signal S1 through the node N1 and a signal S2 through the node N2. The reset circuit 114 is used to adjust the level of the node N1 to a preset level (e.g., the voltage VDD) during the reset period, and adjust the level of the node N2 to the preset level. In some embodiments, the aforementioned reset period may be a period when the clock signal CLK has a low level.

[0017] For example, the input pair circuit 112 includes a transistor M1 and a transistor M2. The control terminal (e.g., gate) of the transistor M1 receives the input signal IN1. The first terminal (e.g., drain) of the transistor M1 is coupled to the node N1. The second terminal (e.g., source) of the transistor M1 is coupled to the bias circuit 130. The control terminal of the transistor M2 receives the input signal IN2. The first terminal of the transistor M2 is coupled to the node N2. The second terminal of the transistor M2 is coupled to the bias circuit 130. The reset circuit 114 includes a transistor M3 and a transistor M4. The first terminal (e.g., source) of the transistor M3 and the first terminal of the transistor M4 receive the voltage VDD. The second terminal (e.g., drain) of the transistor M3 is coupled to the node N1, and the second terminal of the transistor M4 is coupled to the node N2. The control terminal of the transistor M3 and the control terminal of the transistor M4 receive the clock signal CLK.

[0018] During the reset period (e.g., during the period when the clock signal CLK has a low level), the transistor M3 and the transistor M4 are turned on to transmit the voltage VDD to the node N1 and the node N2. Under this condition, the level of the node N1 and the level of the node N2 can be reset to the voltage VDD. During the comparison period (e.g., during the period when the clock signal CLK has a high level), the transistor M3 and the transistor M4 are not turned on. Under this condition, the transistor M1 and the transistor M2 can select to pull down the level of one of the node N1 and the node N2 according to the input signal IN1 and the input signal IN2, and maintain the level of the other of the node N1 and the node N2 to generate the signal S1 and the signal S2.

[0019] The bias circuit 130 includes a switch 132, a switch 134, and a capacitor array circuit 136. The switch 132 is coupled between the input pair circuit 112 and the capacitor array circuit 136 and is used to be turned on during the comparison period. The switch 134 is used to be turned on during the reset period to discharge the capacitor array circuit 136. The capacitor array circuit 136 is used to provide an adjustable capacitor C tail , where the adjustable capacitor C tail The capacitance of can be adjusted according to the control signal SC.

[0020] For example, the switch 132 may be implemented by (but not limited to) a transistor M5, and the switch 134 may be implemented by (but not limited to) a transistor M6. The first end of the transistor M5 is coupled to the second ends of both the transistor M1 and the transistor M2. The second end of the transistor M5 is coupled to the capacitor array circuit 136. The control end of the transistor M5 receives the frequency signal CLK. The first end of the transistor M6 is coupled to the second end of the transistor M5. The second end of the transistor M6 is coupled to the ground. The control end of the transistor M6 receives the frequency signal CLK'. The phase of the frequency signal CLK' is 180 degrees different from the phase of the frequency signal CLK. In other words, if the frequency signal CLK has a high level, the frequency signal CLK' has a low level. If the frequency signal CLK has a low level, the frequency signal CLK' has a high level.

[0021] During the period when the clock signal CLK has a low level (ie, a reset period), the transistor M6 is turned on to discharge the capacitor array circuit 136. Under this condition, the adjustable capacitor C tail The voltage on the node is the ground voltage. During the reset period, transistor M3 and transistor M4 are turned on to charge the parasitic capacitor (not shown) coupled to node N1 and the parasitic capacitor (not shown) coupled to node N2. During the period when the frequency signal CLK has a high level (i.e., the comparison period), transistor M5 is turned on and transistor M6 is not turned on. In this way, the parasitic capacitors coupled to nodes N1 and N2 begin to discharge to charge the adjustable capacitor C tail Under this condition, the adjustable capacitor C tailThe voltage on the adjustable capacitor C increases to reduce the gate-source voltage of the transistor M1 and reduce the gate-source voltage of the transistor M2. tail A dynamic bias can be provided to the input pair circuit 112 during the comparison period. By means of the above biasing method, the total input referred noise of the amplifier circuit 110 can be reduced. tail The lower the capacitance value, the lower the total input-related noise of the amplifier circuit 110. However, if the capacitance value is too low, the operation speed of the latch circuit 120 may be slowed down. As described later, by means of the detection circuit 140, the adjustable capacitor C tail The capacitance value can achieve a good balance between operating speed and noise performance.

[0022] The latch circuit 120 includes a plurality of transistors M7 to M14. The plurality of transistors M7 to M8, M10 to M12 and M14 form a positive feedback circuit, which can be used to generate an output signal SO1 and an output signal SO2 according to the signal S1 and the signal S2. The transistor M9 and the transistor M13 reset the level of the node N3 and the level of the node N4 during the reset period. For example, during the reset period, the transistor M9 and the transistor M13 are turned on according to the clock signal CLK' to pull the level of the node N3 and the level of the node N4 down to the ground. During the comparison period, if the signal S1 has a high level and the signal S2 has a low level, the transistor M8 is turned off and the transistor M12 is turned on. Under this condition, the level of the node N4 is pulled up to the voltage VDD to output the output signal SO1 with a high level. In response to the level of the node N4, the transistor M7 is turned off and the transistor M10 is turned on to pull the level of the node N3 down to the ground to output the output signal SO2 with a low level.

[0023] The above-mentioned configuration of the amplifier circuit 110, the latch circuit 120, and the bias voltage 130 is for example only, and the present invention is not limited thereto. In some embodiments, the plurality of transistors M1, M2, M5, M6, M9, M10, M13, and M14 may be N-type transistors, and the plurality of transistors M3, M4, M7, M8, M11, and M12 may be P-type transistors. In some embodiments, the above-mentioned transistors may be implemented by metal oxide field effect transistors (MOSFETs), but the present invention is not limited thereto. All types of transistors that can implement similar operations are within the scope of the present invention.

[0024] The detection circuit 140 is used to detect the output signal SO1 and the output signal SO2 according to the preset clock signal CLKd to generate the control signal SC. In some embodiments, the detection circuit 140 can be configured to detect the output signal SO1 and the output signal SO2 according to the preset clock signal CLKd in a preset period (e.g., Figure 3BThe output signal SO1 and the output signal SO2 are detected during a preset period T) to confirm whether the operating speeds of the amplifier circuit 110 and the latch circuit 120 meet the preset requirements. If the operating speeds do not meet the preset requirements, the detection circuit 140 can output a corresponding control signal SC to adjust the adjustable capacitor C tail By adjusting the adjustable capacitor C tail The capacitance value can adjust the operating speed of both the amplifier circuit 110 and the latch circuit 120.

[0025] In some related technologies, capacitors with fixed capacitance are used to implement bias circuits. In these technologies, due to process variation, voltage variation and / or temperature variation, the threshold voltages of multiple input pairs of circuits (for example, transistors M1 and transistors M2) and the power supply voltage (for example, voltage VDD) will be offset. As a result, the capacitance of the capacitor and the level of the internal nodes of the comparator circuit (for example, nodes N1 and N2) cannot be accurately controlled, resulting in possible failure of the circuit operation or affecting the operation of the next stage circuit (for example, latch circuit 120). Compared to the above-mentioned related technologies, in some embodiments of the present case, by setting a capacitor array circuit 136, the detection circuit 140 can confirm the operating speed of the amplifier circuit 110 and the latch circuit 120 based on the output signal SO1 and the output signal SO2. If the operating speed does not meet the preset requirements, the detection circuit 140 can output a control signal SC to adjust the adjustable capacitor C tail In this way, under the influence of process variation, voltage variation and / or temperature variation, the performance of the current-steering comparator 100 can still meet the preset requirements.

[0026] Figure 2 According to some embodiments of the present invention, Figure 1 Schematic diagram of the capacitor array circuit 136 in FIG. The capacitor array circuit 136 includes a plurality of capacitors C and a plurality of switches SW. The plurality of switches SW are respectively coupled to the plurality of capacitors C and are selectively turned on according to the control signal SC. For example, the first switch SW receives the first bit [0] of the control signal SC, the second switch SW receives the second bit [1] of the control signal SC, and the third switch SW receives the third bit [2] of the control signal SC. By analogy, the corresponding relationship between the plurality of switches SW and the plurality of bits of the control signal SC can be understood.

[0027] exist Figure 1In the example, since transistor M8 and transistor M12 are P-type transistors, the level of node N1 and the level of node N2 will directly affect the operating speed of latch circuit 120. For example, the lower the level of node N1, the greater the driving current of transistor M8, so the operating speed will increase. Conversely, the higher the level of node N1, the smaller the driving current of transistor M8, so the operating speed will decrease. If the detection circuit 140 determines that the operating speeds of both amplifier circuit 110 and latch circuit 120 are too slow, the detection circuit 140 can output a corresponding control signal SC to turn on more switches SW. Under this condition, the adjustable capacitor C tail The capacitance of the adjustable capacitor C is increased to reduce the level of the node N1 and the level of the node N2. In this way, the operation speed of the latch circuit 120 can be increased. Alternatively, if the detection circuit 140 determines that the operation speed is too fast, the detection circuit 140 can output a corresponding control signal SC to make more switches SW non-conductive. Under this condition, the adjustable capacitor C tail The capacitance of the latch circuit 120 is reduced to increase the voltage levels of the node N1 and the node N2. In this way, the operation speed of the latch circuit 120 can be reduced.

[0028] Figure 3A According to some embodiments of the present invention, Figure 1 Schematic diagram of the detection circuit 140 in FIG. Figure 3B According to some embodiments of the present invention, Figure 1 Schematic diagram of the waveforms of the frequency signal CLK and the preset frequency signal CLKd in FIG. 140. The detection circuit 140 includes a logic gate circuit 310, a flip-flop circuit 320, and a processing circuit 330. The logic gate circuit 310 is used to generate a detection signal SD1 according to the output signal SO1 and the output signal SO2. Figure 3A In the example of FIG. 1 , the logic gate circuit 310 may be a NOR gate circuit. In other embodiments, according to the configuration of the amplifier circuit 110 , the logic gate circuit 310 may be (but not limited to) an exclusive OR gate circuit, a NAND gate circuit, etc.

[0029] As mentioned previously, during reset, Figure 1The level of the node N3 and the level of the node N4 in the reset period are reset to the ground voltage. Therefore, during the reset period, the logic gate circuit 310 can output the detection signal SD1 with a logic value of 1. If the amplifier circuit 110 and the latch circuit 120 can generate a comparison result during the comparison period, according to different comparison results, one of the node N3 and the node N4 will have a high level (that is, one of the output signal SO1 and the output signal SO2 has a high level), and the other of the node N3 and the node N4 will have a high level (that is, the other of the output signal SO1 and the output signal SO2 has a high level). In response to the output signal SO1 and the output signal SO2, the logic gate circuit 310 can output the detection signal SD1 with a logic value of 0. On the contrary, if the amplifier circuit 110 and the latch circuit 120 cannot generate a comparison result during the comparison period, the logic gate circuit 310 still outputs the detection signal SD1 with a logic value of 1.

[0030] The flip-flop circuit 320 is used to output the detection signal SD1 as the detection signal SD2 according to the preset frequency signal CLKd. The flip-flop circuit 320 can output the detection signal SD1 as the detection signal SD2 within a preset period T after the amplifier circuit 110 enters the comparison period. Figure 3B As shown, there is a delay time Td between the transition edge of the clock signal CLK (for example, but not limited to, a rising edge) and the transition edge of the preset clock signal CLKd (for example, but not limited to, a rising edge). The flip-flop circuit 320 may be (but not limited to) a D-type flip-flop circuit, which may output the detection signal SD1 as the detection signal SD2 according to the rising edge of the preset clock signal CLKd.

[0031] The processing circuit 330 is used to determine whether the operating speeds of the amplifier circuit 110 and the latch circuit 120 meet the preset requirements according to the detection signal SD2, so as to generate the control signal SC. For example, if the detection signal SD2 is a logic value of 0, it means that the amplifier circuit 110 and the latch circuit 120 cannot generate a comparison result within the comparison period (i.e., the operating speeds of the amplifier circuit 110 and the latch circuit 120 are too slow to meet the preset requirements). Under this condition, the processing circuit 330 can output the corresponding control signal SC to increase the adjustable capacitor C tail Alternatively, if the detection signal SD2 is a logic value of 1, it means that the amplifier circuit 110 and the latch circuit 120 are able to generate a comparison result within the comparison period (i.e., the operation speeds of the amplifier circuit 110 and the latch circuit 120 meet the preset requirements). Under this condition, the processing circuit 330 can output a corresponding control signal SC to reduce the adjustable capacitor C tail Thus, the noise of the amplifier circuit 110 can be further reduced. By repeatedly performing the above operation, the adjustable capacitor Ctail The capacitance value can achieve a better balance between operating speed and noise performance under process variation, voltage variation and / or temperature variation. In some embodiments, the processing circuit 330 can be implemented as a microcontroller circuit, a digital signal processing circuit or other digital circuit with processing capabilities. In some embodiments, the aforementioned preset requirements can be determined according to the actual application of the current-steering comparator 100. For example, when the current-steering comparator 100 is applied to an analog-to-digital converter circuit, the preset requirements can be determined according to the conversion time of the analog-to-digital converter.

[0032] Figure 4 The flowchart of a capacitance control method 400 is shown according to some embodiments of the present invention. In some embodiments, the capacitance control method 400 is used for (but not limited to) adjusting a variable capacitance in a comparator circuit.

[0033] In operation S410, a bias circuit (e.g., Figure 1 The bias circuit 130 of the current steering comparator is biased during the comparison period to bias the amplifier circuit (e.g. Figure 1 The amplifier circuit 110) includes an amplifier circuit 110, wherein the amplifier circuit compares the first input signal and the second input signal during the comparison period to output the first signal and the second signal, and the latch circuit (e.g., Figure 1 The latch circuit 120 generates a first output signal and a second output signal according to the first signal and the second signal during the comparison period. In operation S420, the first output signal and the second output signal are detected according to the preset frequency signal to generate a control signal to adjust the adjustable capacitance.

[0034] The description of the above-mentioned multiple operations can refer to the above-mentioned embodiments, so it will not be repeated. The multiple operations of the above-mentioned capacitance control method 400 are only examples and are not limited to be performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present case, the various operations under the capacitance control method 400 can be appropriately increased, replaced, omitted or performed in a different order (for example, they can be performed simultaneously or partially simultaneously).

[0035] In summary, the current-steering comparator and capacitance control method in some embodiments of the present invention can accurately adjust the capacitance of the variable capacitor in the comparator under process variation, voltage variation and / or temperature variation to achieve a better balance between noise performance and operating speed.

[0036] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Ordinary technicians in this technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of the patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on the scope of the claims of this specification.

[0037]

Explanation of symbols

[0038] 100: Current-steering comparator

[0039] 110: Amplifier Circuit

[0040] 112: Input to circuit

[0041] 114: Reset circuit

[0042] 120: Latch circuit

[0043] 130: Bias circuit

[0044] 132, 134: switch

[0045] 136: Capacitor Array Circuit

[0046] 140: Detection circuit

[0047] 310: Logic Gate Circuit

[0048] 320: Flip-flop circuit

[0049] 330: Processing circuit

[0050] 400: Capacitor Control Method

[0051] [0], [1], [2]: Bit

[0052] C: Capacitance

[0053] CLK, CLK': frequency signal

[0054] CLKd: preset frequency signal

[0055] C tail : Adjustable capacitor

[0056] IN1, IN2: input signal

[0057] M1~M14: Transistor

[0058] N1~N4:Node

[0059] S1, S2: Signal

[0060] S410, S420: Operation

[0061] SC: Control signal

[0062] SD1, SD2: detection signal

[0063] SO1, SO2: output signal

[0064] SW: Switch

[0065] T: Default period

[0066] Td: delay time

[0067] VDD: voltage

Claims

1. A current-steering comparator, comprising: an amplifier circuit for comparing a first input signal with a second input signal during a comparison period to output a first signal and a second signal; a bias circuit for biasing the amplifier circuit using an adjustable capacitor during the comparison period; A latch circuit for generating a first output signal and a second output signal according to the first signal and the second signal during the comparison period; as well as A detection circuit is used to detect the first output signal and the second output signal according to a preset frequency signal to generate a control signal to adjust the adjustable capacitor, wherein the detection circuit includes: A logic gate circuit, used for generating a first detection signal according to the first output signal and the second output signal; a flip-flop circuit, configured to output the first detection signal as a second detection signal according to the preset frequency signal; and The processing circuit is used for determining whether the operation speeds of the amplifier circuit and the latch circuit meet the preset requirements according to the second detection signal, so as to generate the control signal. 2 . The current-steering comparator as claimed in claim 1 , wherein the detection circuit is used for detecting the first output signal and the second output signal during a preset period after the amplifier circuit enters the comparison period.

3. The current-steering comparator as claimed in claim 1, wherein the amplifier circuit is used to enter the comparison period according to a frequency signal, and a transition edge of the frequency signal differs from a transition edge of the preset frequency signal by a delay time.

4. The current-steering comparator of claim 1 , wherein the amplifier circuit comprises: A reset circuit, used to adjust the level of the first node to a preset level and adjust the level of the second node to the preset level during a reset period; as well as The input pair circuit is used for comparing the first input signal with the second input signal to output the first signal through the first node and output the second signal through the second node.

5. The current-steering comparator as claimed in claim 4, wherein the bias circuit comprises: A capacitor array circuit, used to provide the adjustable capacitance; A first switch is coupled between the input pair circuit and the capacitor array circuit and is used to be turned on during the comparison period; The second switch is used to be turned on during the reset period to discharge the capacitor array circuit.

6. The current-steering comparator as claimed in claim 5, wherein the capacitor array circuit comprises: Multiple capacitors; as well as A plurality of third switches are respectively coupled to the capacitors and are used for selectively being turned on according to the control signal. 7 . The current-steering comparator as claimed in claim 1 , wherein the flip-flop circuit outputs the second detection signal within a preset period after the amplifier circuit enters the comparison period. 8 . The current-steering comparator as claimed in claim 1 , wherein if the operating speed does not meet the preset requirement, the processing circuit outputs the control signal to increase the capacitance of the adjustable capacitor.

9. A capacitance control method, comprising: biasing an amplifier circuit of a current-steering comparator during a comparison period by a bias circuit having an adjustable capacitor, wherein the amplifier circuit compares a first input signal with a second input signal during the comparison period to output a first signal and a second signal, and a latch circuit in the current-steering comparator generates a first output signal and a second output signal according to the first signal and the second signal during the comparison period; and The first output signal and the second output signal are detected according to a preset frequency signal to generate a control signal to adjust the adjustable capacitor, wherein a first detection signal is generated according to the first output signal and the second output signal by a logic gate circuit, the first detection signal is output as a second detection signal according to the preset frequency signal by a flip-flop circuit, and whether the operating speeds of the amplifier circuit and the latch circuit meet the preset requirements is determined by a processing circuit according to the second detection signal to generate the control signal.

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