Memory fault handling methods and devices
By identifying memory fault types through a pre-trained fault prediction model and directly restarting the device, the problem of hardware device downtime caused by memory faults is solved, the repair time is reduced, and the processing efficiency and user transaction effectiveness are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ALIBABA (CHINA) CO LTD
- Filing Date
- 2022-04-18
- Publication Date
- 2026-05-26
AI Technical Summary
In existing technologies, memory failures can cause hardware devices to crash, resulting in long repair times and impacting the effectiveness of user transactions.
The pre-trained fault prediction model identifies memory fault types. If the fault is a restartable and repairable type, the device is restarted directly to reduce repair time.
It reduces the time required to recover from memory failures, improves processing efficiency, and ensures the effectiveness of user transactions.
Smart Images
Figure CN114691409B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to a method and apparatus for handling memory faults. Background Technology
[0002] With the development of network technology, more and more hardware devices are being used, and all programs run in memory, so memory performance has a great impact on hardware devices.
[0003] In existing technologies, memory failure is a common type of failure that can potentially cause hardware devices to crash. To mitigate the impact of crashes, it is possible to predict which hardware devices are at risk of failure. Once identified, user virtual machines on these risky devices can be migrated in advance.
[0004] However, after migrating user virtual machines from hardware devices at risk of failure, it usually takes a long time to stress test and repair the memory modules on those devices, increasing the time required to repair memory failures and thus affecting the effectiveness of user transactions. Summary of the Invention
[0005] This application provides a memory fault handling method and apparatus to reduce the repair time of hardware device memory faults.
[0006] In a first aspect, embodiments of this application provide a memory fault handling method, including:
[0007] Obtain memory fault data;
[0008] The memory fault data is input into a pre-trained fault prediction model to obtain fault identification results;
[0009] If the fault identification result is a restartable and repairable fault, then restart the device under test.
[0010] Optionally, inputting the memory fault data into a pre-trained fault prediction model to obtain fault identification results includes:
[0011] Determine whether the memory device corresponding to the memory fault data needs to be taken offline based on the pre-stored offline rules;
[0012] If it is determined that the memory device corresponding to the memory fault data needs to be taken offline, the memory fault data is input into a pre-trained fault prediction model to obtain the fault identification result.
[0013] Optionally, if the fault identification result is a restartable and repairable fault, then restarting the device under test includes:
[0014] If the fault identification result is a restartable and repairable fault, then determine whether each software model in the device under test is the latest version;
[0015] If all software models in the device under test are the latest versions, then restart the device under test;
[0016] If any software model in the device under test is not the latest version, then update the operating system of the device under test and restart the device under test after updating the operating system.
[0017] Optionally, after obtaining the fault identification result, the method further includes:
[0018] If the fault identification result is a non-repairable fault, then the memory device in the device under test is repaired according to the preset repair rules.
[0019] Optionally, before acquiring memory fault data, the method further includes:
[0020] Obtain a memory fault training dataset, wherein the memory fault training dataset contains multiple memory fault training data, and each memory fault training data contains memory state data and fault type;
[0021] The memory state data and the corresponding fault type are input into the network model for training to obtain the fault prediction model.
[0022] Optionally, after inputting the memory state data and the corresponding fault type into the network model for training to obtain the fault prediction model, the method further includes:
[0023] The fault prediction model is optimized and trained according to the preset optimization rules to obtain the optimized fault pre-stored model. The optimized fault pre-stored model can identify fault types that cannot be repaired by PPR after packaging and fault types that are difficult to reproduce by stress testing.
[0024] Optionally, after inputting the memory fault data into the pre-trained fault prediction model to obtain the fault identification result, the method further includes:
[0025] If the fault identification result is a non-repairable fault, then increase the interception priority of the fault type corresponding to the memory fault data.
[0026] Optionally, after restarting the device under test if the fault identification result is a restartable and repairable fault, the method further includes:
[0027] Store the memory fault data to obtain a list of faults that can be restarted and repaired;
[0028] After obtaining new memory fault data, determine whether the new memory fault data is in the list of restartable and repairable faults;
[0029] If the device is in the list of restartable and repairable faults, then restart the device under test.
[0030] Optionally, if the fault identification result is a restartable and repairable fault, then restarting the device under test includes:
[0031] If the fault identification result is a restartable and repairable fault, a device restart prompt will be generated;
[0032] In response to the confirmation control applied to the device restart prompt, the device under test is restarted within a preset time period.
[0033] Secondly, embodiments of this application provide a memory fault handling apparatus, comprising:
[0034] The acquisition module is used to acquire memory fault data;
[0035] The processing module is used to input the memory fault data into a pre-trained fault prediction model to obtain fault identification results;
[0036] The processing module is further configured to restart the device under test if the fault identification result is a restartable and repairable fault.
[0037] This application provides a memory fault handling method and apparatus. By adopting the above scheme, memory fault data can be obtained first, and then the memory fault data can be input into a pre-trained fault prediction model to obtain fault identification results. If the fault identification result is a restartable and repairable fault, the device under test can be restarted. By directly repairing the memory fault by restarting after determining that the memory fault is a restartable and repairable fault type, the repair time of the memory fault of the device under test is reduced, the processing efficiency of memory faults is improved, and the implementation effect of user transactions is guaranteed. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 A schematic diagram of the application system architecture for the memory fault handling method provided in the embodiments of this application;
[0040] Figure 2 A flowchart illustrating the memory fault handling method provided in an embodiment of this application;
[0041] Figure 3 A schematic diagram illustrating the principle of the memory fault handling method provided in the embodiments of this application;
[0042] Figure 4 A schematic diagram illustrating the principle of the fault prediction model training process provided in the embodiments of this application;
[0043] Figure 5 This is a schematic diagram of the structure of the memory fault handling device provided in the embodiments of this application;
[0044] Figure 6 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can also include other sequential examples besides those illustrated or described. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0047] Memory failures, the causes of memory errors, can generally be categorized into soft failures and hard failures. Hard failures typically refer to unrecoverable hardware errors, such as a stuck-at bit, where the bit always has a fixed value. For example, a stuck-at 0 bit means that regardless of what value (0 or 1) is written, the value of this bit is always 0. Soft failures, on the other hand, are caused by random events, such as rays or backplane radiation, and can usually be repaired by rewriting. Memory failures can cause hardware devices to crash, significantly impacting the reliability, availability, and serviceability of the operating system. Memory failures can sometimes generate uncorrectable errors or memory error storms. In cloud computing environments, uncorrectable errors can cause system crashes, affecting system availability, while memory error storms can lead to impaired system performance or even system unavailability. To reduce unexpected crashes and performance impacts caused by memory failures, hardware devices at risk of failure can be predicted in advance. Once identified, user virtual machines on these devices can be migrated in advance. For example, hot migration can be used to migrate user virtual machines on hardware devices at risk of failure. However, after the hot migration is completed, it usually takes a long time (usually 4 to 6 days) to stress test all memory modules of the risky machine to find the faulty rows. Then, PPR (Post Package Repair) is used to repair and isolate the faulty rows, which increases the processing time of hardware memory failures and thus affects the implementation effect of user transactions.
[0048] Based on the aforementioned technical issues, this application addresses the problem by directly repairing the memory fault through a restart after determining that the memory fault is a type that can be repaired by restarting. This approach achieves the technical effect of reducing the repair time of memory faults in the device under test, improving the processing efficiency of memory faults, and thus ensuring the effectiveness of user transactions.
[0049] Figure 1 A schematic diagram of the application system architecture for the memory fault handling method provided in the embodiments of this application is shown below. Figure 1 As shown, this application system may include a central server 101 and devices under test 102. The central server 101 may be equipped with a trained fault prediction model. There may be multiple devices under test 102, each containing a memory device (exemplarily, a memory module). The central server 101 can acquire memory fault data generated by the memory devices in each device under test 102 and input this data into the fault prediction model to obtain a fault identification result for each device under test 102. If the fault identification result for any device under test is a restartable and repairable fault, the device under test can be restarted to repair the memory fault.
[0050] In addition, the central server 101 can also obtain memory fault data of its own memory devices and input the memory fault data into the fault prediction model to obtain the fault identification result of the central server 101.
[0051] In addition, the application system may not include a central server 101, and a fault prediction model may be deployed in each device under test 102. The processor in the device under test 102 can obtain memory fault data of its own memory device, and input the memory fault data into the fault prediction model to obtain the fault identification result of the device under test 102.
[0052] The device to be tested 102 can be a server, smartphone, personal computer, or smart wearable device, etc.
[0053] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0054] Figure 2 This is a flowchart illustrating a memory fault handling method provided in an embodiment of this application. The method in this embodiment can be executed by a central server 101 or a device under test 102. Figure 2 As shown, the method in this embodiment may include:
[0055] S201: Obtain memory fault data.
[0056] In this embodiment, when repairing memory device faults, memory fault data can be obtained first, and then the memory device can be repaired based on the obtained memory fault data. The memory fault data can be data directly obtained from the logs generated by the memory device, indicating the operating status of each memory device. For example, the memory fault data may include memory model, fault location, fault type, etc. The fault type can include any one or more combinations of row faults, column faults, hard cell faults, and bank faults. A cell is the basic unit of memory storage, and a bank is a two-dimensional array composed of cells.
[0057] Furthermore, there are several ways to obtain memory fault data. For example, memory fault data can be obtained every preset time interval, or it can be obtained directly when the firmware or operating system detects a memory error.
[0058] S202: Input the memory fault data into the pre-trained fault prediction model to obtain the fault identification result.
[0059] In this embodiment, through multiple data analyses, it was discovered that specific fault types in certain batches of memory modules can be repaired by restarting. For example, column faults in some batches are caused by failures in the four DQs (Data Queues, output channels) of a single DRAM chip, which can be repaired by restarting. Alternatively, due to manufacturing processes, the center offset of input / output devices may accumulate after prolonged use, which can also be corrected by restarting. Therefore, to save on fault repair costs, once it is determined that a memory fault can be repaired by restarting, the stress testing and repair steps can be skipped. This saves manpower and time costs associated with stress testing and repair, and improves the efficiency of memory fault repair. Therefore, after obtaining the memory fault data, it can be directly input into a pre-trained fault prediction model to determine the fault identification result.
[0060] The fault identification results can be of two types: one is a restartable repairable fault, which indicates a memory fault that can be repaired by restarting; the other is a non-restartable repairable fault, which indicates a memory fault that cannot be repaired by restarting.
[0061] S203: If the fault identification result is a restartable and repairable fault, then restart the device under test.
[0062] In this embodiment, after obtaining the fault identification result, if the fault identification result is a restartable and repairable fault, the device under test containing the faulty memory device can be directly restarted.
[0063] In addition, after obtaining the fault identification result, the following is also included:
[0064] If the fault identification result is a non-repairable fault, then the memory device in the device under test is repaired according to the preset repair rules.
[0065] Specifically, if the fault identification result is a non-repairable fault, the memory device in the device under test can be repaired using existing repair methods. This can be achieved through memory stress testing and repair. Memory stress testing involves generating specific bitstreams to read and write memory after the machine is taken offline for maintenance, triggering and reproducing common memory faults. These include faults such as fixed bit values, coupling faults, or faults caused by excessive charge loss. Once the fault is identified through stress testing, it can be repaired using PPR (Performance Reproducibility) methods. This involves replacing the faulty rows identified during stress testing with redundant healthy rows, thus isolating the faulty rows.
[0066] Furthermore, if the fault identification result is a restartable and repairable fault, then restarting the device under test may specifically include:
[0067] If the fault identification result is a restartable and repairable fault, a device restart prompt will be generated.
[0068] In response to the confirmation control applied to the device restart prompt, the device under test is restarted within a preset time period.
[0069] In this embodiment, when the fault identification result is a restartable and repairable fault, a device restart prompt can be generated first. This prompt may include the text "The device needs to be restarted to repair the memory fault," as well as confirmation and rejection controls. Then, responding to the confirmation control in the device restart prompt, the virtual machine on the device under test can be migrated within a preset time period. After the migration is complete, the device under test can be restarted. The preset time period can be a pre-set time frame, selecting a period with fewer online users. For example, the preset time period can be between 12:00 AM and 2:00 AM, ensuring the normal operation of user transactions and improving the user experience for maintenance personnel by generating a device restart prompt.
[0070] By adopting the above scheme, memory fault data can be obtained first, and then the memory fault data can be input into a pre-trained fault prediction model to obtain fault identification results. If the fault identification result is a restartable and repairable fault, the device under test can be restarted. By directly repairing the memory fault by restarting after determining that the memory fault is a restartable and repairable fault type, the processing time of memory faults in the device under test is reduced, the processing efficiency of memory faults is improved, and the implementation effect of user transactions is guaranteed.
[0071] based on Figure 2 In addition to the method described herein, this specification also provides some specific implementation schemes of the method, which will be described below.
[0072] In another embodiment, the memory fault data is input into a pre-trained fault prediction model to obtain fault identification results, which may specifically include:
[0073] Determine whether the memory device corresponding to the memory fault data needs to be taken offline based on the pre-stored offline rules.
[0074] If it is determined that the memory device corresponding to the memory fault data needs to be taken offline, the memory fault data is input into a pre-trained fault prediction model to obtain the fault identification result.
[0075] After acquiring memory fault data, which may contain varying numbers and types of memory faults, some types have a greater impact and require immediate attention, while others have a smaller impact and can be temporarily ignored. Therefore, after acquiring the memory fault data, we can determine whether the memory device corresponding to the fault data needs to be taken offline based on pre-stored offline rules. Specifically, we need to determine if the number of memory faults in the data exceeds a certain threshold, or if the fault priority of the fault type exceeds a certain priority threshold. If the number of memory faults exceeds the threshold, or if the fault priority of the fault type exceeds the threshold, then the memory device corresponding to the fault data needs to be taken offline. The memory fault data can then be input into a pre-trained fault prediction model to obtain the fault identification result.
[0076] In addition, if the number of memory faults in the memory fault data does not exceed the number threshold, and the fault priorities of the memory fault types in the memory fault data do not exceed the priority threshold, it indicates that the memory device corresponding to the memory fault data does not need to be taken offline, and the device under test can continue to operate.
[0077] in addition, Figure 3 This is a schematic diagram illustrating the principle of the memory fault handling method provided in the embodiments of this application, as shown below. Figure 3 As shown, the method in this embodiment may include: when the firmware or operating system detects a memory fault, determining whether the memory device corresponding to the memory fault meets the offline conditions. If the offline conditions are met, then determining whether the memory fault is a fault that can be repaired by restarting. If the memory fault is a restart-repairable fault, then directly performing system reinstallation and restart operations, and then continuing to keep the device under test running. If the memory fault is a restart-unrepairable fault, then repairing the memory fault through stress testing and maintenance, then performing system reinstallation and restart operations, and continuing to keep the device under test running. Alternatively, if the offline conditions are not met, then the device under test can continue to run.
[0078] In summary, by only repairing memory faults when the corresponding memory devices need to be taken offline, the operation and maintenance process is optimized, the number of memory faults is reduced, the efficiency of memory fault handling is improved, and manpower and time costs are effectively saved.
[0079] Furthermore, in another embodiment, if the fault identification result is a restartable and repairable fault, then the device under test is restarted, which may specifically include:
[0080] If the fault identification result is a restartable and repairable fault, then determine whether each software model in the device under test is the latest version.
[0081] If all software models in the device under test are the latest versions, then restart the device under test.
[0082] If any software model in the device under test is not the latest version, then update the operating system of the device under test and restart the device under test after updating the operating system.
[0083] In this embodiment, after determining that the fault identification result is a restartable and repairable fault, it can first be checked whether all software models in the device under test are the latest versions. If all are the latest versions, it indicates that no software version update is required, and the device under test can be directly restarted to repair the memory fault. If one of the software models in the device under test is not the latest version, in order to reduce the number of subsequent software updates, the operating system of the device under test can be directly updated to update all software versions to the latest version, and then the device under test with the updated operating system can be restarted.
[0084] By updating the operating system to the latest version of each software model when the software model is not the latest version, and then restarting the device under test to repair the memory fault, the number of subsequent software updates is reduced, the stable running time of the device under test is increased, and the user experience is improved.
[0085] Furthermore, in another embodiment, before acquiring the memory fault data, the method may further include:
[0086] Obtain a memory fault training dataset, wherein the memory fault training dataset contains multiple memory fault training data, and each memory fault training data contains memory state data and fault type.
[0087] The memory state data and the corresponding fault type are input into the network model for training to obtain the fault prediction model.
[0088] In this embodiment, a fault prediction model can be obtained by training a network model. Subsequently, based on the fault prediction model, it can be determined whether the fault type of the memory device is a restartable and repairable fault.
[0089] Furthermore, a fault prediction model can be obtained by training the network model on a memory fault training dataset containing multiple sets of memory state data and corresponding fault types. The fault types can include restartable and non-restartable faults.
[0090] The memory status data can be offline raw memory error data (i.e., memory error logs), combined with hardware model, firmware, and operating system configuration. Fault type can serve as a label for the training data, indicating whether the memory fault has been repaired within a preset time period after restarting the device under test, based on the raw memory error data (the result can be a repairable fault or a non-repairable fault). The preset time period can be six months or one year.
[0091] In addition, memory status data can also be used to generate micro-level memory fault type statistics (such as: number of memory row / column faults, number of hard cell faults, range and concentration of row / column faults, etc.) after obtaining the raw offline memory error data.
[0092] In addition, after inputting the memory state data and the corresponding fault type into the network model for training to obtain the fault prediction model, the process further includes:
[0093] The fault prediction model is optimized and trained according to the preset optimization rules to obtain the optimized fault pre-stored model. The optimized fault pre-stored model can identify fault types that PPR cannot repair and fault types that are difficult to reproduce by stress testing.
[0094] Specifically, after training a fault prediction model based on a memory fault training dataset, there may be memory faults that the model cannot identify but can still be repaired by restarting. Therefore, the fault prediction model can be optimized and trained using memory domain expertise to obtain a model that can identify fault types that cannot be repaired by PPR (Problem Resolver) and fault types that are difficult to reproduce during load testing. Examples include column faults that cannot be repaired by PPR, faults that cannot be reproduced during load testing due to long-link I / O device failures, and faults specific to certain memory batches.
[0095] in addition, Figure 4 This is a schematic diagram illustrating the principle of the fault prediction model training process provided in the embodiments of this application, as follows: Figure 4As shown, the method in this embodiment may include: acquiring memory error data streams in real time, storing the memory error data streams in an error data warehouse, performing statistical analysis and classification of fault types on the memory error data streams in the error data warehouse, i.e., micro-level memory fault type statistics (e.g., number of memory row / column faults, number of hard cell faults, row / column fault range and concentration, etc.), and then combining this with the model of the device under test and the configuration of the operating system to obtain memory status data, training a network model to obtain an initial fault prediction model. The initial fault prediction model can also be optimized using professional knowledge in the memory field to obtain a final fault prediction model. Using this fault prediction model, the acquired memory error data streams can be predicted to determine whether the memory fault is a type that can be repaired by restarting.
[0096] In summary, by optimizing the trained fault prediction model, the model can identify memory faults that the model could not recognize under certain special circumstances, but which can still be repaired by restarting, thus improving the accuracy of memory fault identification.
[0097] Furthermore, in another embodiment, after inputting the memory fault data into a pre-trained fault prediction model to obtain fault identification results, the method may further include:
[0098] If the fault identification result is a non-repairable fault, then increase the interception priority of the fault type corresponding to the memory fault data.
[0099] In this embodiment, if the fault identification result is a non-repairable fault, it indicates that the memory fault contained in the memory fault data cannot be repaired by restarting. Therefore, the memory fault can be repaired using existing repair methods. Furthermore, this type of non-repairable memory fault increases the risk of the device under test crashing. Therefore, the interception priority of the fault type corresponding to this memory fault data can be increased. After determining this fault type, memory faults of this type are repaired first, reducing the risk of the device under test crashing.
[0100] Furthermore, in another embodiment, after restarting the device under test if the fault identification result is a restartable and repairable fault, the method may further include:
[0101] The memory fault data is stored to obtain a list of faults that can be restarted and repaired.
[0102] After obtaining new memory fault data, determine whether the new memory fault data is in the list of restartable and repairable faults.
[0103] If the device is in the list of restartable and repairable faults, then restart the device under test.
[0104] In this embodiment, after determining that the memory fault contained in the memory fault data is a restartable and repairable fault through the fault prediction model, the memory fault data can be stored in the restartable and repairable fault list. Subsequently, upon acquiring new memory fault data, it can be first determined whether the new memory fault data is in the restartable and repairable fault list. If it is in the restartable and repairable fault list, it indicates that the fault type contained in the memory fault data is a restartable and repairable fault type, and the device under test can be directly restarted. If the new memory fault data is not in the restartable and repairable fault list, but is in the list, the memory fault data is input into the pre-trained fault prediction model to obtain the fault identification result. If the fault identification result is a restartable and repairable fault, the device under test is restarted, and the memory fault data is stored in the restartable and repairable fault list.
[0105] In summary, by storing memory fault data that can be restarted and repaired in a list of restartable and repairable faults, the number of times it is necessary to determine whether memory fault data can be restarted and repaired is reduced, thereby reducing the workload of hardware devices.
[0106] Based on the same idea, this specification also provides an apparatus corresponding to the above method. Figure 5 This is a schematic diagram of the structure of the memory fault handling device provided in the embodiments of this application, as shown below. Figure 5 As shown, the apparatus provided in this embodiment may include:
[0107] Module 501 is used to acquire memory fault data.
[0108] The processing module 502 is used to input the memory fault data into a pre-trained fault prediction model to obtain fault identification results.
[0109] The processing module 502 is further configured to restart the device under test if the fault identification result is a restartable and repairable fault.
[0110] In this embodiment, the processing module 502 is further configured to:
[0111] If the fault identification result is a non-repairable fault, then the memory device in the device under test is repaired according to the preset repair rules.
[0112] Furthermore, the processing module 502 is also used for:
[0113] If the fault identification result is a restartable and repairable fault, a device restart prompt will be generated.
[0114] In response to the confirmation control applied to the device restart prompt, the device under test is restarted within a preset time period.
[0115] Furthermore, in another embodiment, the processing module 502 is also used for:
[0116] Determine whether the memory device corresponding to the memory fault data needs to be taken offline based on the pre-stored offline rules.
[0117] If it is determined that the memory device corresponding to the memory fault data needs to be taken offline, the memory fault data is input into a pre-trained fault prediction model to obtain the fault identification result.
[0118] Furthermore, in another embodiment, the processing module 502 is also used for:
[0119] If the fault identification result is a restartable and repairable fault, then determine whether each software model in the device under test is the latest version.
[0120] If all software models in the device under test are the latest versions, then restart the device under test.
[0121] If any software model in the device under test is not the latest version, then update the operating system of the device under test and restart the device under test after updating the operating system.
[0122] Furthermore, in another embodiment, the processing module 502 is also used for:
[0123] Obtain a memory fault training dataset, wherein the memory fault training dataset contains multiple memory fault training data, and each memory fault training data contains memory state data and fault type.
[0124] The memory state data and the corresponding fault type are input into the network model for training to obtain the fault prediction model.
[0125] In this example, the processing module 502 is further configured to:
[0126] The fault prediction model is optimized and trained according to the preset optimization rules to obtain the optimized fault pre-stored model. The optimized fault pre-stored model can identify fault types that cannot be repaired by PPR after packaging and fault types that are difficult to reproduce by stress testing.
[0127] Furthermore, in another embodiment, the processing module 502 is also used for:
[0128] If the fault identification result is a non-repairable fault, then increase the interception priority of the fault type corresponding to the memory fault data.
[0129] Furthermore, in another embodiment, the processing module 502 is also used for:
[0130] The memory fault data is stored to obtain a list of faults that can be restarted and repaired.
[0131] After obtaining new memory fault data, determine whether the new memory fault data is in the list of restartable and repairable faults.
[0132] If the device is in the list of restartable and repairable faults, then restart the device under test.
[0133] The apparatus provided in this application embodiment can achieve the above-mentioned... Figure 2 The methods in the embodiments shown are similar in principle and technical effect, and will not be described again here.
[0134] Figure 6 A schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application, such as... Figure 6 As shown, the device 600 provided in this embodiment includes a processor 601 and a memory communicatively connected to the processor. The processor 601 and the memory 602 are connected via a bus 603.
[0135] In a specific implementation, the processor 601 executes the computer execution instructions stored in the memory 602, causing the processor 601 to execute the method in the above method embodiment.
[0136] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0137] In the above Figure 6 In the illustrated embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0138] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage.
[0139] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0140] This application also provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the memory fault handling method described in the above method embodiments.
[0141] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the memory fault handling method described above.
[0142] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0143] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0144] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A memory failure handling method, characterized by, include: Obtain memory fault data; The memory fault data is input into a pre-trained fault prediction model to obtain fault identification results; If the fault identification result is a restartable and repairable fault, then restart the device under test; Wherein, if the fault identification result is a restartable and repairable fault, then restarting the device under test includes: If the fault identification result is a restartable and repairable fault, then determine whether each software model in the device under test is the latest version; If all software models in the device under test are the latest versions, then restart the device under test; If any software model in the device under test is not the latest version, then update the operating system of the device under test and restart the device under test after updating the operating system.
2. The method of claim 1, wherein, The step of inputting the memory fault data into a pre-trained fault prediction model to obtain fault identification results includes: Determine whether the memory device corresponding to the memory fault data needs to be taken offline based on the pre-stored offline rules; If it is determined that the memory device corresponding to the memory fault data needs to be taken offline, the memory fault data is input into a pre-trained fault prediction model to obtain the fault identification result.
3. The method of claim 1, wherein, After obtaining the fault identification result, the following is also included: If the fault identification result is a non-repairable fault, then the memory device in the device under test is repaired according to the preset repair rules.
4. The method according to any one of claims 1 to 3, characterized in that, Before acquiring memory fault data, the following is also included: Obtain a memory fault training dataset, wherein the memory fault training dataset contains multiple memory fault training data, and each memory fault training data contains memory state data and fault type; The memory state data and the corresponding fault type are input into the network model for training to obtain the fault prediction model.
5. The method of claim 4, wherein, After inputting the memory state data and the corresponding fault type into the network model for training to obtain the fault prediction model, the method further includes: The fault prediction model is optimized and trained according to the preset optimization rules to obtain the optimized fault pre-stored model. The optimized fault pre-stored model can identify fault types that cannot be repaired by PPR after packaging and fault types that are difficult to reproduce by stress testing.
6. The method according to any one of claims 1 to 3, characterized in that, After inputting the memory fault data into the pre-trained fault prediction model to obtain the fault identification result, the method further includes: If the fault identification result is a non-repairable fault, then the interception priority of the fault type corresponding to the memory fault data is increased so as to prioritize the repair of memory faults of that type.
7. The method according to any one of claims 1 to 3, characterized in that, If the fault identification result is a restartable and repairable fault, then after restarting the device under test, the method further includes: Store the memory fault data to obtain a list of faults that can be restarted and repaired; After obtaining new memory fault data, determine whether the new memory fault data is in the list of restartable and repairable faults; If the device is in the list of restartable and repairable faults, then restart the device under test.
8. The method according to any one of claims 1-3, characterized in that, If the fault identification result is a restartable and repairable fault, then restarting the device under test includes: If the fault identification result is a restartable and repairable fault, a device restart prompt will be generated; In response to the confirmation control applied to the device restart prompt, the device under test is restarted within a preset time period.
9. A memory fault handling device, characterized in that, include: The acquisition module is used to acquire memory fault data; The processing module is used to input the memory fault data into a pre-trained fault prediction model to obtain fault identification results; The processing module is further configured to restart the device under test if the fault identification result is a restartable and repairable fault. The processing module is specifically used for: If the fault identification result is a restartable and repairable fault, then restarting the device under test includes: If the fault identification result is a restartable and repairable fault, then determine whether each software model in the device under test is the latest version; If all software models in the device under test are the latest versions, then restart the device under test; If any software model in the device under test is not the latest version, then update the operating system of the device under test and restart the device under test after updating the operating system.
10. An electronic device, characterized in that, include: Memory is used to store instructions executed by the computer; A processor for executing computer execution instructions stored in the memory, causing the processor to perform the memory fault handling method as described in any one of claims 1-8.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the memory fault handling method as described in any one of claims 1-8.
12. A computer program product, characterized in that, The program product includes a computer program that, when executed by a processor, implements the memory fault handling method as described in any one of claims 1-8.