A method, apparatus, storage medium, and electronic device for determining hardware performance

Abstract

Embodiments of the present application provide a method, apparatus, storage medium, and electronic device for determining hardware performance. The method comprises: obtaining multiple instruction sequences, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware; training a training model according to the mapping relationship to obtain a target training model; and determining a target performance parameter corresponding to the target instruction sequence based on the target training model. The present application automatically determines the performance parameter corresponding to the instruction sequence by generating a target training model with equivalent performance to a given piece of hardware, thereby efficiently obtaining the performance parameters of the hardware.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a method, device, storage medium, and electronic device for determining hardware performance. Background Art

[0002] Before writing hardware code, the performance and reliability of the hardware design must be evaluated in advance. Currently, hardware models are typically built using languages such as SystemC, C++, and SystemVerilog to complete a preliminary assessment of hardware performance. However, the complexity of modern hardware devices and the frequency of demand changes are increasing. The development of hardware performance simulators is becoming increasingly difficult, and the development speed and pace are no longer able to keep up with the frequency of hardware updates. Furthermore, developing performance simulators for complex hardware consumes significant human and physical resources. Therefore, how to quickly develop hardware performance simulators that meet user needs is an urgent issue. Summary of the Invention

[0003] Embodiments of the present application provide a method, apparatus, storage medium, and electronic device for determining hardware performance, which can efficiently obtain hardware performance parameters.

[0004] In a first aspect, an embodiment of the present application provides a method for determining hardware performance, the method comprising:

[0005] Acquire a plurality of instruction sequences, where a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware;

[0006] Training the training model according to the mapping relationship to obtain a target training model;

[0007] According to the target training model, target performance parameters corresponding to the target instruction sequence are determined.

[0008] In a second aspect, an embodiment of the present application provides a device for determining hardware performance, the device comprising:

[0009] an acquiring unit, configured to acquire a plurality of instruction sequences, wherein a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware;

[0010] A training unit, configured to train the training model according to the mapping relationship to obtain a target training model;

[0011] A determination unit is used to determine target performance parameters corresponding to a target instruction sequence based on the target training model.

[0012] In a third aspect, an embodiment of the present invention provides a combined processing device, comprising the device for determining hardware performance as described in the second aspect, a universal interconnect interface, and other processing devices. The device for determining hardware performance interacts with the other processing devices to jointly complete user-specified operations. The combined processing device may also include a storage device, which is connected to the device for determining hardware performance and the other processing devices, respectively, and is used to store data from the device for determining hardware performance and the other processing devices.

[0013] In a fourth aspect, this embodiment provides a neural network chip, which includes the device for determining hardware performance described in the second aspect, or the combined processing device described in the third aspect.

[0014] In a fifth aspect, an embodiment of the present application provides a neural network chip packaging structure, which includes the neural network chip described in the fourth aspect above.

[0015] In a sixth aspect, an embodiment of the present application provides a board comprising a memory device, an interface device, a control device, and the neural network chip described in the fourth aspect; wherein the neural network chip is connected to the memory device, the control device, and the interface device, respectively; the memory device is used to store data; the interface device is used to implement data transmission between the chip and an external device; and the control device is used to monitor the status of the chip.

[0016] In the seventh aspect, an embodiment of the present application provides an electronic device, which includes a memory, a processor, a communication bus and a communication interface, wherein the processor and the communication interface memory communicate with each other through the communication bus; the memory is used to store computer programs; and when the processor is used to execute the program stored in the memory, it implements some or all of the steps described in the first aspect above.

[0017] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, which includes a computer program for storing data exchange, and when the computer program is executed by a processor, implements some or all of the steps described in the first aspect of the embodiment of the present application.

[0018] In a ninth aspect, embodiments of the present application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute some or all of the steps described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

[0019] Embodiments of the present application provide a method and apparatus for determining hardware performance by obtaining multiple instruction sequences, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware; training a training model based on the mapping relationship to obtain a target training model; and determining target performance parameters corresponding to the target instruction sequence based on the target training model. The present application trains the training model using existing hardware parameters to obtain a target training model. Based on the target training model, performance parameters corresponding to any instruction sequence can be obtained, thus avoiding the time-consuming hardware simulation process and efficiently obtaining hardware performance parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 This is a flowchart of a method for determining hardware performance provided by an embodiment of the present application;

[0023] Figure 3a This is a schematic diagram of segmenting an instruction sequence provided in an embodiment of the present application;

[0024] Figure 3b This is a schematic diagram of another instruction sequence segmentation provided in an embodiment of the present application;

[0025] Figure 4 This is a schematic diagram of converting a signal into an instruction sequence provided by an embodiment of the present application;

[0026] Figure 5 1 is a flow chart of another method for determining hardware performance provided by an embodiment of the present application;

[0027] Figure 6a This is a block diagram of the functional units of a device for determining hardware performance provided by an embodiment of the present application;

[0028] Figure 6b This is a block diagram of the functional units of another device for determining hardware performance provided by an embodiment of the present application;

[0029] Figure 7 is a structural diagram of a combined processing device provided in an embodiment of the present application;

[0030] Figure 8This is a structural diagram of a board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0032] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] The present application will be described in detail below with reference to specific embodiments.

[0034] See also Figure 1 , Figure 1 is a structural diagram of an electronic device provided in an embodiment of the present application, such as Figure 1 As shown, the electronic device includes a memory, an input device, an output device and a processor, wherein the electronic device may further include a communication bus, and the processor, input device, output device and memory may be interconnected through the bus. Optionally, the above-mentioned electronic device may further include an instruction storage unit, which is arranged adjacent to the processor. Further optionally, the instruction storage unit is integrated with the processor, that is, the instruction storage unit is an on-chip storage unit of the processor. In this way, when the processor needs to execute a program in the memory, the electronic device first loads the program in the memory into the instruction storage unit, and then the processor can access the above-mentioned instruction storage unit to execute the program in the instruction storage unit.

[0035] The processor is configured to execute the program stored in the memory to implement the following steps:

[0036] Acquire multiple instruction sequences from a memory, where a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware; train a training model according to the mapping relationship to obtain a target training model; and determine a target performance parameter corresponding to the target instruction sequence based on the target training model.

[0037] Furthermore, the processor may be a central processing unit (CPU), an intelligence processing unit (NPU), a graphics processing unit (GPU), or an image processing unit, and this application does not limit this. Depending on the processor, the method for determining hardware performance proposed in the embodiment of the present application can be applied to artificial intelligence application fields such as image recognition processing, deep learning processing, computer vision processing, intelligent robot processing, and natural language processing, and execute complex functional programs in the field of artificial intelligence.

[0038] See also Figure 2 , Figure 2 This is a flow chart of a method for determining hardware performance provided by an embodiment of the present application, which is applied to a processor of an electronic device. Figure 2 As shown, the method includes the following steps:

[0039] S210: Acquire multiple instruction sequences, where a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware.

[0040] In a specific implementation, a computer program consists of an instruction sequence containing at least one instruction and data, and is stored in a memory. The electronic device invokes corresponding hardware to perform corresponding operations based on the instruction sequence in the memory. The instructions in the instruction sequence are binary instructions. The mapping relationship is a mapping relationship between the instruction sequence and the first performance parameter. Multiple instruction sequences may correspond to one or more first performance parameters.

[0041] Optionally, the at least one first performance parameter is a performance parameter obtained by respectively inputting the multiple instruction sequences into the target hardware.

[0042] In an embodiment of the present application, before training the training model, a training set needs to be constructed. The training set includes instruction sequences of multiple hardware. The instruction sequences of the multiple hardware are respectively input into given hardware for execution. The given hardware is already designed hardware, and then the process of the hardware executing the multiple instruction sequences is simulated, hardware tested and other technical means are used to obtain hardware performance parameters corresponding to the instruction sequence. Among them, the performance parameters of the hardware may include running time, energy consumption, latency, throughput, word length, frequency, etc. Each instruction sequence is respectively bound to the hardware performance parameters obtained by inputting the instruction sequence, and a mapping relationship between the instruction sequence and the first performance parameter is obtained, thereby constructing a training set for the training model.

[0043] Among them, the multiple instruction sequences may correspond to one or more first performance parameters. For example, the multiple instruction sequences are respectively input into the target hardware. If the multiple instruction sequences are all instruction sequences of the same operation or the same calculation instructions, then one second performance parameter may be obtained; if the multiple instruction sequences are used to perform different operations or different calculations, then multiple second performance parameters may be obtained.

[0044] Furthermore, the specific form of the above-mentioned given hardware can be determined according to user needs. Optionally, the given hardware may include but is not limited to one or more of hardware that bypasses the memory and central processing unit (CPU), memory, and CPU. The hardware that bypasses the memory and CPU is hardware that does not interact with the memory and CPU, such as a high-performance network card, remote direct memory access (RDMA), intelligent hardware, etc. Exemplarily, the hardware that bypasses the memory and CPU can be hardware of the PCI (Peripheral Component Interconnect) standard, or hardware of other standards, which is not specifically limited in the embodiments of the present application.

[0045] In one possible implementation, the method further includes: comparing the data length of the first instruction sequence with a preset length; if the data length of the first instruction sequence is greater than the preset length, dividing the first instruction sequence into multiple sub-instruction sequences, wherein the first instruction sequence is any instruction sequence among the multiple instruction sequences and / or the target instruction sequence.

[0046] In an embodiment of the present application, the longer the input instruction sequence, the larger the input of the instruction sequence, the higher its complexity, and the higher the performance requirements for the hardware. The hardware instruction sequence can be preliminarily simplified based on the instruction information. Therefore, in order to reduce the complexity of hardware simulation input and output, a longer instruction sequence is split, and the sum of the performance parameters of each subsequence obtained by the split is equal to the total performance parameters of the entire instruction sequence.

[0047] When constructing a training set, the data length of each instruction sequence in multiple instruction sequences is compared with the preset length. If the data length of an instruction sequence in the multiple instruction sequences is greater than the preset length, that is, the instruction sequence input once is too long, the instruction sequence corresponding to the data length greater than the preset length is divided into multiple sub-instruction sequences.

[0048] Among them, dividing the instruction sequence does not affect the performance parameters corresponding to the instruction sequence, that is, the performance parameters corresponding to the multiple sub-instruction sequences obtained by division are accumulated to obtain the performance parameters corresponding to the complete instruction sequence.

[0049] Optionally, dividing the first instruction sequence into multiple sub-instruction sequences includes: dividing the first instruction sequence into the multiple sub-instruction sequences of equal length; or, based on a synchronization instruction in the first instruction sequence, dividing the first instruction sequence into the multiple sub-instruction sequences, the synchronization instruction is used to instruct synchronization between hardware.

[0050] There are many ways to split the instruction sequence, for example, split the instruction sequence into equal lengths, such as Figure 3a As shown, the first instruction sequence is divided into a plurality of sub-instruction sequences of the same data length. The number or data length of the divided sub-instruction sequences can be set according to actual conditions.

[0051] Exemplarily, the instruction sequence can be segmented according to the instruction information, and the instruction information for performing the same or similar operations can be segmented into the same sub-instruction sequence. The instruction information includes an operation code and an operand, the operation code is used to indicate the function of the instruction, and the operand is used to identify the data for performing the operation, and the instructions for performing the same or similar operations can be segmented into the same sub-instruction sequence according to the operation code of the instruction. Some existing instruction sets have synchronization instructions, and the hardware performs time synchronization according to the synchronization instructions when executing the instruction sequence. The instruction sequences with different semantics are distinguished by the synchronization instructions as identifiers, and the instruction sequences with the same semantics are segmented together by the synchronization instructions. The instruction sequences with the same semantics are instruction sequences that include instruction information for performing the same or similar operations. For example, when performing calculations using a neural network model, the instructions for convolution operations in the instruction sequence are segmented into a sub-instruction sequence, and the instructions for pooling operations in the instruction sequence are segmented into another sub-instruction sequence.

[0052] Optionally, dividing the first instruction sequence into the multiple sub-instruction sequences based on the synchronization instructions in the first instruction sequence includes: searching for the synchronization instructions in the first instruction sequence; and dividing the first instruction sequence into the multiple sub-instruction sequences with each of the synchronization instructions as a dividing point.

[0053] Specifically, if Figure 3b As shown, the first instruction sequence includes multiple synchronization instructions. When constructing the instruction set, if the data length of the first instruction sequence is greater than a preset length, all synchronization instructions in the first instruction sequence are searched, and the first instruction sequence is divided into multiple sub-instruction sequences using each synchronization instruction in the first instruction sequence as a division point. The number of sub-instruction sequences depends on the number of synchronization instructions in the first instruction sequence, and the last instruction in the sub-instruction sequence is the synchronization instruction.

[0054] Among them, if the data length of the sub-command sequence is still greater than the preset length, the sub-command sequence can be further divided. For example, the sub-command sequence can be divided into equal lengths like the first command sequence mentioned above; the sub-command sequence can also be divided according to the preset length, that is, the sub-command sequence is divided with the preset length as the data length of the division. For example, the data length of the sub-command sequence is 250 bits, and the preset length is 64 bits. When divided according to the preset length, the sub-command sequence can be further divided into 4 sub-command sequences, whose data lengths are 64 bits, 64 bits, 64 bits and 58 bits respectively.

[0055] In a possible implementation, when the first instruction sequence is a signal group, the signal group includes a signal identifier and a first signal, and the signal identifier is used to indicate whether the first signal is valid at a current moment;

[0056] The method further includes: when the signal identifier indicates that the first signal is valid at the current moment, converting the first signal into the instruction sequence.

[0057] In practical applications, for hardware that inputs in a non-instruction sequence form, such as a Network on Chip (NoC), there may be multiple groups of input ports, each of which may input multiple signal groups. Each signal group includes a signal identifier and a first signal, and the first signal includes part or all of the instruction information in the instruction sequence. Since each signal group may include some instruction information, the hardware may need the instruction information in multiple signal groups together to perform a task. When the signal identifier in the signal group indicates that the first signal is valid at the current moment, the instruction information in the multiple signal groups is converted into an instruction sequence through preprocessing, which facilitates the intelligent algorithm to calculate its hardware performance parameters.

[0058] Optionally, converting the first signal into the instruction sequence includes: extracting instruction information from the first signals of the multiple groups of signal groups; and converting the instruction information into a binary string with the same format as the instruction sequence.

[0059] Specifically, if Figure 4As shown, the hardware includes N groups of input ports, each group of input ports inputs a group of signal groups. Therefore, the input of the hardware is N groups of signal groups. When the signal identifier Valid1 in the first signal group indicates that signal Signals1 is valid at the current moment, the signal identifier Valid2 in the second signal group indicates that signal Signals2 is valid at the current moment, ..., the signal identifier Valid N in the Nth signal group indicates that signal Signals N is valid at the current moment, Signals1, Signals2, ..., Signals N in the N signal groups can be converted into a group of binary strings with the same format as the instruction sequence through preprocessing. The preprocessing can include a hash algorithm, a compression algorithm, a splicing algorithm, etc.

[0060] S220: Train the training model according to the mapping relationship to obtain a target training model.

[0061] In an embodiment of the present application, the training model can be an intelligent algorithm whose input is an instruction sequence or a sub-instruction sequence and whose output is a hardware performance parameter. The intelligent algorithm can be a machine learning algorithm for classification, such as the K-means algorithm, the K-nearest neighbor (KNN) classification algorithm, a decision tree, etc., or a neural network algorithm, such as a recurrent neural network (RNN), a convolutional neural network (CNN), a long short-term memory network (LSTM), and various variant neural network algorithms.

[0062] Among them, the training of the training model uses the constructed training set to train the parameters of the entire intelligent algorithm until the training reaches the convergence of the intelligent algorithm. The convergence of the intelligent algorithm means that the intelligent algorithm obtains the global optimal solution to the problem under the assumption that the iteration time tends to infinity, that is, after multiple iterations of the intelligent algorithm, the difference between the second performance parameter output by the intelligent algorithm with updated parameters and the first performance parameter corresponding to the multiple instruction sequences input to the intelligent algorithm is less than the threshold set, so that the converged intelligent algorithm can output valid performance parameters. The training process can use a variety of algorithm acceleration hardware or software platforms, such as CPU multi-threaded acceleration, GPU acceleration and dedicated hardware accelerator acceleration. In multiple tasks in the CPU, data does not interact and can be executed in parallel. Therefore, CPU multi-threading can be used to process tasks in parallel, accelerating the processing speed of the intelligent algorithm. GPU is a large-scale parallel computing architecture composed of thousands of smaller and more efficient cores (designed for processing multiple tasks simultaneously). Therefore, GPU can also be used to perform parallel computing to accelerate the processing speed of the intelligent algorithm. The dedicated hardware accelerator replaces the software algorithm by adding hardware modules to fully utilize the inherent fast characteristics of the hardware, thereby improving the processing speed of the intelligent algorithm.

[0063] Optionally, the training model according to the mapping relationship includes: inputting the multiple instruction sequences into the training model and outputting at least one second performance parameter; obtaining the at least one first performance parameter corresponding to the multiple instruction sequences based on the mapping relationship; and updating the parameters of the training model according to the at least one first performance parameter and the at least one second performance parameter.

[0064] Specifically, multiple instruction sequences from the training set constructed above are input into an intelligent algorithm to obtain at least one second performance parameter corresponding to the multiple instruction sequences. This at least one second performance parameter is then compared with at least one first performance parameter bound to the multiple instruction sequences to construct a loss function for the intelligent algorithm. The parameters of the intelligent algorithm are updated based on the loss function, thereby obtaining a target training model.

[0065] During model training, because we want the model's output to be as close as possible to the desired predicted value, we can compare the current model's predicted value with the desired target value and then update the intelligent algorithm's weight vector based on the difference between the two. For example, if the model's predicted value is too high, the weight vector is adjusted to make it predict a lower value. This adjustment is continued until the model can predict the desired target value or a value very close to the desired target value. The loss function is an important equation used to measure the difference between the predicted value and the target value. For example, a higher loss function output value (loss) indicates a greater difference, so model training becomes a process of minimizing this loss as much as possible. Ultimately, the parameters corresponding to the minimum loss function are determined as the parameters of the training model.

[0066] Exemplarily, multiple instruction sequences are input into an intelligent algorithm. If the multiple instruction sequences are all instruction sequences for the same operation or the same calculation, a first performance parameter may be obtained. For example, the multiple instruction sequences are convolution instructions in a convolutional neural network. When each instruction sequence is input into the convolutional neural network, the first performance parameter obtained is the same. Therefore, the multiple instruction sequences correspond to one first performance parameter. If the multiple instruction sequences are used to perform different operations or different calculations, multiple first performance parameters may be obtained. S230: Determine the target performance parameter corresponding to the target instruction sequence according to the target training model.

[0067] In a specific implementation, after the target training model is obtained through training, the hardware performance parameters corresponding to any instruction sequence can be obtained based on the trained intelligent algorithm.

[0068] For example, when calculating the target instruction sequence through the target training model, a variety of algorithm acceleration hardware or software platforms can be used, such as CPU multi-threaded acceleration, GPU acceleration, and dedicated hardware accelerator acceleration, thereby reducing the execution time of the intelligent algorithm and obtaining the performance parameters of the hardware more efficiently.

[0069] The following describes the method of the embodiment of the present application in detail, taking the target training model as LSTM as an example. LSTM is a deep neural network that solves long-term dependency problems and is a deep learning architecture. A deep learning architecture refers to multiple levels of learning at different levels of abstraction through machine learning algorithms. As a deep learning architecture, LSTM is suitable for processing and predicting tasks with long intervals and delays in time series.

[0070] like Figure 5 As shown, Figure 5A flow chart of another method for determining hardware performance provided in an embodiment of the present application. The input of LSTM 500 is a sequence of variable-length instructions, and the output is a performance parameter. First, a training set is constructed using existing target hardware A510. The target hardware A510 can be a physical hardware object or a register transfer level code or gate-level netlist in the design phase. N instruction sequences 520 are used as input, where N is a positive integer and the format of the N instruction sequences is 512-bit binary code. Performance parameters 530 corresponding to the N instruction sequences are obtained through technical means such as simulation and hardware testing. The performance parameters 530 are bound to the N instruction sequences 520 to form a training set for LSTM 500. The obtained training set is then used to train LSTM 500 to obtain a trained LSTM 540. The training process can be accelerated using existing intelligent algorithm acceleration hardware or software platforms. The trained LSTM 540 can enter the actual use process. The new instruction sequence 550 is directly calculated by the trained LSTM 540 to obtain the performance parameters 560 of the new instruction sequence 550.

[0071] It can be seen that the method for determining hardware performance in an embodiment of the present application obtains multiple instruction sequences, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware; trains a training model according to the mapping relationship to obtain a target training model; and determines the target performance parameter corresponding to the target instruction sequence based on the target training model. The present application automatically determines the performance parameter corresponding to the instruction sequence by generating a target training model with equivalent performance to the given hardware, thereby efficiently obtaining the performance parameters of the hardware.

[0072] For example, when the method for determining hardware performance proposed in this application is applied to image recognition processing, a processor retrieves multiple instruction sequences for image recognition from a memory, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the image recognition hardware; a training model is trained according to the mapping relationship to obtain a target training model; and based on the target training model, a target performance parameter corresponding to the target instruction sequence for image recognition is determined. This application automatically determines the performance parameters corresponding to the instruction sequence for image recognition by generating a target training model with equivalent performance to a given piece of image recognition hardware, thereby efficiently obtaining the performance parameters of the image recognition hardware.

[0073] Furthermore, when the method for determining hardware performance proposed in this application is applied to deep learning, a processor retrieves multiple instruction sequences applied to deep learning from a memory, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the deep learning hardware; a training model is trained according to the mapping relationship to obtain a target training model; and based on the target training model, a target performance parameter corresponding to the target instruction sequence applied to deep learning is determined. This application automatically determines the performance parameters corresponding to the instruction sequence applied to deep learning by generating a target training model with equivalent performance to a given deep learning hardware, thereby efficiently obtaining the performance parameters of the image recognition hardware.

[0074] The above mainly introduces the solution of the embodiment of the present application from the perspective of the execution process of the method side. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and / or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0075] The embodiment of the present application can divide the functional units of the electronic device according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0076] See also Figure 6a , Figure 6a This is a block diagram of the functional units of an apparatus 600 for determining hardware performance provided in an embodiment of the present application, such as Figure 6a As shown, the device 600 for determining hardware performance includes an acquisition unit 610, a training unit 620, and a determination unit 630, wherein:

[0077] The acquisition unit 610 is configured to acquire a plurality of instruction sequences, wherein a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware;

[0078] The training unit 620 is used to train the training model according to the mapping relationship to obtain a target training model;

[0079] The determining unit 630 is configured to determine target performance parameters corresponding to a target instruction sequence based on the target training model.

[0080] As can be seen, an embodiment of the present application provides a device for determining hardware performance, wherein an acquisition unit acquires multiple instruction sequences, wherein a mapping relationship exists between the multiple instruction sequences and at least one first performance parameter of the hardware; a training unit trains a training model according to the mapping relationship to obtain a target training model; and a determination unit determines a target performance parameter corresponding to the target instruction sequence based on the target training model. The present application automatically determines the performance parameter corresponding to the instruction sequence by generating a target training model with equivalent performance to a given piece of hardware, thereby efficiently obtaining the performance parameters of the hardware.

[0081] Optionally, the at least one first performance parameter is a performance parameter obtained by respectively inputting the multiple instruction sequences into the target hardware; the training unit 620 is specifically configured to:

[0082] Input the multiple instruction sequences into the training model and output at least one second performance parameter; obtain the at least one first performance parameter corresponding to the multiple instruction sequences based on the mapping relationship; and update the parameters of the training model based on the at least one first performance parameter and the at least one second performance parameter.

[0083] Optional, such as Figure 6b , which is a block diagram of functional units of another apparatus 600 for determining hardware performance provided by an embodiment of the present application, the apparatus 600 further includes: a segmentation unit 640;

[0084] The segmentation unit 640 is used to compare the data length of the first instruction sequence with a preset length. If the data length of the first instruction sequence is greater than the preset length, the first instruction sequence is segmented into multiple sub-instruction sequences, wherein the first instruction sequence is any instruction sequence among the multiple instruction sequences and / or the target instruction sequence.

[0085] Optionally, in terms of dividing the first instruction sequence into a plurality of sub-instruction sequences, the dividing unit 640 is specifically configured to: divide the first instruction sequence into the plurality of sub-instruction sequences of equal length; or

[0086] The first instruction sequence is divided into the plurality of sub-instruction sequences based on a synchronization instruction in the first instruction sequence, wherein the synchronization instruction is used to instruct synchronization between hardware.

[0087] Optionally, in terms of dividing the first instruction sequence into the multiple sub-instruction sequences based on the synchronization instructions in the first instruction sequence, the dividing unit 640 is specifically used to: search for the synchronization instructions in the first instruction sequence; and divide the first instruction sequence into the multiple sub-instruction sequences with each of the synchronization instructions as a dividing point.

[0088] Optionally, the device 600 further includes a conversion unit 650, wherein:

[0089] In the case where the first instruction sequence is a signal group, wherein the signal group includes a signal identifier and a first signal, and the signal identifier is used to indicate whether the first signal is valid at a current moment;

[0090] The conversion unit 650 is configured to convert the first signal into the instruction sequence when the signal identifier indicates that the first signal is valid at the current moment.

[0091] Optionally, the conversion unit 650 is specifically configured to: extract instruction information from the first signals of the plurality of signal groups; and convert the instruction information into a binary string having the same format as the instruction sequence.

[0092] It can be understood that the functions of each program module of the device for determining hardware performance in the embodiment of the present application can be specifically implemented according to the method in the above method embodiment. The specific implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0093] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments.

[0094] The present application also provides a computer program product comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package.

[0095] Figure 7 FIG. 7 is a structural diagram showing a combined processing device 700 according to an embodiment of the present disclosure. Figure 7 As shown in FIG, the combined processing device 700 includes a computing processing device 702, an interface device 704, other processing devices 706, and a storage device 708. According to different application scenarios, the computing processing device may include one or more computing devices 710, which may be configured to execute the combined processing device 702 in conjunction with the attached Figure 2 The described operation.

[0096] In various embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In exemplary applications, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing and processing device of the present disclosure may be considered to have a single-core structure or a homogeneous multi-core structure.

[0097] In exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through interface means, to jointly complete the operation specified by the user. Depending on the difference in implementation, the other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as central processing unit (Central Processing Unit, CPU), graphics processing unit (Graphics Processing Unit, GPU), artificial intelligence processor. These processors may include but are not limited to digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0098] In one or more embodiments, the other processing device may serve as an interface between the computing device disclosed herein (which may be embodied as an artificial intelligence computing device such as a neural network computing device) and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, and so on. In other embodiments, the other processing device may also collaborate with the computing device to jointly complete computing tasks.

[0099] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0100] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0101] In some embodiments, the present disclosure also discloses a neural network chip (e.g. Figure 8 In one implementation, the chip is a system on chip (SoC) and integrates one or more components such as Figure 7 The chip can be connected to the external interface device (such as Figure 8 The external interface device 806 shown in the figure is connected to other related components. The related components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) can be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 8 The board is described in detail.

[0102] Figure 8 FIG. 8 is a schematic diagram showing the structure of a board 800 according to an embodiment of the present disclosure. Figure 8As shown in , the board includes a storage device 804 for storing data, which includes one or more storage units 810. The storage device can be connected to the control device 808 and the chip 802 described above and transmit data by means of, for example, a bus. Furthermore, the board also includes an external interface device 806, which is configured for data relay or transfer function between the chip (or the chip in the chip packaging structure) and the external device 812 (such as a server or computer, etc.). For example, the data to be processed can be passed from the external device to the chip through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0103] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the working state of the chip.

[0104] According to the above combination Figure 7 and Figure 8 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0105] According to different application scenarios, the electronic devices or devices disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic devices or devices disclosed herein may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic devices or devices disclosed herein may also be used in cloud, edge, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0106] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teachings of the present disclosure, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present disclosure. In addition, depending on the different schemes, the description of some embodiments of the present disclosure also has different emphases. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0107] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this document divides them based on the consideration of logical functions, and there may be other ways of division in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0108] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solution described in the embodiments of this disclosure. In addition, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically separately.

[0109] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0110] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0111] The foregoing content can be better understood in accordance with the following terms:

[0112] Item A1. A method for determining hardware performance, comprising:

[0113] Acquire a plurality of instruction sequences, where a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware;

[0114] Training the training model according to the mapping relationship to obtain a target training model;

[0115] According to the target training model, target performance parameters corresponding to the target instruction sequence are determined.

[0116] A2. The method according to A1, wherein the at least one first performance parameter is a performance parameter obtained by inputting the plurality of instruction sequences into the target hardware;

[0117] The training model is trained according to the mapping relationship, comprising:

[0118] Inputting the plurality of instruction sequences into the training model and outputting at least one second performance parameter;

[0119] Acquire the at least one first performance parameter corresponding to the multiple instruction sequences according to the mapping relationship;

[0120] The parameters of the training model are updated according to the at least one first performance parameter and the at least one second performance parameter.

[0121] A3. The method according to A1 or A2, further comprising:

[0122] The data length of the first instruction sequence is compared with a preset length. If the data length of the first instruction sequence is greater than the preset length, the first instruction sequence is divided into multiple sub-instruction sequences, wherein the first instruction sequence is any instruction sequence among the multiple instruction sequences and / or the target instruction sequence.

[0123] A4. The method according to A3, wherein dividing the first instruction sequence into a plurality of sub-instruction sequences comprises:

[0124] Splitting the first instruction sequence into the multiple sub-instruction sequences of equal length; or,

[0125] The first instruction sequence is divided into the plurality of sub-instruction sequences based on a synchronization instruction in the first instruction sequence, wherein the synchronization instruction is used to instruct synchronization between hardware.

[0126] A5. The method according to A4, wherein the first instruction sequence is divided into the plurality of sub-instruction sequences based on the synchronization instruction in the first instruction sequence, comprising:

[0127] Searching for a synchronization instruction in the first instruction sequence;

[0128] The first instruction sequence is divided into the plurality of sub-instruction sequences using each of the synchronization instructions as a division point.

[0129] A6. The method according to A4 or A5, wherein the first instruction sequence is a signal group, wherein the signal group includes a signal identifier and a first signal, the signal identifier being used to indicate whether the first signal is valid at the current moment;

[0130] The method further includes: when the signal identifier indicates that the first signal is valid at the current moment, converting the first signal into the instruction sequence.

[0131] A7. The method according to A6, wherein converting the first signal into the instruction sequence comprises:

[0132] extracting instruction information from the first signal of the plurality of signal groups;

[0133] The instruction information is converted into a binary string having the same format as the instruction sequence.

[0134] A8. An apparatus for determining hardware performance, comprising:

[0135] an acquiring unit, configured to acquire a plurality of instruction sequences, wherein a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware;

[0136] A training unit, configured to train the training model according to the mapping relationship to obtain a target training model;

[0137] A determination unit is used to determine target performance parameters corresponding to a target instruction sequence based on the target training model.

[0138] A9. The apparatus according to A8, wherein the at least one first performance parameter is a performance parameter obtained by inputting the plurality of instruction sequences into target hardware; and the training unit is specifically configured to:

[0139] Input the multiple instruction sequences into the training model and output at least one second performance parameter; obtain the at least one first performance parameter corresponding to the multiple instruction sequences based on the mapping relationship; and update the parameters of the training model based on the at least one first performance parameter and the at least one second performance parameter.

[0140] A10. The apparatus according to A8 or A9, further comprising a segmentation unit;

[0141] The segmentation unit is used to compare the data length of the first instruction sequence with a preset length. If the data length of the first instruction sequence is greater than the preset length, the first instruction sequence is segmented into multiple sub-instruction sequences, wherein the first instruction sequence is any instruction sequence among the multiple instruction sequences and / or the target instruction sequence.

[0142] A11. The apparatus according to A10, wherein, in dividing the first instruction sequence into a plurality of sub-instruction sequences, the dividing unit is specifically configured to: divide the first instruction sequence into the plurality of sub-instruction sequences of equal length; or

[0143] The first instruction sequence is divided into the plurality of sub-instruction sequences based on a synchronization instruction in the first instruction sequence, wherein the synchronization instruction is used to instruct synchronization between hardware.

[0144] A12. According to the device described in A11, in terms of dividing the first instruction sequence into the multiple sub-instruction sequences based on the synchronization instructions in the first instruction sequence, the dividing unit is specifically used to: search for the synchronization instructions in the first instruction sequence; and divide the first instruction sequence into the multiple sub-instruction sequences with each of the synchronization instructions as a dividing point.

[0145] A13. The device according to A10-A12, further comprising a conversion unit, wherein

[0146] In the case where the first instruction sequence is a signal group, wherein the signal group includes a signal identifier and a first signal, and the signal identifier is used to indicate whether the first signal is valid at a current moment;

[0147] The conversion unit is configured to convert the first signal into the instruction sequence when the signal identifier indicates that the first signal is valid at a current moment.

[0148] A14. According to the device described in A13, the conversion unit is specifically used to: extract instruction information from the first signal of the multiple groups of signal groups; and convert the instruction information into a binary string with the same format as the instruction sequence.

[0149] B1. A neural network chip comprising a chip for executing a method as described in any one of clauses A1-A7.

[0150] C1. A computer-readable storage medium comprising a computer program for data exchange, wherein when the computer program is executed by a processor, the method according to any one of clauses A1 to A7 is implemented.

[0151] D1. An electronic device comprising:

[0152] processor;

[0153] a memory for storing processor-executable instructions;

[0154] The processor is configured to call instructions stored in the memory to execute the method as described in any one of clauses A1 to A7.

[0155] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that the above embodiments are provided by way of example only. Those skilled in the art may conceive of many changes, modifications, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for determining hardware performance, characterized in that, The method comprises: Acquire a plurality of instruction sequences, wherein a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware; the performance parameter comprises running time, energy consumption, latency, throughput, word length, or frequency; Training the training model according to the mapping relationship to obtain a target training model; Determining target performance parameters corresponding to a target instruction sequence according to the target training model; The at least one first performance parameter is a performance parameter obtained by respectively inputting the multiple instruction sequences into the target hardware; and the training model according to the mapping relationship includes: Inputting the plurality of instruction sequences into the training model and outputting at least one second performance parameter; Acquire the at least one first performance parameter corresponding to the multiple instruction sequences according to the mapping relationship; The parameters of the training model are updated according to the at least one first performance parameter and the at least one second performance parameter.

2. The method according to claim 1, characterized in that The method further comprises: The data length of the first instruction sequence is compared with a preset length. If the data length of the first instruction sequence is greater than the preset length, the first instruction sequence is divided into multiple sub-instruction sequences, wherein the first instruction sequence is any instruction sequence among the multiple instruction sequences and / or the target instruction sequence.

3. The method according to claim 2, characterized in that The step of dividing the first instruction sequence into a plurality of sub-instruction sequences includes: Splitting the first instruction sequence into the multiple sub-instruction sequences of equal length; or, The first instruction sequence is divided into the plurality of sub-instruction sequences based on a synchronization instruction in the first instruction sequence, wherein the synchronization instruction is used to instruct synchronization between hardware.

4. The method according to claim 3, characterized in that The step of dividing the first instruction sequence into the plurality of sub-instruction sequences based on the synchronization instruction in the first instruction sequence includes: Searching for a synchronization instruction in the first instruction sequence; The first instruction sequence is divided into the plurality of sub-instruction sequences using each of the synchronization instructions as a division point.

5. The method according to any one of claims 2 to 4, characterized in that: In the case where the first instruction sequence is a signal group, wherein the signal group includes a signal identifier and a first signal, and the signal identifier is used to indicate whether the first signal is valid at a current moment; The method further includes: when the signal identifier indicates that the first signal is valid at the current moment, converting the first signal into the instruction sequence.

6. The method according to claim 5, characterized in that The converting the first signal into the instruction sequence includes: extracting instruction information from the first signal of the plurality of signal groups; The instruction information is converted into a binary string having the same format as the instruction sequence.

7. A device for determining hardware performance, characterized in that The device comprises: an acquisition unit, configured to acquire a plurality of instruction sequences, wherein a mapping relationship exists between the plurality of instruction sequences and at least one first performance parameter of the hardware; the performance parameter comprises a running time, energy consumption, latency, throughput, word length, or frequency; A training unit, configured to train the training model according to the mapping relationship to obtain a target training model; a determination unit, configured to determine a target performance parameter corresponding to a target instruction sequence based on the target training model; The at least one first performance parameter is a performance parameter obtained by inputting the multiple instruction sequences into the target hardware respectively; the training unit is specifically configured to: Input the multiple instruction sequences into the training model and output at least one second performance parameter; obtain the at least one first performance parameter corresponding to the multiple instruction sequences based on the mapping relationship; and update the parameters of the training model based on the at least one first performance parameter and the at least one second performance parameter.

8. A neural network chip, characterized in that: The neural network chip is used to execute the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program for data exchange, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

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