Memory module data buffer

Abstract

The present invention includes apparatus and methods related to a data buffer in a non-volatile dual in-line memory module (NVDIMM). An example apparatus may include: a data buffer that can be coupled to a host; a first memory device (e.g., volatile memory), wherein the first memory device is coupled to the data buffer via a first bus; a second memory device (e.g., non-volatile memory); and a controller, wherein the controller is coupled to the data buffer via a second bus, and wherein the controller is configured to transfer data from the first memory device to the second memory device via the data buffer and the second bus.

Description

[0001] Priority information

[0002] This application is a non-provisional application of U.S. Provisional Application No. 63 / 132,818, filed on December 31, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to memory devices, and more particularly, to apparatus and methods for data buffers in memory modules. Background Art

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0005] Memory is also used as both volatile and nonvolatile data storage devices in a wide range of electronic applications. Nonvolatile memory can be used, for example, in personal computers, portable memory sticks, digital cameras, cell phones, portable music players such as MP3 players and movie players, and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device.

[0006] The memory may be part of a memory module, such as a dual in-line memory module (DIMM), used in a computing device. The memory module may include volatile memory, such as DRAM, and / or non-volatile memory, such as flash memory or RRAM. DIMMs may be used as main memory in a computing system. Summary of the Invention BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a device in the form of a computing system including a memory system according to several embodiments of the present disclosure.

[0008] Figure 2is a block diagram of a device in the form of a dual in-line memory module (DIMM) according to several embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of a memory system including dual in-line memory modules (DIMMs) according to several embodiments of the present disclosure.

[0010] Figure 4 A flowchart illustrating an example data transfer in a memory process according to several embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0011] The present disclosure includes apparatus and methods related to a data buffer in a memory module. For example, the memory module may be a dual in-line memory module (DIMM) and / or a non-volatile DIMM (NVDIMM). An example apparatus may include: a data buffer that may be coupled to a host; a first memory device (e.g., a volatile memory), wherein the first memory device is coupled to the data buffer via a first bus; a second memory device (e.g., a non-volatile memory); and a controller, wherein the controller is coupled to the data buffer via a second bus, and wherein the controller is configured to transfer data from the first memory device to the second memory device via the data buffer and the second bus.

[0012] A memory system may include a dual in-line memory module (DIMM) having a plurality of memory devices. For example, the DIMM may be a non-volatile DIMM (NVDIMM) that includes a plurality of volatile memory devices and a plurality of non-volatile memory devices. The plurality of non-volatile memory devices may serve as backup storage for the volatile memory devices. For example, the non-volatile memory devices may be configured to store data from the volatile memory devices during a critical save operation. The critical save operation may save data from the volatile memory devices to the non-volatile memory devices in response to a power loss on the DIMM. After the DIMM is powered on, a recovery operation may save data from the non-volatile memory devices to the volatile memory devices.

[0013] In several embodiments, the NVDIMM may include multiple data buffers for data transfer between a host and several volatile memory devices and / or for data transfer between several volatile memory devices and several non-volatile memory devices. The data buffer may be or may include static random access memory (SRAM), SDRAM, and / or DRAM memory arrays. The data buffer may be coupled to the several volatile memory devices so that all DQ pins of the several volatile memory devices are coupled to the data buffer, so that the several volatile memory devices can have any type of input / output configuration (e.g., x4, x8, and / or x16, among others) and / or any number of ranks. The data buffer may be coupled to the controller via a sideband bus. The data buffer may receive data from the several volatile memory devices, and the data buffer may transmit the data serially to the controller on the sideband bus. The sideband bus can operate by serially transferring data at a speed that allows the volatile memory to operate at full speed (e.g., the buffer can transfer data on the sideband bus so that the volatile memory can operate at full speed without being slowed down by any latency associated with the buffer and / or non-volatile memory). Transferring data from the plurality of volatile memory devices to the plurality of non-volatile memory devices can be accomplished using the data buffer, so the plurality of volatile memory devices do not include DQ pins reserved for transferring data to the controller and / or the plurality of non-volatile memory devices. Furthermore, data can be transferred from the plurality of volatile memory devices to the plurality of non-volatile memory devices using the sideband bus coupled to the data buffer, which can reduce the number of signals required for data transfer when compared to transferring data on DQ pins of the plurality of volatile memory devices directly coupled to the controller. The sideband bus coupling the data buffer to the controller can transfer data in a single wiring layer and, for example, can transfer data in one or two lanes. Backup operations that transfer data from volatile memory devices to nonvolatile memory devices may include transferring data from volatile memory devices to a data buffer without the latency associated with transferring data from volatile memory to memory at slower access speeds.

[0014] The NVDIMM may receive a command from another device, such as a host, to transfer data and / or the NVDIMM may generate a command to transfer data via a controller on the NVDIMM. The command received from the other device may include a request to transfer data between the host and the plurality of volatile memory devices. The command to transfer data between the host and the plurality of volatile memory devices may be executed by transferring the data through a data buffer coupled to the host. The data buffer may include a multiplexer that selects a data bus coupled to the host for data transfer. The data buffer may be an active driver for the DQ / DQS I / O on the volatile memory, so that the data buffer does not affect bandwidth limitations on the host.

[0015] A command generated by a controller of an NVDIMM may include a request to transfer data between a plurality of volatile memory devices and a plurality of non-volatile memory devices. The command to transfer data between a host and the plurality of volatile memory devices may be executed by transferring the data through a data buffer coupled to the controller, the controller being coupled to the plurality of non-volatile memory devices. The data buffer may include a multiplexer that selects a data bus (e.g., a sideband bus) coupled to the controller for data transfer.

[0016] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which are shown by way of illustration how several embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designator "N" indicates that a number of the particular features so designated may be included in several embodiments of the present disclosure.

[0017] As used herein, "a number" of something may refer to one or more of such things. For example, "a number of memory devices" may refer to one or more of the memory devices. Additionally, designators such as "N" as used herein, particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated may be included with several embodiments of the present disclosure.

[0018] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure numbers, and the remaining digits identify the elements or components in the figures. Similar elements or components between different figures can be identified by using similar numerals. As will be appreciated, the elements shown in the various embodiments herein can be added, exchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, the proportions and relative scales of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

[0019] Figure 1 is a functional block diagram of a computing system 100 including a device in the form of a plurality of memory systems 104-1 ... 104-N according to one or more embodiments of the present disclosure. As used herein, "device" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. Figure 1 In the embodiment described in, the memory system 104-1...104-N may include one or more dual in-line memory modules (DIMMs) 110-1,...,110-X, 110-Y. The DIMMs 110-1,...,110-X, 110-Y may include volatile memory and / or non-volatile memory. In several embodiments, the memory system 104-1,...,104-N may include a multi-chip device. The multi-chip device may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module. Figures 1 to 4 The described example uses DIMMs as memory modules, but embodiments of the present disclosure can be used on any memory system that includes volatile and / or non-volatile memory. In Figure 1, memory system 104-1, coupled to a host via channel 103-1, can include DIMMs 110-1, ..., 110-X, where DIMMs 110-1, ..., 110-X are NVDIMMs. In this example, each DIMM 110-1, ..., 110-X, 110-Y includes a controller 114. Controller 114 can generate and / or receive commands from host 102 and control the execution of commands on the DIMMs. Furthermore, in several embodiments, the disclosed protocol can be implemented by a memory device (e.g., a DIMM) that does not have a controller, and the execution of commands using the disclosed protocol can be built into the memory device. Depending on the type of memory in the DIMM, the host 102 can use the disclosed protocol and / or a previous protocol to send commands to the DIMMs 110-1, ..., 110-X, 110-Y. For example, the host can use the disclosed protocol to communicate with NVDIMMs on the same channel (e.g., channel 103-1) and can use a previous protocol to communicate with DRAM DIMMs that are both located on the same memory system 104.

[0020] like Figure 1 As illustrated in FIG, host 102 may be coupled to memory systems 104-1...104-N. In several embodiments, each memory system 104-1...104-N may be coupled to host 102 via a channel (eg, channels 103-1,..., 103-N). Figure 11, memory system 104-1 is coupled to host 102 via channel 103-1, and memory system 104-N is coupled to host 102 via channel 103-N. Host 102 may be a laptop computer, a personal computer, a digital camera, a digital recording and playback device, a mobile phone, a PDA, a memory card reader, an interface hub, or other host system, and may include a memory access device (e.g., a processor). Those skilled in the art will understand that "processor" may refer to one or more processors, such as a parallel processing system, a plurality of coprocessors, and the like.

[0021] Host 102 includes a host controller 108 for communicating with memory systems 104-1...104-N. Host controller 108 can send commands to DIMMs 110-1,..., 110-X, 110-Y via channels 103-1...103-N. Host controller 108 can communicate with controllers 114 on DIMMs 110-1,..., 110-X, 110-Y and / or each of DIMMs 110-1,..., 110-X, 110-Y to read, write, and erase data, among other operations. A physical host interface can provide an interface for passing control, address, data, and other signals between memory systems 104-1...104-N and host 102 having a receiver compatible with the physical host interface. Signals may be communicated between 102 and DIMMs 110-1, ..., 110-X, 110-Y, for example, via channels 103-1 ... 103-N over several buses, such as a data bus and / or an address bus.

[0022] The host controller 108 and / or controller 114 on the DIMM may include control circuitry, such as hardware, firmware, and / or software. In one or more embodiments, the host controller 108 and / or controller 114 may be an application-specific integrated circuit (ASIC) and / or a field-programmable gate array (FPGA) coupled to a printed circuit board containing the physical interface. In addition, the controller 114 of each DIMM 110-1, ..., 110-X, 110-Y may include a buffer 106 and registers 107 of volatile and / or non-volatile memory. The buffer 106 may be used to cache data used during the execution of commands.

[0023] DIMMs 110-1, ..., 110-X, 110-Y can provide main memory for a memory system or can be used as additional memory or storage devices in the overall memory system. Each DIMM 110-1, ..., 110-X, 110-Y can include one or more arrays of memory cells on a memory die, such as volatile and / or non-volatile memory cells. For example, the arrays can be flash arrays having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

[0024] Figure 1 Embodiments of the present disclosure may include additional circuitry not described to avoid obscuring the embodiments of the present disclosure. For example, memory systems 104-1...104-N may include address circuitry to latch address signals provided on I / O connections by I / O circuitry. The address signals may be received and decoded by row and column decoders to access DIMMs 110-1,..., 110-X, 110-Y. One of ordinary skill in the art will appreciate that the number of address input connections may depend on the density and architecture of DIMMs 110-1,..., 110-X, 110-Y.

[0025] Figure 2 FIG2 is a block diagram of a device in the form of a dual in-line memory module (DIMM) 210 according to several embodiments of the present disclosure. Figure 2In the embodiment of the present invention, DIMM 210 may include a controller 214. Controller 214 may include memory, such as SRAM memory, which may be a buffer 206 and / or a plurality of registers 207. DIMM 210 includes memory devices 220-1 and 220-2 coupled to the controller via buses 246-1 and 246-2, respectively. DIMM 210 includes buffers 232-1 and 232-2 coupled to controller 214 via buses 242-1 and 242-2, respectively. DIMM 210 includes memory devices 230-1 and 230-2 coupled to buffers 232-1 and 232-2 via buses 244-1 and 244-2, respectively. Memory devices 230-1 and 230-2 may be volatile memory. Memory devices 220-1 and 220-2 may be non-volatile memory devices that may serve as backup storage for memory devices 230-1 and 230-2. Memory devices 220-1, 220-2, 230-1, and 230-2, and buffers 232-1 and 232-2 include control circuitry 222 (e.g., hardware, firmware, and / or software) that can be used to execute commands on memory devices 220-1, 220-2, 230-1, and 230-2, and buffers 232-1 and 232-2. Control circuitry 222 may receive commands from controller 214. Control circuitry 222 may be configured to execute commands to read and / or write data from memory devices 220-1, 220-2, 230-1, and 230-2, and buffers 232-1 and 232-2.

[0026] Buffers 232-1 and 232-2 can be configured to transfer data between memory devices 230-1 and 230-2 and another device (not shown), such as a host. For example, buffers 232-1 and 232-2 can receive data from the host on a bus (not shown) and transfer the data to memory devices 230-1 and 230-1 via buses 244-1 and 244-2, respectively. Buffers 232-1 and 232-2 can include multiplexers 248-1 and 248-2 to select a bus (not shown) to transfer data between buffers 232-1 and 232-2 and another device (not shown). Buffers 232-1 and 232-2 can receive data from memory devices 230-1 and 230-1, respectively, via buses 244-1 and 244-2, and transfer the data to the host on the bus (not shown).

[0027] Buffers 232-1 and 232-2 may be configured to transfer data between memory devices 230-1 and 230-1 and memory devices 220-1 and 220-2. For example, buffers 232-1 and 232-2 may receive data from memory devices 230-1 and 230-1 via buses 244-1 and 244-2, respectively, and transfer the data to controller 214 via buses 242-1 and 242-2, respectively. Controller 214 may then transfer the data to memory devices 220-1 and 220-2 via buses 246-1 and 246-2, respectively. Buses 242-1 and 242-2 may be sideband buses configured to transfer data serially. The buses 242-1 and 242-2 can be operated by serially transferring data at a speed that allows the memory devices 230-1 and 230-2 to operate at full speed (e.g., the buffers can transfer data on the buses 242-1 and 242-2 so that the memory devices 230-1 and 230-2 can operate at full speed without being slowed down by any latency associated with the buffers 232-1 and 232-2, the controller 214, and / or the memory devices 220-1 and 220-2). The buffers 232-1 and 232-2 can include multiplexers 248-1 and 248-2 to select the buses 242-1 and 242-2 to transfer data between the buffers 232-1 and 232-2 and the controller 214 and / or the memory devices 220-1 and 220-2.

[0028] Buffers 232-1 and 232-2 can be configured to transfer data from a host and memory devices 220-1 and 220-2. For example, buffers 232-1 and 232-2 can receive data from a host (via a bus, not shown) and transfer the data to controller 214 via buses 242-1 and 242-2, respectively. Controller 214 can then transfer the data to memory devices 220-1 and 220-2 via buses 246-1 and 246-2, respectively. Buses 242-1 and 242-2 can be sideband buses configured to transfer data serially.

[0029] Figure 3 FIG is a block diagram of a memory system including a dual in-line memory module (DIMM) 310 according to several embodiments of the present disclosure. Figure 3 In FIG. 3 , DIMM 310 includes an edge connector 350 coupled to data buses 340-1, ..., 340-8 and a command / address bus 362. The host can connect to the DIMMs via several channels (e.g., Figure 1330-8). A host may couple DIMM 310 to a first channel (channels 103-1, ..., 103-N) of a DIMM 310 and an edge connector 350. For example, a host may couple DIMM 310 via a first channel including data buses 340-1, ..., 340-4 and a second channel including data buses 340-5 and 340-8. For example, the host may send commands on the first channel for execution on memory devices 330-1, ..., 330-4, and may send commands on the second channel for execution on memory devices 330-5, ..., 330-8. Controller 314 may receive commands from the host. Commands from the host may be sent to register clock driver (RCD) 360 via bus 362, and commands from RCD 360 may be sent to controller 314 via bus 364. Controller 314 can receive commands from RCD 360 and store data associated with the commands (e.g., command instructions and / or data to be read from and / or written to memory devices 320 and / or 330 during execution of the command) in buffer 306. Controller 314 can send a signal to RCD 360 on bus 364 indicating which of memory devices 330-1, ..., 330-8 will execute the command. Signals can be sent from RCD 360 on buses 366-1 and 366-2 to the memory devices 330-1, ..., 330-8 that will execute the command. For example, if the command transfers data between memory device 330-1 and the host, the signal can instruct multiplexer 348-1 to couple bus 340-1 to buffer 332-1. The command can be executed by transferring data between the host and buffer 332-1 on bus 340-1 and between buffer 332-1 and memory device 330-1 on bus 344-1. Memory devices 330-1, ..., 330-8 can send a signal (e.g., a command completion signal) to RCD 360 and controller 314 on buses 366-1 and 366-2, indicating that memory devices 330-1, ..., 330-8 have completed the execution of the command and are ready to receive additional commands. Once the command has been executed, controller 314 can send another command to RCD 360 for execution and / or send a status signal to the host, indicating that the command received from the host has been executed. Controller 314 can include non-volatile and / or volatile memory, such as SRAM memory, which can be buffer 306 and / or register 307 used during the execution of the command.

[0030] DIMM 310 can include a first number of memory devices 330-1, ..., 330-8. Memory devices 330-1, ..., 330-8 can be, for example, DRAM memory devices, as well as other types of volatile and / or non-volatile memory. Each of the memory devices 330-1, ..., 330-8 may be paired with a cache 332-1, ..., 332-8, wherein the memory device 330-1 is paired with the cache 332-1 via the bus 344-1, the memory device 330-2 is paired with the cache 332-2 via the bus 344-2, the memory device 330-3 is paired with the cache 332-3 via the bus 344-3, the memory device 330-4 is paired with the cache 332-4 via the bus 344-4, the memory device 330-5 is paired with the cache 332-5 via the bus 344-5, the memory device 330-6 is paired with the cache 332-6 via the bus 344-6, the memory device 330-7 is paired with the cache 332-7 via the bus 344-7, and the memory device 330-8 is paired with the cache 332-8 via the bus 344-8. The buffers 332 - 1 , . . . , 332 - 8 may be configured to buffer data transferred between the host and the memory devices 330 - 1 , . . . , 330 - 8 .

[0031] Memory devices 330-1, ..., 330-8 may be paired with buffers 332-1, ..., 332-8 for transferring data to a host and / or to memory devices 320-1, ..., 320-8. Buffers 332-1, ..., 332-8 may include multiplexers 348-1, ..., 348-2 that may select buses 340-1, ..., 340-8 when transferring data to / from the host, and / or may select buses 342-1, ..., 342-8 via controller 314 when transferring data to / from memory devices 320-1, ..., 320-8. Data buffers 332-1, ..., 332-8 may include SRAM, SDRAM, and / or DRAM arrays. The data buffers 332-1, ..., 332-8 can be coupled to the memory devices 330-1, ..., 330-8 such that all DQ pins of the memory devices 330-1, ..., 330-8 are coupled to the data buffers 332-1, ..., 332-8. Therefore, the memory devices 330-1, ..., 330-8 can have any type of input / output configuration (e.g., x4, x8, and / or x16, among others) and / or any number of ranks. Furthermore, because the buffers 332-1, ..., 332-8 use the sideband buses 342-1, ..., 342-8 for such transfers, the memory devices 330-1, ..., 330-8 do not include DQ pins dedicated for transferring data to the memory devices 320-1, ..., 320-8. The sideband buses 342-1, ..., 342-8 may operate by serially transferring data at a speed that allows the memory devices 330-1, ..., 330-8 to operate at full speed without being slowed down by any latency associated with the buffers 332-1, ..., 332-8, the controller 314 and / or the memory devices 320-1, ..., 320-8.

[0032] DIMM 310 may include a second number of memory devices 320-1, ..., 320-8. For example, memory devices 320-1, ..., 320-8 may be 3D XPoint memory devices, as well as other types of volatile and / or non-volatile memory. Memory devices 320-1, ..., 320-8 may be configured as backup storage devices for memory devices 330-1, ..., 330-8. The controller may be configured to transfer data from memory devices 330-1, ..., 330-8 to memory devices 320-1, ..., 320-8 periodically and / or as part of a power-down operation.

[0033] DIMM 310 may be configured to receive command / address information from a host controller (e.g., Figure 1The host executes commands sent from the host to the DIMMs 310 using data sent to the register clock driver (RCD) 360 and data on the data buses 340-1, ..., 340-8 by the host controller 108 in the DIMM 310. The commands from the host may include address information of the memory devices 330-1, ..., 330-8, where the host is requesting an operation on data at a specific location in the memory devices 330-1, ..., 330-8.

[0034] In several embodiments, memory devices 330-1, ..., 330-8 can be configured as caches. For example, a memory device can be configured as a cache for data stored in memory devices 320-1, ..., 320-8 and / or other memory devices coupled to the computing system. DIMM 310 can be configured to have a portion of memory devices 330-1, ..., 330-8 that is addressable by the host and a portion of memory devices 330-1, ..., 330-8 that is configured as a cache.

[0035] In several embodiments, commands may be received from the host and / or generated by the controller 314 to transfer data between the host and the memory devices 330-1, ..., 330-8, to transfer data between the host and the memory devices 320-1, ..., 320-8, and / or to transfer data between the memory devices 330-1, ..., 330-8 and the memory devices 320-1, ..., 320-8. Data may be transferred between the memory devices 330-1, ..., 332-8 and the memory devices 320-1, ..., 320-8 via the buffers 332-1, ..., 332-8, the sideband buses 342-1, ..., 342-8, the controller 314, and the buses 346-1 and 346-2. Data may be transferred between the host and the memory devices 320-1, ..., 320-8 via the data buses 340-1, ..., 340-8, the buffers 332-1, ..., 332-8, the sideband buses 342-1, ..., 342-8, the controller 314, and the buses 346-1 and 346-2.

[0036] A command may be generated by controller 314 to transfer data from memory devices 330-1, ..., 330-8 to memory devices 320-1, ..., 320-8. The command may be sent by the controller to register clock driver (RCD) 360 via bus 364, which indicates which of the memory devices 330-1, ..., 330-8 is to execute the command. A signal may be sent from RCD 360 on buses 366-1 and 366-2 to the memory device 330-1, ..., 330-8 that is to execute the command. For example, if the command is to send data from memory device 330-1 to memory device 320-1, the signal may instruct multiplexer 348-1 to couple bus 342-1 to buffer 332-1. The command may be executed by transferring data from memory device 330-1 to buffer 332-1 on bus 344-1, from buffer 332-1 to controller 314 on bus 342-1, and from controller 314 to memory device 320-1 via bus 346-1.

[0037] A command may be generated by controller 314 to transfer data from memory devices 320-1, ..., 320-8 to memory devices 330-1, ..., 330-8. The command may be sent by the controller to register clock driver (RCD) 360 via bus 364, which indicates which of the memory devices 330-1, ..., 330-8 will execute the command and receive data from the memory devices 320-1, ..., 320-8. A signal may be sent from RCD 360 on buses 366-1 and 366-2 to the memory device 330-1, ..., 330-8 that will execute the command. For example, if the command is transferring data from memory device 320-1 to memory device 330-1, the signal may instruct multiplexer 348-1 to couple bus 342-1 to buffer 332-1. The command may be executed by transferring data from the memory device 320-1 to the controller 314 on the bus 346-1, from the controller 314 to the buffer 332-1 on the bus 342-1, and from the buffer 332-1 to the memory device 330-1 on the bus 344-1.

[0038] Figure 4 1 is a flow chart illustrating an example data transfer in a memory process according to several embodiments of the present disclosure. Figure 4 The process described in may be performed by, for example, a memory system comprising, for example, Figure 3 NVDIMM of DIMM 310 shown in FIG.

[0039] At box 462, the method may include receiving a first command at a controller on a memory module from a host device, wherein the memory module includes a data buffer coupled to the first memory device via a first bus, a data buffer coupled to the host device via a second bus, and a data buffer coupled to the controller via a third bus, and wherein the first command includes an instruction to transfer data between the host and the first memory device.

[0040] At block 464, the method may include generating, by a controller of the memory module, a second command to transfer data from a first memory device to a second memory device on the memory module, wherein the second memory device is coupled to the controller.

[0041] At block 466 , the method may include executing the first command by transferring data between the host and the first memory device through the data buffer.

[0042] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of the various embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and non-restrictive manner. It will be apparent to those skilled in the art that combinations of the above embodiments and other embodiments not specifically described herein will be apparent after reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

[0043] In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This approach to disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure necessarily utilize more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A device for caching data, comprising: a data buffer capable of being coupled to a host; a first memory device coupled to the data buffer via a first bus; a second memory device; as well as a controller coupled to the data buffer via a second bus and configured to: causing a first data transfer from the first memory device to the second memory device via the data buffer and the second bus in response to receiving a first command from the host via a register clock driver (RCD), wherein the controller generates a second command to cause the first data transfer from the first memory device to the second memory device in response to receiving the first command from the host, wherein the controller sends the second command to the first memory device via the RCD, and wherein the controller is configured to cause a second data transfer from the host to the second memory device via the data buffer and the second bus, wherein the second bus coupling the data buffer to the controller is a sideband bus that allows full speed operation of the first memory device when transferring data between the host and the first memory device; as well as causing a third data transfer from the first memory device to the host via the data buffer and the first bus in response to receiving a third command from the host via the RCD, wherein the controller generates a fourth command to transfer data between the first memory device and the host in response to receiving the third command from the host, and wherein the controller sends the fourth command to the first memory device, and wherein the sideband bus is configured to transfer data associated with the second data transfer while the first memory device transfers data associated with the third data transfer at full speed.

2. The apparatus of claim 1 , wherein all DQ pins on the first memory device are coupled to the data buffer via the first bus, and wherein the data buffer comprises a multiplexer configured to select a third bus to transfer data from the host to the first memory device.

3. The apparatus of claim 1, wherein the data buffer comprises a multiplexer configured to select the second bus to transfer data from the first memory device to the second memory device. 4 . The apparatus of claim 1 , wherein the apparatus is a non-volatile dual in-line memory module (NVDIMM), the first memory device is a volatile memory device, and the second memory device is a non-volatile memory device.

5. The apparatus of claim 1, wherein the second memory device is a non-volatile memory device configured to store data from the first memory device during a critical save operation.

6. A device for caching data, comprising: A memory module, wherein the memory module includes a first memory device coupled to a data buffer via a first bus, the data buffer coupled to a controller via a second bus, and the memory module includes a second memory device coupled to the controller, wherein the memory module is coupled to a host, and wherein the memory module is configured to: receiving a first number of commands to transfer data between the first memory device and the host via the data buffer, wherein the first number of commands are received by the controller from the host via a register clock driver (RCD), wherein the controller generates a second number of commands to transfer data between the first memory device and the host in response to receiving the first number of commands from the host, wherein the controller sends the second number of commands to the first memory device via the RCD; receiving a third number of commands to transfer data between the first memory device and the second memory device via the data buffer, wherein the data buffer is coupled to the controller via the second bus, the second bus being a sideband bus configured for serialized data transfer that enables full speed operation of the first memory device when transferring data between the host and the first memory device; as well as A fourth number of commands is received to transfer data between the host and the second memory device via the data buffer and the second bus.

7. The apparatus of claim 6, wherein the data buffer is coupled to the host via a third bus.

8. The apparatus of claim 6, wherein all DQ pins of the first memory device are coupled to the data buffer via the first bus.

9. A device for caching data, comprising: Register clock driver RCD; a controller coupled to the RCD and configured to receive commands from a host via the RCD; a first number of memory devices coupled to the controller via the RCD and via a number of data buffers; as well as a second number of memory devices coupled to the controller, wherein the plurality of data buffers each include a multiplexer configured to select a first bus for transferring data between the plurality of data buffers and the host, and to select a second bus for transferring data between the plurality of data buffers and the controller, wherein the controller is configured to receive a first command from the host via the RCD to transfer data between the host and the first number of memory devices, wherein in response to receiving the first command from the host the controller generates a second command to cause data transfer between the host and the first number of memory devices, and wherein the second command is sent from the controller to the first number of memory devices via the RCD and is executed by transferring data between the host and the first number of memory devices via the plurality of data buffers, and wherein the second bus coupling the plurality of data buffers to the controller is a sideband bus configured for serialized data transfer that allows full-speed operation of the first number of memory devices when transferring data between the host and the first number of memory devices.

10. The apparatus of claim 9, wherein the controller is configured to send a third command to the first number of memory devices via the RCD to transfer data between the first number of memory devices and the second number of memory devices.

11. The apparatus of claim 10, wherein the third command is performed by transferring data between the first number of memory devices and the second number of memory devices through the number of data buffers.

12. The apparatus of claim 10, wherein the third command is executed by transferring data from the first number of memory devices to the number of data buffers, from the number of data buffers to the controller on the second bus, and from the controller to the second number of memory devices.

13. The apparatus of claim 9, wherein the first bus is a data bus coupled to the host.

14. A method for caching data, comprising: receiving, at a controller on a memory module, a first command from a host device via a register clock driver (RCD), wherein the memory module includes a data buffer coupled to a first memory device via a first bus, the data buffer coupled to the host device via a second bus, and the data buffer coupled to the controller via a third bus, and wherein the first command includes an instruction to transfer data between the host and the first memory device; generating, by the controller of the memory module, a second command to transfer the data between the host and the first memory device in response to receiving the first command; generating, by the controller of the memory module, a third command to transfer the data from the first memory device to a second memory device on the memory module, wherein the second memory device is coupled to the controller; sending the second command and the third command to the first memory device via the RCD; executing the second command by transferring the data between the host and the first memory device via the data buffer; executing the third command by transferring the data from the first memory device to the data buffer, transferring the data from the data buffer to the controller via the third bus, and transferring the data from the controller to the second memory device, wherein the third bus coupling the data buffer and the controller is a sideband bus configured for serialized data transfer, and the speed of the serialized data transfer allows full speed operation of the first memory device, the full speed operation allowing full speed operation of the first memory device when transferring data between the host and the first memory device; receiving, at the controller on the memory module, a fourth command from the host device via the RCD, wherein the fourth command includes an instruction to transfer additional data between the host and the second memory device; as well as The fourth command is executed by transferring the additional data between the host and the second memory device via the data buffer and the third bus.

15. The method of claim 14, wherein executing the third command comprises selecting the third bus via a multiplexer on the data buffer to transfer the data from the data buffer to the controller.

16. The method of claim 14, wherein all DQ pins on the first memory device are coupled to the data buffer via the first bus.

17. The method of claim 14, wherein executing the second command comprises selecting the first bus via a multiplexer on the data buffer to transfer the data between the host and the data buffer.

18. The method of claim 14, further comprising executing the third command to back up the data transferred by the second command in response to completing execution of the second command.

Images