Data processing method based on multi-core processor and related product

Abstract

The disclosure discloses a data processing method based on a multi-core processor, a multi-core processor, a chip and a board. The multi-core processor can be included in a combined processing device as a computing device, and the combined processing device can further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices, respectively, for storing data of the computing device and the other processing devices. The scheme of the disclosure optimizes the sorting processing based on the multi-core processor, and improves the operation processing efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of data processing. More particularly, the present disclosure relates to a data processing method based on a multi-core processor, a multi-core processor, a chip and a board card. BACKGROUND

[0002] In the process of data processing, it is often necessary to select part of data meeting a condition from a large amount of data. For example, in a TopK operator in neural network operation, k(k is a positive integer) data with the largest (or the smallest or meeting other inequalities or other numerical constraints) values or together with indexes are needed to be selected and output. At present, data selection and output are mainly based on sorting algorithms such as heap sorting, quick sorting and bubble sorting, and sorting algorithms are usually implemented based on a single processing core, so the data processing efficiency is low.

[0003] With the development of hardware technology, modern intelligent processors mostly adopt a multi-core parallel framework. How to efficiently solve sorting problems such as TopK for large-scale data in the multi-core parallel framework, effectively reduce the memory access overhead of external storage circuits and maximize the parallelism of data are problems urgently needed to be solved in the field of data processing at present. SUMMARY

[0004] In order to at least solve one or more technical problems as mentioned above, the embodiments of the present disclosure provide a data processing method based on a multi-core processor, a multi-core processor, a chip and a board card.

[0005] In a first aspect, the embodiments of the present disclosure provide a data processing method based on a multi-core processor, the multi-core processor comprising a plurality of processing cores, the method comprising:

[0006] According to a configuration scheme, one or more processing cores are scheduled to perform sorting processing on to-be-processed data, wherein the configuration scheme indicates a number of processing cores to be used and a splitting manner of the to-be-processed data, and the sorting processing is used to filter out a specified number of values meeting a first predetermined condition from a specified sorting dimension of the to-be-processed data; and

[0007] According to the configuration scheme, the processing results returned by the scheduled one or more processing cores are selectively post-processed to obtain a final result.

[0008] In a second aspect, the embodiments of the present disclosure provide a multi-core processor comprising a plurality of processing cores, the multi-core processor being configured to perform data processing by the method of the first aspect.

[0009] In a third aspect, the embodiments of the present disclosure provide a chip comprising the multi-core processor of the second aspect.

[0010] In a fourth aspect, the embodiments of the present disclosure provide a board card comprising the chip of the foregoing third aspect.

[0011] Through the multi-core processor-based data processing method, the multi-core processor, the chip and the board card provided as above, the scheme of the embodiments of the present disclosure can reasonably and flexibly schedule available processing cores to jointly perform sorting processing, thereby matching the scale of data to be processed and the available processing core resources, fully utilizing the parallel processing capability of multiple processing cores, and effectively improving the data sorting processing speed. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example, and wherein like reference numerals refer to like elements throughout. In the drawings:

[0013] Figure 1 a structural diagram of a board card of the embodiments of the present disclosure is shown;

[0014] Figure 2 a structural diagram of a combined processing device of the embodiments of the present disclosure is shown;

[0015] Figure 3a an internal structure schematic diagram of a single processing core in a computing device of the embodiments of the present disclosure is shown;

[0016] Figure 3b a simplified internal structure schematic diagram of a multi-core computing device of the embodiments of the present disclosure is shown;

[0017] Figure 4 an exemplary logic flow diagram of selecting the Kth largest data in a data screening stage according to the embodiments of the present disclosure is shown;

[0018] Figure 5 an exemplary logic diagram of performing data screening according to a first screening configuration according to the embodiments of the present disclosure is shown;

[0019] Figure 6 an exemplary logic diagram of performing data screening according to a second screening configuration according to the embodiments of the present disclosure is shown;

[0020] Figure 7 an exemplary logic diagram of performing data screening according to a fourth screening configuration according to the embodiments of the present disclosure is shown; and

[0021] Figure 8 an exemplary flow diagram of a multi-core processor-based data processing method according to the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in the embodiments of the present disclosure in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0023] It should be understood that the terms "first", "second", "third", and "fourth" and the like that can occur in the claims, specification, and drawings of the present disclosure are used to distinguish different objects, rather than to describe a particular order. The terms "comprise" and "include" used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or sets thereof.

[0024] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure means any combination of one or more of the associated listed items and all possible combinations thereof, and includes these combinations.

[0025] As used in the specification and claims of the present disclosure, the term "if" can be interpreted as "when" or "upon" or "in response to a determination" or "in response to detecting" depending on the context.

[0026] Exemplary hardware environment

[0027] Figure 1 A structural schematic diagram of a board card 10 according to an embodiment of the present disclosure is shown. As shown, the board card 10 includes a chip 101, which is a system on chip (SoC) or a system on chip, integrating one or more combined processing devices, which is an artificial intelligence operation unit, to support various deep learning and machine learning algorithms, to meet the intelligent processing needs in complex scenarios in the fields of computer vision, speech, natural language processing, data mining, etc. In particular, deep learning technology is widely used in cloud intelligent fields. A significant feature of cloud intelligent applications is the large amount of input data, which has high requirements for the storage capacity and computing capacity of the platform. The board card 10 of this embodiment is suitable for cloud intelligent applications and has a large off-chip storage, on-chip storage, and powerful computing capacity. Figure 1 ​

[0028] The chip 101 is connected with an external device 103 through the external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card or a wifi interface, etc. The data to be processed can be transmitted by the external device 103 to the chip 101 through the external interface device 102. The calculation result of the chip 101 can be transmitted back to the external device 103 through the external interface device 102. According to different application scenarios, the external interface device 102 can have different interface forms, such as PCIe interface, etc.

[0029] The board card 10 further comprises a storage device 104 for storing data, which comprises one or more storage units 105. The storage device 104 is connected and transmits data with the control device 106 and the chip 101 through a bus. The control device 106 in the board card 10 is configured to regulate the state of the chip 101. For this purpose, in one application scenario, the control device 106 can comprise a single-chip microcomputer (MCU).

[0030] Figure 2 is a structural diagram of the combined processing device in the chip 101 of this embodiment. As shown in Figure 2 The combined processing device 20 comprises a computing device 201, an interface device 202, a processing device 203 and a storage device 204.

[0031] The computing device 201 is configured to perform user-specified operations, mainly implemented as a single-core intelligent processor or a multi-core intelligent processor, to perform the calculation of deep learning or machine learning, which can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0032] The interface device 202 is used to transmit data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 can obtain input data from the processing device 203 through the interface device 202 and write it into the storage device on the computing device 201. Further, the computing device 201 can obtain control instructions from the processing device 203 through the interface device 202 and write them into the control cache on the computing device 201. Alternatively or optionally, the interface device 202 can also read the data in the storage device of the computing device 201 and transmit it to the processing device 203.

[0033] The processing device 203, as a general processing device, performs basic control including but not limited to data carrying, starting and / or stopping of the computing device 201, etc. Depending on the implementation, the processing device 203 can be one or more types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), or other general purpose and / or special purpose processors, including but not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, etc., and the number thereof can be determined according to actual needs. As mentioned above, only in terms of the computing device 201 of the present disclosure, it can be considered as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0034] The storage device 204 is used to store data to be processed, which can be a DRAM, a DDR memory, usually with a size of 16G or more, for saving data of the computing device 201 and / or the processing device 203.

[0035] Figure 3a The internal structure of a single processing core in the computing device 201 is shown. The computing device 301 is used to process input data such as computer vision, speech, natural language, data mining, etc., and the computing device 301 includes three major modules: a control module 31, an operation module 32, and a storage module 33.

[0036] The control module 31 is used to coordinate and control the work of the operation module 32 and the storage module 33 to complete the task of deep learning, which includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 is used to obtain instructions from the processing device 203, and the instruction decode unit 312 decodes the obtained instructions and sends the decoding results as control information to the operation module 32 and the storage module 33.

[0037] The operation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support vector multiplication, addition, nonlinear transformation and other complex operations; the matrix operation unit 322 is responsible for the core calculation of the deep learning algorithm, i.e. matrix multiplication and convolution.

[0038] The storage module 33 is used to store or transfer related data, including a neuron storage unit (NRAM) 331, a weight storage unit (WRAM) 332, and a direct memory access module (DMA) 333. The NRAM 331 is used to store input neurons, output neurons and intermediate results after calculation; the WRAM 332 is used to store the convolution kernel of the deep learning network, i.e. the weight; the DMA 333 is connected to the DRAM 204 through the bus 34 and is responsible for data transfer between the computing device 301 and the DRAM 204.

[0039] Figure 3b A simplified schematic diagram of the internal structure of the multi-core computing device 201 is shown. The multi-core computing device can be abstracted by a hierarchical hardware model. As shown in the figure, the multi-core computing device can be abstracted into four levels, i.e. card level (Card) 350, chip level (Chip) 360, cluster level (Cluster) 370 and core level (Core) 380. In this embodiment of the disclosure, the data transmission of the storage unit and the computing unit part are mainly involved, so the relevant computing structure is briefly shown and introduced, and other parts are omitted.

[0040] At the card level, each card contains local DDR storage, and each processor chip serves as a computing and control unit.

[0041] At the chip level, each processor chip contains multiple multi-processors as computing units.

[0042] At the computing cluster level, each multi-processor includes multiple accelerator cores as control and computing units, and a shared storage SRAM as a storage unit.

[0043] At the processor core level, each accelerator core contains local storage and a local processing unit array. NFU refers to a neuron function unit (Neuron Function Unit) used for convolution calculation.

[0044] In the multi-core computing device, the storage model includes board card global memory, SRAM (shared memory) on Cluster, NRAM on Core, WRAM and registers, etc. In order to obtain better performance, data movement between the following storage levels of Card and the balance between memory access and calculation can be controlled explicitly. The SRAM is contained in the memory processing unit MPU (Memory Process Unit Core, referred to as MPU, or Mem Core). The Core refers to an intelligent processing core (Intelligent Process Unit Core, referred to as IPU Core or Core) in the multi-core computing device. One IPU Core contains NRAM, WRAM, NFU, etc. The Cluster refers to a processor cluster or computing cluster. Generally, the multi-core computing device contains several Clusters, and one Cluster contains one Mem Core and N IPU Cores.

[0045] Exemplary sorting processing logic

[0046] Based on the foregoing hardware environment of the multi-core processor, the embodiments of the disclosure provide a sorting processing scheme which can fully utilize the parallel-computing capability of the plurality of processing cores, and flexibly and reasonably schedule one or more available processing cores to realize sorting processing according to the size of the data to be processed.

[0047] The sorting processing of the embodiments of the disclosure refers to filtering out a specified number (for example, K) of values that meet a first predetermined condition (for example, maximum, minimum, or meet other inequalities or other numerical constraints) from the specified sorting dimension of the input data. Depending on the requirements of the sorting processing, the index position (index) of the corresponding value can also be returned. Further, the specified number of values filtered out can also be sorted in ascending order or descending order.

[0048] Therefore, the sorting processing can involve two stages: a data filtering stage and a full sorting stage. The data filtering stage is used to filter out K values that meet the first predetermined condition from the input data. The full sorting stage is used to sort all the K values filtered out, for example, in ascending order or descending order. Those skilled in the art can understand that, according to the specific sorting processing requirements and / or parameter settings, the sorting processing can only include the data filtering stage, only include the full sorting stage, or both. For example, when the sorted data is not required, only the data filtering stage is needed. For another example, when the sorting dimension size is equal to the value of K, the data filtering stage is not needed, and only the full sorting stage is needed, because all the data needs to be sorted.

[0049] For ease of description, in the following embodiments, the first predetermined condition is taken as an example of the maximum value, i.e., the sorting processing is to filter out the maximum K values from the sorting dimension of the input data. It can be understood that the method described herein is also suitable for the first predetermined condition being the minimum value or satisfying other inequalities or other numerical constraints.

[0050] In the data filtering stage, the processing logic can be divided into two parts: selecting the Kth largest data, also referred to as the GV threshold or threshold GV; and filtering the data greater than or equal to GV according to GV.

[0051] Figure 4 An exemplary logic flow diagram of selecting the Kth largest data in the data filtering stage according to an embodiment of the present disclosure is shown. Overall, GV is initialized first, and then it is determined whether the amount of data greater than or equal to GV in the currently read data reaches K. Then, GV is updated according to the number of filtered data. Considering that the Kth largest data can appear more than once, i.e., repeatedly, it is necessary to first determine the amount of data greater than or equal to GV, and then determine the amount of data greater than GV.

[0052] Specifically, as shown in the figure, in step 410, the GV threshold is first initialized to a small value. For example, GV can be initialized to the minimum value in the currently loaded and to-be-processed data on the processing core, or a value slightly smaller than the minimum value, so as to ensure that the data can be filtered, and the iteration times are not too many. At the same time of initialization, the upper bound and lower bound of the currently loaded and to-be-processed data can be determined, and the middle value is used for updating GV subsequently. The upper bound up can be the maximum value in the current data, the lower bound down can be set as GV, and the middle value middle is the average value of the upper bound and the lower bound.

[0053] Then, in step 420, it is determined whether the amount of data greater than or equal to GV in the currently loaded and to-be-processed data reaches K.

[0054] In some embodiments, considering the computing power of the hardware processing core, especially the vector processing power of the processing core, in the embodiments of the present disclosure, a vector instruction can be used in the judgment to screen the input data. The vector instruction can be implemented by a single instruction multiple data (SIMD) instruction set. More specifically, the number of data greater than or equal to GV can be counted by using a vector instruction (e.g., _bang_ge) that performs a bitwise comparison of elements in a vector. The _bang_ge instruction can perform a bitwise "greater than or equal to" comparison of elements of two equal-length vectors A and B, and return a vector C, in which the element value corresponding to the element position that satisfies the "greater than or equal to" condition is 1, and the rest is 0. In this embodiment, vector A is a vector composed of the numerical values of the currently loaded and to-be-processed data in the sorting dimension; and vector B is a vector composed of GV, each element value of which is equal to GV. Thus, by counting the number of elements with a value of "1" in vector C, the number of data greater than or equal to GV in the currently loaded and to-be-processed data can be counted.

[0055] If it is determined in step 420 that the number of data greater than or equal to GV has reached K, proceed to step 430, where it is further determined whether the number of data greater than GV has reached K.

[0056] Similarly, a vector instruction can also be used to screen the input data. For example, the number of data greater than GV can be counted by using the vector instruction _bang_gt at this time. The _bang_gt instruction can perform a bitwise "greater than" comparison of elements of two equal-length vectors A and B, and return a vector C, in which the element value corresponding to the element position that satisfies the "greater than" condition is 1, and the rest is 0. Thus, by counting the number of elements with a value of "1" in vector C, the number of data greater than GV in the currently loaded and to-be-processed data can be counted.

[0057] If the number of data greater than GV exceeds K, it indicates that the current GV is too small, and a larger GV should be selected. At this time, proceed to step 440, where GV is updated to select a larger GV.

[0058] Since the current GV is too small, the lower bound of the data needs to be adjusted when updating. Specifically, if the current lower bound down is not equal to the middle value middle, the lower bound down can be updated to the current middle value middle; otherwise, the lower bound down is updated to the current upper bound up. Then, the updated middle value is calculated based on the updated lower bound, and GV is assigned to update its value.

[0059] Based on the updated GV, return to step 420 to repeat the foregoing steps.

[0060] If it is determined in step 430 that the number of data greater than GV does not reach K, it means that the current GV is the Kth largest data. In this case, GV can be determined as the Kth largest data among the current loaded and to-be-processed data in step 450.

[0061] If it is determined in step 420 that the number of data greater than or equal to GV does not reach K, it means that the current GV is too large, and a smaller GV should be selected. In this case, proceed to step 460 to update GV to select a smaller GV.

[0062] Since the current GV is too large, the upper bound of data needs to be adjusted when updating. Specifically, if the current upper bound up is not equal to the middle value middle, the upper bound up can be updated to the current middle value middle; otherwise, the upper bound up is updated to the current lower bound down. Then, the updated middle value is calculated based on the updated upper bound, and GV is assigned to update its value.

[0063] Based on the updated GV, return to step 420 to repeat the foregoing steps.

[0064] Through repeated adjustment, the Kth largest data in the current processed data and the threshold GV can be found. After the GV threshold is determined, the data greater than or equal to GV can be directly filtered according to GV. In some embodiments, the vector instruction _bang_select can be used to filter data. The _bang_select instruction can select corresponding vector elements from the source input vector according to the mask vector mask. For example, the mask vector and the source input vector are equal in length, and the vector elements of the mask vector are composed of 0 / 1, and the _bang_select selects the vector elements corresponding to the position with a value of 1 in the mask vector from the source input vector. The mask vector mask can be determined according to the result obtained by the vector instruction _bang_gt or _bang_ge in the last iteration process (for example, the vector C in the foregoing).

[0065] In some embodiments, depending on the actual needs in the sorting process, the current processed data can be output according to the part greater than GV, the part equal to GV, and / or the part less than GV; or according to the part greater than or equal to GV and / or the part less than GV. After the data is filtered, the full sorting phase can be entered.

[0066] In the full sorting phase, the processing logic can also be divided into two parts: according to the quicksort algorithm, the to-be-sorted values (for example, the K values filtered) are divided until the size of the divided value block meets the predetermined condition; and for each value block, the bubble sort algorithm is used to sort the values in the value block.

[0067] In the quicksort algorithm, data blocks are continuously sorted according to... Data block size The data is divided by size until the sorting process is complete. However, considering the computing power of the hardware processing cores, especially their vector processing capabilities, in this disclosed embodiment, the splitting process can be stopped once the size of the resulting numerical blocks meets a predetermined condition, such as not exceeding the processing capacity of a single processing core in a single operation.

[0068] In one embodiment, the upper and lower boundaries of the values ​​to be sorted can be determined first, and the mean of the upper and lower boundaries can be calculated. Then, the data can be segmented based on this mean, for example, into an upper portion greater than or equal to the mean, and a lower portion less than the mean. Next, the upper and lower portions can be re-segmented using the aforementioned method until the size of the resulting data blocks is less than a threshold. This threshold can be determined, for example, based on the processing power of a single vector operation performed by a single processing core.

[0069] Afterward, bubble sort can be applied to each of the partitioned numerical blocks. More specifically, the bubble sort algorithm can be implemented using vector instructions for finding extreme elements in a vector (e.g., `_bang_max`, which finds the maximum value and its index), thus fully utilizing the processing core's computational power. After each `_bang_max` filter finds the maximum value, it can be written back to the minimum value to prevent it from being filtered again. This process is repeated multiple times until the values ​​within each numerical block are sorted, resulting in K sorted values ​​being output.

[0070] Exemplary configuration schemes

[0071] The core logic of the sorting process has been described above. In this disclosed embodiment, based on the above sorting process logic, the processing cores can be configured reasonably according to the scale of the data to be processed and the currently schedulable processing core resources to achieve sorting processing quickly and efficiently. The configuration scheme can indicate the number of processing cores to be used and the method of splitting the data to be processed.

[0072] Furthermore, given that the sorting process can be divided into a data filtering stage and a full sorting stage, the configuration scheme can be configured differently for each stage, thereby making more flexible use of the computing power of multi-core processors. Specifically, for the data filtering stage, the configuration scheme can specify the number of processing cores to be used and the method of splitting the data to be processed; while for the full sorting stage, the configuration scheme can specify the number of processing cores to be used and the method of splitting the K values ​​to be sorted. The configuration schemes for each stage will be described below.

[0073] Configuration of the data filtering stage

[0074] In the data screening phase, it is required to screen out K values satisfying the first predetermined condition on the specified sorting dimension from the to-be-processed data or input data, for example, the K largest values. Therefore, according to the scale of the input data, for example, the batch number, the size of the sorting dimension, and the schedulable processing core information, for example, the number of processing cores, the single processing capacity of the processing core, the on-chip available storage space of the processing core, and the like, there can be multiple screening configuration schemes for flexible configuration to maximize the use of the computing power of the multi-core processor.

[0075] The first screening configuration: in this configuration, one processing core processes one complete batch of data to screen out K values. It can be understood that if the data volume of a single batch is not large, for example, a single processing core can process it at a time, then only the data screening according to the sorting processing logic described above is required. When the data volume of a single batch is large and the processing core cannot process it at a time, it needs to be processed block by block until the entire batch of data is processed. In addition, it can be understood that in this configuration, the size of K cannot exceed the on-chip available storage space of the processing core.

[0076] Figure 5 An exemplary logic diagram for data screening according to the first screening configuration is shown. In this example, the data volume of a single batch is large, and the processing core needs to load data blocks in sequence for processing. The processing diagram in the initial state 510, the preparation phase 520, and the iteration processing phase 530 is shown in the figure.

[0077] As shown in the figure, in the initial state 510, a complete batch of input data 501 to be processed is stored on the external storage circuit, which exceeds the on-chip storage capacity 502 of the processing core. It is assumed that the on-chip can process a data volume of delta size.

[0078] In the preparation phase 520, first, data is loaded from the external storage circuit (step 521), and the loaded data volume is, for example, the data volume delta that can be processed on-chip. Then, the data screening logic described above can be applied to the data volume delta to select and store K values satisfying the first predetermined condition from the loaded data, and to determine the threshold GV corresponding to the first predetermined condition at present (step 522). Specifically, the Kth largest value in the current data, that is, the threshold GV, can be found according to the logic described above in combination with the first screening configuration. Figure 4 Then, according to the threshold GV, the current data is divided into two parts for storage: the first part greater than or equal to GV and the second part less than GV. It can be understood that the K values to be finally screened out will be stored in the first part.

[0079] Next, the iteration processing stage 530 can be entered to update the on-chip first portion (i.e. the largest K values) of data by traversing the unprocessed input data on the external storage circuit. In this stage, a portion of unprocessed data is loaded from the external storage circuit each time, and the on-chip first portion of data is updated by comparison until the entire batch of input data is traversed.

[0080] As shown, new unprocessed data is filtered from the unprocessed input data on the external storage circuit according to the threshold value GV determined last time (step 531). The new data must be greater than the threshold value GV, otherwise it is meaningless. The data amount of the new data is the data amount delta that can be processed on-chip minus the data amount of the first portion (i.e. the K values).

[0081] Next, the loaded new data is compared with the K values of the first portion of data stored on-chip last time to update and store the new K values (the first portion on-chip) and the threshold value GV (step 532). The specific implementation of this step can be the same as step 522 of the preparation stage 520, which is not repeated here.

[0082] Then, the above filtering (step 531) and updating (step 532) steps are repeated until the entire batch of input data is traversed. The data of the first portion on-chip, i.e. the last updated K values, is the output data of the data filtering stage.

[0083] Second filtering configuration: In this configuration, multiple processing cores jointly process a complete batch of data, and each processing core inputs a complete batch of data and filters a corresponding block of K values. In actual sorting processing, for example, the TopK operator in a neural network, which is a computational bottleneck operator, and a large part of the overhead is in the quicksort processing in full sorting. In the second filtering configuration, the filtering of K values is divided into multiple processing cores, so that the full sorting of K values in the subsequent full sorting stage can also be allocated to multiple processing cores. It can be understood that in this configuration, the on-chip storage space available to the processing core is required to be able to store a complete batch of data, and therefore is suitable for scenarios with small sorting dimensions.

[0084] Figure 6 An exemplary logic diagram of data filtering according to the second filtering configuration according to embodiments of the present disclosure is shown. In this example, the data amount of a single batch is small, and the processing core can read all the data to be processed at a time. The initial state 610 and the processing stage 620 on each processing core are shown in the figure.

[0085] As shown, in the initial state 610, the on-chip storage capacity 603 of the processing core exceeds the unprocessed input data 601 of a complete batch on the external storage circuit, and also exceeds the output data 602 (i.e. the K values).

[0086] In the processing stage 620 on each processing core, first, each processing core loads a complete batch of input data from the external storage circuit (step 621). Each processing core is also assigned a corresponding block of K values. Specifically, according to the size of K and the number of scheduled processing cores Ncore, K is split into Ncore blocks, which are assigned to the Ncore processing cores. The blocks are ordered. For example, assuming that the sorting task is to find the largest 100 numbers, K = 100, and the number of scheduled processing cores Ncore = 4, K can be split as follows:

[0087] The largest 25 numbers of the K values are assigned to processing core 1 (i.e., Top25) for screening, the next largest 25 numbers are assigned to processing core 2 (i.e., Top50-Top25) for screening, the next largest 25 numbers are assigned to processing core 3 (i.e., Top75-Top50) for screening, and the smallest 25 numbers are assigned to processing core 4 for screening (i.e., Top100-Top75).

[0088] Next, each processing core can screen the data of the corresponding block according to the upper and lower limits of the assigned block (step 622). The specific screening logic can still refer to the data screening logic described above, and only needs to be appropriately combined, which will not be described in detail here.

[0089] Thus, each processing core can output the data of a block of K values, which is spliced into all K values, i.e., the output data of the data screening stage. In this configuration, since the blocks are ordered, only the values in the blocks need to be fully sorted in the subsequent configuration, thereby sharing the overhead of the quicksort. This will be described in the description of the configuration of the full sorting stage.

[0090] The third screening configuration: this configuration can further include the preliminary screening configuration and the secondary screening configuration. In the preliminary screening configuration, multiple processing cores share the processing of a complete batch of data, and each processing core inputs a different data block in the same complete batch of data to screen K values that meet a first predetermined condition in the data block. In the secondary screening configuration, the K values are further screened from the data screened by the multiple processing cores using the first screening configuration or the second screening configuration described above.

[0091] When the batch number is not large, but the data volume of a single batch is large, a plurality of processing cores can be used to share the processing of a batch of data. For example, according to the number of schedulable processing cores Ncore, the to-be-processed data can be equally split into Ncore data blocks in a specified sorting dimension of the to-be-processed data, and the Ncore processing cores are assigned. Each processing core selects K values (for example, the largest K values) that meet the first predetermined condition from the assigned data block. It can be understood that when the data volume of the data block is not large, for example, a processing core can process it at a time, only the data selection according to the sorting processing logic described above is required. When the data volume of a single data block is also large, and a processing core cannot process it at a time, the processing can be performed part by part as described above Figure 5 , until the entire data block is processed. In addition, it can be understood that in this configuration, the size of K cannot exceed the on-chip available storage space of the processing core. After the preliminary screening stage, Ncore*K selected values are obtained.

[0092] In the secondary screening stage, the Ncore*K preliminary screened values are screened again to obtain K values. According to the size of the Ncore*K data volume, the first screening configuration or the second screening configuration described above can be used for secondary screening. For example, when Ncore*K is relatively small, for example, does not exceed the on-chip available storage space of a single processing core, the second screening configuration can be applied, that is, Ncore*K data is processed by a plurality of processing cores, and each processing core selects a corresponding block of K values from Ncore*K values, so as to facilitate the subsequent full sorting pressure to be shared by each processing core. For another example, when Ncore*K is relatively large, for example, exceeds the on-chip available storage space of a single processing core, the first screening configuration can be applied, that is, a single processing core sequentially processes Ncore*K data to screen K values.

[0093] The fourth screening configuration: in this configuration, a processing core processes a complete batch of data, and outputs K selected values in blocks, wherein the blocks are in order, and the values in the blocks are not sorted. When K is relatively large, for example, exceeds the on-chip available storage space of a single processing core, the sorting of K is preferably shared by a plurality of processing cores. However, when K is very large, the sorting dimension of the to-be-processed data must be greater than or equal to K, so the second screening configuration described above cannot be applied. Therefore, in the fourth screening configuration, a single processing core is used to serially process and output a corresponding block of K values, thereby splitting K, facilitating subsequent full sorting processing.

[0094] Figure 7An exemplary logic diagram of data filtering according to a fourth filtering configuration based on an embodiment of this disclosure is shown. In this example, the amount of data in a single batch is large, and the processing core cannot read all the data to be processed at once; data blocks need to be loaded sequentially for processing. The diagram illustrates the processing in the initial state 710, the preparation stage 720, and the iterative processing stage 730.

[0095] As shown in the figure, in the initial state 710, the input storage area of ​​the external storage circuit stores a complete batch of input data 701 to be processed, which exceeds the on-chip storage capacity 703 of the processing core. Furthermore, the amount of data 702 that needs to be filtered out (K values) is also large, and it is stored in the output storage area of ​​the external storage circuit, also exceeding the on-chip storage capacity 703 of the processing core. Let's assume that the chip can process a data volume of 2δ.

[0096] In the preparation phase 720, firstly, data is loaded from the input storage area of ​​the external storage circuit (step 721), and the amount of data loaded is, for example, the on-chip data capacity 2δ. Next, this loaded data capacity 2δ can be divided into three parts according to the median: a first part greater than the median, a second part equal to the median, and a third part less than the median (step 722). The method for determining the median can be found in the preceding text. Figure 4 The logic for selecting the Kth largest data point is described, except that here the Kth largest is replaced with the δth largest data point, i.e., the median. Next, the data volume 2δ, divided according to the median, can be stored in the output storage area of ​​the external storage circuit (step 723). Note that the output data volume stored in the output storage area at this time is 2δ, which is divided into two equal halves. One half of the δ data volume includes the portion greater than or equal to the median (the first δ), and the other half of the δ data volume includes the portion less than or equal to the median (the second δ).

[0097] Next, we can enter the iterative processing stage 730. The processing core processes 2δ data at a time, dividing and outputting data into blocks of size based on δ data, thereby dividing the K values ​​to be filtered into multiple δ-sized blocks. The δ-sized blocks are ordered, but the values ​​within the blocks are not sorted.

[0098] As shown in the figure, the processing core loads 2δ data points to be processed in the current iteration cycle (step 731). Half of this 2δ data point comes from unprocessed input data in the input storage area of ​​the external storage circuit, and the other half comes from the output data of the previous iteration cycle in the output storage area of ​​the external storage circuit. For example, at the beginning of the first iteration cycle, the output storage area stores the first δ part and the second δ part, and the data in the first δ part is greater than or equal to the data in the second δ part. The processing core can load the first δ part first.

[0099] Next, the loaded data of 2δ is divided into three parts according to the median: the first part greater than the median, the second part equal to the median, and the third part less than the median (step 732). The specific implementation of this step can be the same as step 722 of the preparation phase 720, which is not repeated here.

[0100] Next, the data amount of δ corresponding to the first predetermined condition in the divided three parts of data, for example, the data amount of the larger δ, is output to update the data amount of δ corresponding in the output storage area of the external storage circuit (step 733). That is, the data of the first δ part and the new data of the δ data amount are re-divided into two halves according to size, and the half data with a value greater than or equal to the median is used to update the first δ part in the output storage area.

[0101] The remaining half data continues to be compared, divided, and updated with other δ parts in the output storage area that have not been updated until the output data in the output storage area is traversed and updated in δ units. In the above example, after traversal, the output storage area increases by one δ of data, that is, from 2 δ parts to 3 δ parts (step 734). Thus, the processing of the new data of the δ data amount loaded from the input storage area in the current round is completed.

[0102] Then, the above loading (step 731), dividing (step 732), and updating (step 733) steps are repeated until the entire batch of input data is traversed. At this time, the K values to be screened on the output storage area will be arranged in multiple blocks in δ units, and the blocks are ordered. The data in the blocks has not been sorted. Since each block is ordered, subsequent sorting of the values in the block is only needed, thereby sharing the overhead of quicksort.

[0103] Configuration of the full sorting phase

[0104] In the full sorting phase, all K values selected in the data screening phase need to be sorted. Therefore, according to the size of K and the schedulable processing core information, such as the number of processing cores, the single processing capacity of the processing core, the on-chip available storage space of the processing core, etc., there can be multiple full sorting configuration schemes for flexible configuration to maximize the use of the computing power of the multi-core processor.

[0105] The first full sorting configuration: in this configuration, one processing core performs full sorting processing on K values. When the value of K is not too large, for example, does not exceed the on-chip available storage space of a single processing core, this configuration can be used. The specific full sorting logic can refer to the description in the foregoing, for example, including two phases of quicksort and bubble sort, which is not repeated here.

[0106] Second full sorting configuration: in this configuration, multiple processing cores jointly perform full sorting on K values, each processing core performs full sorting on values in a corresponding block of K values, and the blocks are ordered.

[0107] When K is large, for example, exceeds the on-chip available storage space of a single processing core, multiple processing cores can be utilized to share the full sorting processing. The prerequisite for sharing is that the K values filtered out in the previous data filtering stage are ordered by block, so that the full sorting task can be allocated by block. In the second filtering configuration and the fourth filtering configuration of the data filtering stage, K values are filtered out by block; and in the third filtering configuration, when the re-filtering configuration is the second filtering configuration, K values are also filtered out by block, thus it is easy to meet the prerequisite condition of the second full sorting configuration.

[0108] Although the K values are ordered by block, how to allocate each block on multiple processing cores can also have multiple schemes.

[0109] In one embodiment, each processing core processes full sorting of the data in the allocated block, and the amount of data allocated to each processing core is equal. In this embodiment, the K values are split by equal intervals, and the amount of data processed by each processing core is fixed. It can be understood that there can be duplicate values in the values. Therefore, in order to equally split the K values, the amount of data of the duplicate values needs to be known. In the data filtering logic described in the foregoing, a scheme is provided to output data according to a part greater than GV, a part equal to GV, and a part less than GV; and a scheme is also provided to output data according to a part greater than or equal to GV and a part less than GV. More specifically, for example, in the fourth filtering configuration of the data filtering stage, each time the processing core processes a data amount of 2δ, the data is divided into three parts according to the median: a first part greater than the median, a second part equal to the median, and a third part less than the median. Therefore, equal interval splitting of the K values can be supported. In this splitting case, although the amount of data allocated to each processing core is the same, due to the existence of duplicate data, the actual processing time spent can be different.

[0110] In another embodiment, each processing core processes full sorting of the data in the allocated block, and the amount of data allocated to each processing core is unequal, wherein the amount of data processed by the processing core allocated with duplicate values is greater than the amount of data processed by the processing core not allocated with duplicate values.

[0111] In this embodiment, the K values are non-uniformly split, and the amount of data processed by each processing core is not fixed. For example, in the second screening configuration of the data screening stage, each processing core screens data in a corresponding block of K values from a complete batch of data. When there are duplicate values, although the K values are evenly divided into blocks, the amount of data screened by each block is not necessarily even. For example, in the previous example, when K = 100 is divided into 4 blocks, the first block corresponds to the Top 25, the largest 25 values, but because there are duplicate values, 30 values can be screened; the second block corresponds to Top 50-Top 25, and because there are duplicate values, only 20 values can be screened. Although the amount of data allocated to each processing core is not the same, because of the presence of duplicate data, the actual processing time required can be roughly the same.

[0112] The above describes various configuration schemes for performing data sorting processing on a multi-core processor. Those skilled in the art can understand that these configuration schemes can be variously combined according to actual conditions to efficiently complete the data sorting task.

[0113] Figure 8 An exemplary flowchart of a multi-core processor-based data processing method according to embodiments of the present disclosure is shown.

[0114] As shown, in step 810, according to a configuration scheme, one or more processing cores on a multi-core processor are scheduled to perform sorting processing on the data to be processed. The configuration scheme here indicates the number of processing cores to be used and the manner in which the data to be processed is split, and the sorting processing is required to screen a specified number of values that meet a first predetermined condition from the specified sorting dimension of the data to be processed.

[0115] The configuration scheme can indicate the configuration of each stage (data screening stage, full sorting stage) included in the sorting processing. For example, the data screening stage can include a first screening configuration, a second screening configuration, a third screening configuration, or a fourth screening configuration, or a combination thereof; and the full sorting stage can include a first full sorting configuration or a second full sorting configuration.

[0116] In some embodiments, the configuration scheme can be determined according to the information of the currently schedulable processing cores in the multi-core processor (e.g., the number of processing cores, the processing capability of the processing cores, etc.) and the scale information of the data to be processed (e.g., the size of the sorting dimension, the number of batches, the size of K, etc.). Several specific examples of the configuration scheme will be given later.

[0117] Then, in step 820, the processing results returned by the scheduled one or more processing cores are selectively post-processed according to the configuration scheme to obtain the final results. For example, in the last stage of the sorting processing (i.e., the full sorting stage), if the first full sorting configuration is adopted, i.e., the full sorting is implemented by a single processing core, the result output by the single processing core is the final result without additional processing. If the second full sorting configuration is adopted in the full sorting stage, i.e., the full sorting is implemented by multiple processing cores, the results output by the multiple processing cores need to be spliced in order to obtain the final result; or the multiple processing cores output their respective results in order to a specified location, and the final result can also be directly obtained.

[0118] The multi-core processor is usually embedded in a host system as an accelerator or co-processor to support the execution of complete computing tasks. That is, the sorting processing task can be executed in a heterogeneous computing system. The heterogeneous computing system usually consists of a general-purpose processor and multiple domain-specific processors. The general-purpose processor is referred to as the host, which is used for complex control and scheduling. The main tasks of the host include device acquisition, data or parameter preparation, execution flow creation, task description, kernel launch, and output acquisition. The domain-specific processors are referred to as devices, which are used for large-scale parallel computing and domain-specific computing tasks, and both of them cooperate to complete the computing task. In the present disclosure, the multi-core processor can be used as a device.

[0119] When the present disclosure is implemented on a heterogeneous computing system, the host can split the sorting processing task and / or select different configuration schemes according to the configuration characteristics of different hardware and the size of the data to be processed, so as to maximize the use of the computing power of the multi-core processor. The multi-core processor can then complete the sorting processing task according to the specified configuration scheme.

[0120] The following describes several exemplary configuration schemes for executing sorting processing on a multi-core processor in combination with several specific embodiments.

[0121] Embodiment 1 : First configuration scheme SplitN

[0122] The first configuration scheme of embodiment 1 includes the first screening configuration of the data screening stage and the first full sorting configuration of the full sorting stage, i.e., each processing core processes a complete batch of data, including K-value data screening and K-value full sorting.

[0123] Embodiment 1 is suitable for the case that the batch number of data to be processed is relatively large, for example, a large number of batches of data are usually used for training in a training scenario. When the batch number of data to be processed is greater than a first threshold, at least the first configuration scheme can be used. The first threshold can be determined according to the number of schedulable processing cores, for example. For example, assuming that the number of schedulable processing cores is 16 and the batch number of data to be processed is 24, the threshold can be set to 14-16, and at least the first configuration scheme can be used. Specifically, the 24 batches can be split into 16+8 batches, for the first 16 batches, the first configuration scheme is used, that is, each processing core processes one batch; for the last 8 batches, the first configuration scheme can be used, at this time, part of the processing cores are not used, wasting computing power; or other configuration schemes can be used, as described later, to fully utilize the computing power of the processing cores.

[0124] Embodiment 2: Second configuration scheme SplitCK

[0125] The second configuration scheme of Embodiment 2 includes a second screening configuration of the data screening stage and a second full sorting configuration of the full sorting stage, that is, a plurality of processing cores jointly process one complete batch of data, wherein each processing core inputs one complete batch of data, each screening out a corresponding block from K values, and sorting the data screened out for each block.

[0126] Embodiment 2 is suitable for the case that the sorting dimension of data to be processed is relatively small, for example, no more than the on-chip storage capacity of a single processing core. This usually occurs in a matching scenario, for example, the sorting dimension is in the order of thousands to tens of thousands, for example, no more than 20,000. When the sorting dimension of data to be processed is less than a second threshold, the second configuration scheme can be used. The second threshold can be determined according to the on-chip storage capacity of the processing core, for example, 20,000.

[0127] Embodiment 3: Third configuration scheme SplitC

[0128] The third configuration scheme of Embodiment 3 includes a third screening configuration of the data screening stage, and the configuration of the full sorting stage is determined by the rescreening configuration in the third screening configuration. As described earlier, the third screening configuration includes a preliminary screening configuration and a rescreening configuration. In the preliminary screening configuration, a plurality of processing cores share the processing of one complete batch of data, each processing core inputs a different data block in the same complete batch of data, and screens out K values in the data block that meet a first predetermined condition. In the rescreening configuration, the first screening configuration or the second screening configuration is used to screen out K values from the data screened out by the plurality of processing cores in the preliminary screening configuration.

[0129] For example, if the amount of data after initial screening does not exceed the fourth threshold, such as not exceeding the on-chip available storage space of a single processing core, the rescreening configuration of the third screening configuration can be determined as the second screening configuration. That is, multiple processing cores are used to process Ncore*K data points together, and each processing core selects a block corresponding to K values ​​from the Ncore*K values, thereby facilitating the distribution of the pressure of the subsequent full sorting to each processing core. Correspondingly, the full sorting stage of the third configuration scheme is configured as the second full sorting configuration, that is, each processing core performs a full sort on the values ​​within the block corresponding to the K values.

[0130] For example, if the amount of data after initial screening exceeds the fourth threshold, such as exceeding the on-chip available storage space of a single processing core, the first screening configuration can be applied. That is, a single processing core is used to process Ncore*K data points sequentially, and K values ​​are selected from them. Correspondingly, the full sorting stage of the third configuration scheme is configured as the first full sorting configuration, that is, a single processing core is used to sort the K values.

[0131] Example 3 is suitable for situations where the sorting dimension of the data to be processed is large, but the number of batches is small. For example, the sorting dimension exceeds the on-chip storage capacity of a single processing core, but the number of batches does not exceed the number of schedulable processing cores. This situation typically occurs in inference scenarios, where there are few data batches, but the sorting dimension can be more than 20,000, or even tens of millions, without limitation.

[0132] Embodiment 4: Fourth configuration scheme SplitK

[0133] The fourth configuration scheme in Example 4 includes a fourth filtering configuration for the data filtering stage and a second full sorting configuration for the full sorting stage. That is, firstly, a single processing core processes a complete batch of data, outputting K filtered values ​​by blocks, where the blocks are ordered from one another, but the values ​​within each block are unsorted. Next, multiple processing cores jointly perform a full sorting process on the K values, with each core sorting the values ​​within a corresponding block of the K values. The first part of the computation process can be called the serial part, executed by a single processing core; the second part can be called the parallel part, executed by multiple processing cores.

[0134] Example 4 is suitable for cases where K is relatively large, such as K < 1e4, which removes the restriction on K.

[0135] The above describes and illustrates the sorting processing optimization scheme based on the multi-core processor according to the embodiments of the present disclosure in combination with multiple configuration schemes. Based on the teachings of the present disclosure, those skilled in the art can combine the aforementioned screening configuration and full sorting configuration in various manners according to specific hardware circuit configuration (such as the number of schedulable processing cores, the processing capacity of a single processing core, etc.) and the parameters of the sorting processing task (the size of the data to be processed, the size of K, etc.), thereby obtaining other configuration schemes, which all fall within the scope of the present disclosure, and thus will not be enumerated one by one here.

[0136] The embodiments of the present disclosure also provide a method for executing a sorting processing task by using a multi-core processor, which is split to execute the sorting processing task according to the indicated configuration scheme. Those skilled in the art can understand that the method steps for executing the sorting processing task correspond to the various logics described above in combination with the accompanying drawings, and thus the features described above are also applicable to the method steps, which will not be repeated here.

[0137] The embodiments of the present disclosure also provide a multi-core processor, which can be scheduled to execute data sorting processing according to the configuration scheme. The embodiments of the present disclosure also provide a chip, which can include the multi-core processor of any of the embodiments described above in combination with the accompanying drawings. Further, the present disclosure also provides a board card, which can include the aforementioned chip.

[0138] According to different application scenarios, the electronic device or apparatus of the present disclosure can include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a vehicle record device, a navigator, a sensor, a camera, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a visual terminal, an autonomous driving terminal, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, an oil smoke exhaust fan; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiograph. The electronic device or apparatus of the present disclosure can also be applied to the fields of Internet, Internet of Things, data center, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical treatment, etc. Further, the electronic device or apparatus of the present disclosure can also be used in cloud, edge, terminal, etc. application scenarios related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the electronic device or apparatus with high computing power according to the present disclosure can be applied to a cloud device (such as a cloud server), and the electronic device or apparatus with small power consumption can be applied to a terminal device and / or an edge device (such as a smart phone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or the edge device are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud device according to the hardware information of the terminal device and / or the edge device to simulate the hardware resources of the terminal device and / or the edge device, so as to complete the unified management, scheduling and collaborative work of end-cloud integration or cloud-edge integration.

[0139] It should be noted that for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art can understand that the schemes of the present disclosure are not limited by the order of the described actions. Therefore, those skilled in the art can understand that some steps can be executed in other orders or simultaneously according to the disclosure or teaching of the present disclosure. Further, those skilled in the art can understand that the described embodiments of the present disclosure can be regarded as optional embodiments, i.e. the actions or modules involved therein are not necessarily essential for the implementation of one or more schemes of the present disclosure. In addition, the description of some embodiments of the present disclosure also has different focuses according to the schemes. Therefore, those skilled in the art can understand that the parts not described in detail in one embodiment of the present disclosure can also refer to the relevant description of other embodiments.

[0140] In terms of specific implementation, based on the disclosure and teaching of the present disclosure, those skilled in the art can understand that the several embodiments disclosed by the present disclosure can also be implemented in other manners not disclosed herein. For example, in terms of the units described in the foregoing electronic device or apparatus embodiments, the units can be split into other forms in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions of the units or components can be selectively disabled. In terms of the connection relationship between the units or components, the connection discussed above can be direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling refers to the communication connection using an interface, and the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0141] In the present disclosure, the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units. The foregoing components or units can be located in the same place or distributed on multiple network units. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure can be integrated into one unit or physically exist separately.

[0142] In some other implementation scenarios, the above-mentioned integrated units can also be implemented in the form of hardware, i.e., specific hardware circuits, which can include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit can include but is not limited to physical devices, and the physical devices can include but are not limited to transistors or memristors, etc. In view of this, various devices described herein (e.g., computing devices or other processing devices) can be implemented by appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, ASICs, etc. Further, the aforementioned storage units or storage devices can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM, RAM, etc.

[0143] The above detailed description of the embodiments of the present disclosure is made with specific examples applied to the principles and implementation modes of the present disclosure. The above description of the embodiments is only used to help understand the method of the present disclosure and its core idea; at the same time, for those skilled in the art, according to the idea of the present disclosure, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present disclosure.

Claims

1. A data processing method based on a multi-core processor, the multi-core processor including multiple processing cores, the method comprising: According to the configuration scheme, one or more processing cores are scheduled to perform sorting processing on the data to be processed, wherein the configuration scheme indicates the number of processing cores to be used and the method of splitting the data to be processed, and the sorting processing is used to filter out the values ​​of K that satisfy the first predetermined condition from the specified sorting dimension of the data to be processed. According to the configuration scheme, the processing results returned by one or more scheduled processing cores are selectively post-processed to obtain the final result, where the final result is the result of sorting all K selected values; The sorting process includes a data filtering stage, which is used to filter out K values ​​that meet the first predetermined condition. The configuration scheme further indicates the configuration of the data filtering stage, including the number of processing cores used in the data filtering stage and the method of splitting the data to be processed. In this scenario, when the input data of a complete batch to be processed exceeds the on-chip available storage space of the processing core, and the amount of data of the K selected values ​​exceeds the on-chip available storage space of the processing core, and the on-chip can process a data amount of 2δ, the configuration of the data filtering stage includes a fourth filtering configuration, in which one processing core processes a complete batch of data and outputs the K selected values ​​by block, wherein the blocks are ordered between them, and the values ​​within the blocks are unsorted. In the fourth filtering configuration, a processing core outputs the K filtered values ​​from a complete batch of data, broken down into blocks, as follows: First, data is loaded from the input storage area of ​​the external storage circuit. The amount of data loaded is 2δ, which is the amount of data that can be processed on the chip. Next, for the loaded data volume 2δ, it is divided into three parts according to the median: the first part is greater than the median, the second part is equal to the median, and the third part is less than the median; The data volume 2δ after being divided according to the median is stored in the output storage area of ​​the external storage circuit; at this time, the data volume of the output data stored in the output storage area is 2δ, which is divided into two equal halves, one half of the δ data volume corresponds to the first predetermined condition, and the other half of the δ data volume does not correspond to the first predetermined condition. Next, the iterative processing phase begins, where the data volume, twice the block size (2δ), is iteratively processed on the processing core. Half of the 2δ data comes from unprocessed input data in the input storage area of ​​the external storage circuit, and the other half comes from the output data of the previous iteration in the output storage area of ​​the external storage circuit. The data in 2δ are divided into three parts based on the median: the first part is greater than the median, the second part is equal to the median, and the third part is less than the median. The amount of data corresponding to the first predetermined condition δ in the three parts of the output data is used to update the amount of data corresponding to δ in the output storage area of ​​the external storage circuit. The remaining half of the data continues to be compared, divided, and updated with the other δ parts in the output storage area that have not been updated, until all the output data in the output storage area has been traversed and updated in units of δ. After the traversal is complete, the output storage area will be increased by δ data.

2. The method according to claim 1, wherein, The configuration of the data filtering stage also includes any one or any combination of the following: In the first filtering configuration, one processing core processes a complete batch of data and filters out the K values; wherein, the first filtering configuration is applicable when the size of the K values ​​does not exceed the on-chip available storage space of the processing core; The second filtering configuration involves multiple processing cores processing a complete batch of data. Each processing core inputs a complete batch of data and filters out a block corresponding to K values. The second filtering configuration is suitable when the on-chip available storage space of the processing cores can store a complete batch of data. The third screening configuration includes an initial screening configuration and a secondary screening configuration, with a schedulable number of processing cores, Ncore. In the initial screening configuration, multiple processing cores share the processing of a complete batch of data. Each processing core inputs different data blocks from the same complete batch of data and filters out K values ​​from the data blocks that meet a first predetermined condition. The initial screening configuration is applicable when the size of the K values ​​does not exceed the on-chip available storage space of the processing core. In the secondary screening configuration, the first screening configuration or the second screening configuration is used to filter out the K values ​​from the data initially screened out by the multiple processing cores. The second screening configuration is applied when the size of Ncore*K values ​​does not exceed the on-chip available storage space of a single processing core, and the first screening configuration is applied when the size of Ncore*K values ​​exceeds the on-chip available storage space of a single processing core.

3. The method according to claim 2, wherein, In the first filtering configuration, a processing core filters out the K values ​​from a complete batch of data as follows: Data is loaded from an external storage circuit, from which K values ​​that satisfy the first predetermined condition are selected and stored, and the threshold GV of the first predetermined condition is determined. Based on the threshold GV, unprocessed new data is filtered out from the external storage circuit; The new data is compared with the previously stored K values ​​to update and store the new K values ​​and the threshold GV; as well as Repeat the filtering and updating steps until the data of a complete batch is traversed to obtain the last updated K values.

4. The method according to claim 2, wherein, In the second filtering configuration, multiple processing cores are scheduled for filtering processing as follows: The K is divided into N core blocks and allocated to N core processing cores; and Each processing core takes in a complete batch of data and filters out the data for the corresponding blocks based on the upper and lower limits of the allocated blocks.

5. The method according to claim 2, wherein, In the third screening configuration, multiple processing cores are scheduled for initial screening as follows: The data to be processed is split into N core data blocks along a specified sorting dimension and assigned to N core processing cores. as well as Each processing core selects K values ​​from the allocated data block that satisfy a first predetermined condition.

6. The method according to any one of claims 2-5, wherein, The sorting process also includes a full sorting stage, which is used to fully sort the selected K values. The configuration scheme further indicates the configuration of the full sorting stage, including the number of processing cores used in the full sorting stage and the splitting method of the K values.

7. The method according to claim 6, wherein, The configuration of the full sorting phase includes any of the following: The first full sort configuration involves one processing core performing a full sort on K values. This configuration is suitable when the amount of data for the K values ​​does not exceed the on-chip available storage space of a single processing core; or The second full sort configuration involves multiple processing cores jointly performing a full sort on K values. Each processing core performs a full sort on the values ​​within a corresponding block of the K values, and the blocks are ordered. The second full sort configuration is suitable when the amount of data for the K values ​​exceeds the on-chip available storage space of a single processing core.

8. The method according to claim 7, wherein, In the second full sort configuration, multiple processing cores are scheduled for full sort processing in any of the following ways: Each processing core performs a full sort of the data within its allocated block, and each processing core is allocated an equal amount of data. Each processing core processes the full sort of the data within its allocated block. The amount of data allocated to each processing core is not equal, with processing cores allocated with duplicate values ​​processing more data than processing cores not allocated with duplicate values.

9. The method according to claim 7, wherein, Each processing core performs a full sort on the values ​​to be sorted as follows: According to the quicksort algorithm, the values ​​to be sorted are divided into blocks until the size of the resulting blocks meets a predetermined condition; and For each block of values, the bubble sort algorithm is used to sort the values ​​within the block.

10. The method according to claim 9, wherein, The bubble sort algorithm includes: The bubble sort algorithm is implemented using vector instructions that search for extreme elements in a vector.

11. The method of claim 7, further comprising: The configuration scheme is determined based on the information of the currently schedulable processing cores in the multi-core processor and the scale of the data to be processed.

12. The method according to claim 11, wherein, Determining the configuration scheme includes: In response to the number of batches of the data to be processed being greater than a first threshold, it is determined that at least a first configuration scheme will be used, wherein the first configuration scheme includes the first filtering configuration and the first full sorting configuration.

13. The method according to claim 11, wherein, Determining the configuration scheme includes: In response to the sorting dimension of the data to be processed being less than a second threshold, a second configuration scheme is determined to be used, wherein the second configuration scheme includes the second filtering configuration and the second full sorting configuration.

14. The method according to claim 11, wherein, Determining the configuration scheme includes: In response to the sorting dimension of the data to be processed being greater than a third threshold, a third configuration scheme is determined to be used, wherein the third configuration scheme includes the third filtering configuration; and If the amount of data after initial screening does not exceed the fourth threshold, the rescreening configuration of the third screening configuration is determined to be the second screening configuration, and the full sorting stage configuration of the third configuration scheme is determined to be the second full sorting configuration; otherwise, the rescreening configuration of the third screening configuration is determined to be the first screening configuration, and the full sorting stage configuration of the third configuration scheme is determined to be the first full sorting configuration.

15. The method according to claim 11, wherein, Determining the configuration scheme includes: In response to K being greater than a fifth threshold, a fourth configuration scheme is determined to be used, wherein the fourth configuration scheme includes the fourth filtering configuration and the second full sorting configuration.

16. A multi-core processor comprising a plurality of processing cores, the multi-core processor being configured to perform data processing according to any one of claims 1-15.

17. A chip comprising the multi-core processor according to claim 16.

18. A circuit board comprising the chip according to claim 17.

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