Interface of an integrated circuit chip and method for arranging the interface

Abstract

The present invention provides an interface for an integrated circuit (IC) chip and a method of arranging the interface. The interface includes a plurality of contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and are divided into a transmission group and a reception group. The contact elements in the transmission group have a first contact element sequence, and the contact elements in the reception group have a second contact element sequence, and the first contact element sequence is the same as the second contact element sequence. When the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match each other.

Description

Technical Field

[0001] The present invention relates to the manufacture of semiconductor devices, and more particularly, to an interface of an integrated circuit (IC) chip and a method of arranging an interface of an IC chip. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functionality to adapt to various applications in the modern digital world. However, with the trend of semiconductor manufacturing, digital electronic devices are intended to be smaller and lighter, with improved functionality and higher performance. The semiconductor device can be packaged as a 2.5D semiconductor device, where several circuit chips can be integrated into a larger integrated circuit, and contact elements, inserts, or Redistribution Layers (RDLs) are used for connections between the chips.

[0003] Integrated Fan-Out (InFO) and chip-on-wafer-on-substrate (CoWoS) packaging technologies have been proposed to package multiple chips assembled side by side.

[0004] Regarding the entire electronic circuit, the main circuit can be manufactured based on 2.5D packaging technology. In addition, multiple application-specific integrated circuit (ASIC) chips and serializer / deserializer (SerDes) chips can be additionally placed on the main circuit and connected to each other through an interconnect interface involving a parallel bus.

[0005] The interfaces of two connected chips generally respectively include contact element patterns for connecting to each other. The contact element pattern of a chip includes multiple contact elements for connecting to the contact elements of another chip. How to arrange the contact element pattern of the chip to improve the connection quality remains a design problem. Summary of the Invention

[0006] The present invention provides an interface of an integrated circuit chip and a method of arranging an interface of an integrated circuit chip. The contact elements of the contact element pattern are configured to have a transmission group and a reception group. The contact elements of the transmission group and the reception group are arranged symmetrically. The chip can be easily placed on an insert or a redistribution layer.

[0007] In one embodiment, the present invention provides an interface for an integrated circuit (IC) chip, the interface including a plurality of contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmission group and a reception group. The contact elements in the transmission group have a first contact element sequence, and the contact elements in the reception group have a second contact element sequence, and the first contact element sequence is the same as the second contact element sequence. When the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match each other.

[0008] In one embodiment, the present invention provides a method for arranging an interface of an integrated circuit (IC) chip. The present invention includes configuring a plurality of contact elements to form a contact element pattern corresponding to a parallel bus, wherein the contact elements are arranged in an array of rows and columns and divided into a transmission group and a reception group. The contact elements in the transmission group are assigned a first contact element sequence, and the contact elements in the reception group are assigned a second contact element sequence. The first contact element sequence is the same as the second contact element sequence. When the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match each other.

[0009] To better understand the foregoing, several embodiments are described in detail below with reference to the accompanying drawings. Description of the Drawings

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the embodiments, are used to explain the principles of the present disclosure.

[0011] Figure 1 FIG. schematically shows a cross-sectional stacked structure of a 2.5D semiconductor device having an interface according to an embodiment of the present invention;

[0012] Figure 2 FIG. schematically shows an interface of one chip connected to a plurality of other chips through an interface according to an embodiment of the present invention;

[0013] Figure 3 FIG. schematically shows an interface for connection between a plurality of chips according to an embodiment of the present invention;

[0014] Figure 4 FIG. schematically shows a structure of a contact element pattern according to an embodiment of the present invention;

[0015] Figure 5 FIG. schematically shows a configuration of a contact element pattern in a transmission group and a reception group according to an embodiment of the present invention;

[0016] Figure 6 is a diagram schematically showing the connection between chips according to an embodiment of the present invention;

[0017] Figure 7 is a diagram schematically showing the connection relationship between the contact elements of two connected chips having a symmetric contact element pattern; and

[0018] Figure 8 is a diagram schematically showing the wiring effect between two connected chips having a symmetric contact element pattern.

[0019] Explanation of reference numerals in the drawings

[0020] 50: Platform

[0021] 100: Package substrate

[0022] 102: Through hole

[0023] 104: Bottom solder ball

[0024] 106: Top contact element

[0025] 110: Insert or redistribution layer

[0026] 112: Through-silicon via

[0027] 114: Interconnect wiring

[0028] 116: Contact element

[0029] 120: Serializer / deserializer chip

[0030] 130: Application-specific integrated circuit chip

[0031] 200: Integrated circuit chip

[0032] 200': Processor

[0033] 202, 210, 212: Chips

[0034] 204, 250: Interfaces

[0035] 300: Contact element pattern

[0036] 302: Transmission group

[0037] 304: Reception group

[0038] 306: Functional chip

[0039] 310: Trace path

[0040] 400: Axis Detailed implementation

[0041] The present invention relates to an interface of a 2.5D semiconductor device, where chips are placed on inserts or redistribution layers. The contact element pattern of the chips is configured to have a geometric symmetry relationship. The chips are more freely connected through the interface. The wiring lengths between the contact elements can also be set more evenly and shorter.

[0042] The following provides several embodiments for describing the present invention, but the present invention is not limited to the described embodiments.

[0043] Figure 1 FIG. schematically shows a cross-sectional stacked structure of a 2.5D semiconductor device with an interface according to an embodiment of the present invention. Refer to Figure 1 , in another application, a CoWoS or InFO platform 50 with an expected IC structure is formed based on 2.5D packaging technology. The CoWoS or InFO platform 50 may include a packaging substrate 100 with bottom solder balls 104 and top C4 contact elements 106. Through holes 102 can be used to connect from the bottom solder balls 104 to the top contact elements 106. In addition, an insert or redistribution layer 110 connected to the C4 contact elements 106 can be further formed on the substrate 100. The insert or redistribution layer 110 may also include through-silicon-vias (TSVs) 112, interconnect wirings 114, and contact elements 116. Here, depending on the manufacturing process adopted, the contact element 116 can be a through hole, a bump pad, or any suitable connection structure for terminal-to-terminal contact. The present invention does not limit the contact element 106 to a specific type.

[0044] In practical applications, additional chips, such as an ASIC chip 130 and a SerDes chip 120, can also be used to implement the CoWoS or InFO platform 50. The ASIC chip 130 and the SerDes chip 120 are connected through the wiring 114 and the interface. One ASIC chip 130 can be connected to multiple SerDes chips 120 for various peripheral communications.

[0045] Figure 2 FIG. schematically shows an interface where one chip is connected to multiple other chips through the interface according to an embodiment of the present invention. Refer to Figure 2 , an IC chip 200 (such as a processor or an ASIC chip) can be connected to multiple chips 202 through an interface 204. The interface 204 communicates involving a parallel bus between the chip 200 and the chip 202. The interface 204 may include contact elements in the wiring and the contact element pattern, so that the chip 200 can be connected to the chip 202.

[0046] Figure 3FIG. is a diagram schematically showing an interface for connection between multiple processor chips according to an embodiment of the present invention. Refer to Figure 3 , in another application, multiple processors 200' can be connected together to form a large processor with more powerful functions. In this case, these processors 200' are also connected through interface 204.

[0047] As described above, the 2.5D packaging process can be applied to stack various chips side by side without substantially further consuming the device area. However, in order to allow the chips to be more freely connected together, the contact elements in interface 204 need to be appropriately arranged in a compact manner and further symmetrically for receiving and transmitting signals. The communication between two chips 200 to chip 202 can be easily arranged in the peripheral area. Here, interface 204 can also refer to the Glink interface provided in the market.

[0048] Figure 4 FIG. is a diagram schematically showing the structure of a contact element pattern according to an embodiment of the present invention. Refer to Figure 4 , the total number of contact elements involved in the interface can be the number of signals that communicate in parallel for transmission and reception.

[0049] The total number of contact elements involved in the interface can be a relatively large number. Signals communicate in parallel between chips for transmission and reception. Depending on the data size in one bus, a 32-bit data size with an operating voltage and other functional signals is set as a tile, such as a circuit slice of contact element pattern 300. Contact element pattern 300 can be replicated in a certain number (e.g., 8) to accommodate the total data size of parallel communication. In an example, the data corresponds to 32 bits with a sequence of R_D0 to R_D31 and T_D0 to T_D31, on which T represents the contact element for transmission and R represents the contact element for reception. Additionally, contact element pattern 300 also includes multiple low voltage signals VSS and multiple high voltage VDDP. Additionally, various functional signals are included, including frame T / R_FR; clock T / R_DCKP / N; flow control T / R_FC[1:0]; DBI T / R_DBI[3:0]; parity check T / R_PAR; and path repair T / R_LR[1:0]. However, the contact elements for functional signals are not limited to this embodiment.

[0050] Table 1 is an example defining the contact elements of a transmission (T) group or a reception (R) group. The transmission group and the reception group have the same number of contact elements.

[0051] Table 1

[0052]

[0053] As mentioned, each contact element is specifically defined by its function in use so as to form a sequence of contact elements. The sequence of contact elements includes data contact elements and various functional contact elements. In an example, the contact element pattern includes 8 rows and 15 columns to form an array in a regular square or rectangular shape.

[0054] Figure 5 FIG. schematically shows the configuration of the contact element pattern in a transmission group and a reception group according to an embodiment of the present invention. Refer to Figure 5 , the contact elements are configured as an array having a plurality of rows and a plurality of columns, and the array is formed as a contact element pattern 300 corresponding to parallel buses for transmitting signals and receiving signals. The contact elements in the contact element pattern 300 are arranged in an array of rows and columns, and are divided into a transmission group 302 and a reception group 304. The contact elements of the transmission group � are labeled with "T_", and the contact elements of the reception group 304 are labeled with "R_".

[0055] In one embodiment, the number of rows N is odd or even. In one embodiment, 8 rows are taken as an example. The number of columns M can also be odd or even. In one embodiment, 15 columns are taken as an example. In order to have a compact layout, the central column can be divided into two parts for the transmission group 302 and the reception group 304. Generally, in one embodiment, N and M can be even or odd. In one embodiment, N is even and M is odd. In one embodiment, N is odd and M is even.

[0056] However, the present invention is not limited to the above embodiments. In one embodiment, dummy contact elements can also be used to separate the transmission group 302 and the reception group 304. In other words, the number of columns can be even, and dummy contact elements can be additionally added to clearly separate the transmission group 302 and the reception group 304. The present invention is not limited to the above embodiments.

[0057] The principle of allocating contact elements to the transmission group 302 and the reception group 304 is such that the transmission group 302 and the reception group 304 are symmetric. Ignoring the transmission label "T_" and the reception label "R_", the sequences of the contact elements of the transmission group 302 and the reception group 304 are the same. In other words, when the contact element pattern 300 is rotated 180° with the row direction as the rotation axis and the contact element pattern 300 is further rotated 180° with the column direction as the rotation axis, the sequences of the contact elements are the same.

[0058] In an example, taking the contact element R_DBI3 at the upper left corner of the reception group 304 as an example, after rotation, the contact element will match the contact element T_DBI3 of the transmission group 302. Therefore, the transmission contact elements in the sequence of the contact elements of one chip match the reception contact elements of another chip.

[0059] Figure 6 FIG. is a diagram schematically showing connections between chips according to an embodiment of the present invention. Refer to Figure 6 , the contact element pattern 300 is for one interface chip H, and the actual interface includes multiple interface chips H for one interface 250. In the example, N interfaces labeled as Glink0 to Glink N are used for description. The chip 210 may include multiple interfaces 250 for different communications with the chip 212. In one embodiment, one chip 210 and another chip 212 are taken as examples. The chip 210 includes multiple interfaces 250 of Glink0 to Glink N 250. The chip 212 also includes multiple interfaces 250 of Glink0 to Glink N. In the example, each of the interfaces 250 (Glink0 to Glink N) may include 8 interface chips H. Each interface chip H has a contact element pattern 300, in which the contact elements are symmetrically arranged. According to actual needs, additional functional chips 306 may be implemented at the center between the interface chips H. In the example, the functional chip 306 may be related to a phase locked loop (PLL) for verifying timing signals. In one embodiment, the present invention is not limited to the functional chip 306.

[0060] When the chip 212 is placed on the main chip during the packaging process, the chip 212 can be rotated 180° relative to the axis 400, and the contact element pattern of the chip 212 with symmetric arrangement can still be easily matched with the contact element pattern of the chip 210. In the example, the interface Glink0 of the chip 210 is matched with the interface GlinkN of the chip 212. Similarly, the interface Glink1 of the chip 210 is matched with the interface GlinkN-1 of the chip 212, etc. In other words, even if the chip 212 is rotated due to the requirements of the packaging process, the contact element pattern of each chip H of the chip 210 still allows the contact elements to be matched with the chip H of another chip 212.

[0061] In addition, the axis 400 can extend in the X-axis direction or the Y-axis direction. Additionally, according to the example of Figure 2 and Figure 3 , multiple axes 400 extending in both the X-axis direction and the Y-axis direction may be involved. However, the symmetric nature of the contact element pattern is still maintained.

[0062] Figure 7 FIG. is a diagram schematically showing the connection relationship between the contact elements of two connected chips with symmetric contact element patterns according to an embodiment of the present invention. Refer to Figure 7, taking a bonding pattern 300 of chips 210 and 212 as an example for further description, showing a trace path between contact elements having a contact element sequence as specified in the contact element pattern 300.

[0063] Due to the symmetric property, the contact element sequence of the contact element pattern 300 of chip 212 is the same as the contact element sequence of the contact element pattern 300 of chip 210 due to the rotation required in the packaging process. It is expected that the transmission group "T_" corresponds to the receiving group "R_". In the example, the contact element T_D0 of chip 210 is connected to the contact element R_D0 of chip 212, and the contact element R_D6 of chip 210 is connected to the contact element T_D6 of chip 212.

[0064] Figure 8 is a diagram schematically showing the wiring effect between two connected chips having symmetric contact element patterns according to an embodiment of the present invention. Refer to Figure 7 and Figure 8 , the trace path 310 between the contact elements of chips 210 and 212 can be kept substantially the same length. These features of the contact element pattern can have advantages. Due to the same connection length, the synchronous parallel bus from GLink TX arrives at GLink RX completely synchronously, with a minimum time difference between bits. This situation allows the GLink RX receiver to sample the parallel bus synchronously and achieve high-quality sampling at high frequencies.

[0065] As also referred to Figure 3 , chip 210 can be an ASIC chip 130, and chip 212 can be a SerDes chip 120. The connections in Figure 2 and Figure 3 can also be adopted in the example.

[0066] The present invention provides a contact element pattern with a symmetric arrangement.

[0067] In one embodiment, the present invention provides an interface for an integrated circuit (IC) chip, the interface including a plurality of contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmission group and a receiving group. The contact elements of the transmission group have a first contact element sequence, and the contact elements of the receiving group have a second contact element sequence. The first contact element sequence is the same as the second contact element sequence. When the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match.

[0068] In one embodiment, the present invention provides a method for arranging an interface of an integrated circuit (IC) chip. The present invention includes configuring a plurality of contact elements into a contact element pattern corresponding to a parallel bus, wherein the contact elements are arranged in an array of rows and columns and divided into a transmission group and a reception group. The contact elements of the transmission group are assigned a first contact element sequence, and the contact elements of the reception group are assigned a second contact element sequence. The first contact element sequence is the same as the second contact element sequence. When the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match each other.

[0069] In one embodiment, each of the transmission group and the reception group includes a set of data contact elements, a plurality of function contact elements, and voltage contact elements.

[0070] In one embodiment, the transmission group and the reception group are located on both sides of the contact element pattern in the row direction and joined together.

[0071] In one embodiment, the contact element pattern has N rows and M columns in a square shape or a rectangular shape. In one embodiment, N and M can be even or odd. In one embodiment, N is even and M is odd. In one embodiment, N is odd and M is even.

[0072] In one embodiment, the center column of the contact element pattern is equally divided into two parts for the transmission group and the reception part.

[0073] In one embodiment, N is equal to 8 and M is equal to 15 for transmitting / receiving data having a size of 32 bits.

[0074] In one embodiment, the interface includes a plurality of contact element patterns.

[0075] In one embodiment, the interface includes a plurality of interface chips, and each of the interface chips includes a contact element pattern.

[0076] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations provided they fall within the scope of the appended claims and their equivalents.

Claims

1. An interface of an integrated circuit chip, characterized in that, Comprising: A plurality of contact elements, formed as a contact element pattern corresponding to a parallel bus, wherein the contact elements are arranged in an array of rows and columns and divided into a transmission group and a reception group, wherein the contact elements of the transmission group have a first contact element sequence, and the contact elements of the reception group have a second contact element sequence, and the first contact element sequence is the same as the second contact element sequence, wherein when the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match, wherein the transmission group and the reception group are located on both sides of the contact element pattern in the row direction and joined together.

2. The interface of the integrated circuit chip according to claim 1, wherein Each of the transmission group and the reception group includes a set of data contact elements, a plurality of functional contact elements, and voltage contact elements.

3. The interface of the integrated circuit chip according to claim 1, wherein The contact element pattern has N rows and M columns in a square shape or a rectangular shape, wherein the N and the M are integers.

4. The interface of the integrated circuit chip according to claim 3, wherein The N and the M are even or odd.

5. The interface of the integrated circuit chip according to claim 3, characterized in that, The N is even and the M is odd, or the N is odd and the M is even.

6. The interface of the integrated circuit chip according to claim 5, characterized in that, The center column of the contact element pattern is equally divided into two parts for the transmission group and the reception group.

7. The interface of the integrated circuit chip according to claim 6, characterized in that, The N is equal to 8 and the M is equal to 15 for transmitting / receiving data having a size of 32 bits.

8. The interface of the integrated circuit chip according to claim 1, characterized in that, The interface includes a plurality of the contact element patterns.

9. The interface of the integrated circuit chip according to claim 1, characterized in that, The interface includes a plurality of interface chips, and each of the interface chips includes the contact element pattern.

10. A method for arranging an interface of an integrated circuit chip, characterized in that, Comprising: Configuring a plurality of contact elements to be formed as a contact element pattern corresponding to a parallel bus, wherein the contact elements are arranged in an array of rows and columns and divided into a transmission group and a reception group; And Assigning a first contact element sequence to the contact elements of the transmission group, and assigning a second contact element sequence to the contact elements of the reception group, wherein the first contact element sequence is the same as the second contact element sequence, wherein when the contact element pattern is geometrically rotated 180° with respect to the row direction and the column direction, the contact elements having the first contact element sequence and the second contact element sequence match, wherein the transmission group and the reception group are located on both sides of the contact element pattern in the row direction and joined together.

11. The method for arranging an interface of an integrated circuit chip according to claim 10, characterized in that, Each of the arranged transmission group and the reception group includes a set of data contact elements, a plurality of functional contact elements, and voltage contact elements.

12. The method for arranging an interface of an integrated circuit chip according to claim 10, characterized in that, The arranged contact element pattern has N rows and M columns in a square shape or a rectangular shape, wherein the N and the M are integers.

13. The method for arranging an interface of an integrated circuit chip according to claim 12, characterized in that, The N and the M are configured to be even or odd.

14. The method for arranging an interface of an integrated circuit chip according to claim 12, characterized in that, The N is configured to be even and the M is configured to be odd, or the N is configured to be odd and the M is configured to be even.

15. The method for arranging an interface of an integrated circuit chip according to claim 14, characterized in that, The center column of the contact element pattern is equally divided into two parts for the transmission group and the reception group.

16. The method for arranging an interface of an integrated circuit chip according to claim 15, characterized in that, The N is equal to 8 and the M is equal to 15 for transmitting / receiving data having a size of 32 bits.

17. The method for arranging an interface of an integrated circuit chip according to claim 10, characterized in that, The interface includes a plurality of the contact element patterns.

18. The method for arranging an interface of an integrated circuit chip according to claim 10, characterized in that, The interface includes a plurality of interface chips, and each of the interface chips includes the contact element pattern.

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