A BiCMOS device and a manufacturing method of a heterojunction bipolar transistor therein

Abstract

The present invention provides a BiCMOS and a manufacturing method of a heterojunction bipolar transistor therein. When forming a raised non-intrinsic base region of the heterojunction bipolar transistor, first, C and B are doped in-situ in epitaxial silicon, and a metal catalyst is doped simultaneously. Then, plasma treatment and laser annealing are performed on C to form a graphene region in the Si epitaxial layer. Since graphene has good mobility, the base resistance of the SiGe HBT can be reduced, and its radio frequency performance can be improved. The above method can form a graphene region in the non-intrinsic base region by performing plasma treatment and laser annealing on the doped C on the basis of the traditional BiCMOS device process. The whole process is easy to control and easy to integrate with the traditional BiCMOS device process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a BiCMOS device and a method for manufacturing a heterojunction bipolar transistor therein. Background Art

[0002] Traditional vertical bipolar transistor (VBT) technology is the main technology for high-speed computers. Its remarkable features are: 1) polysilicon emitter, which can scale the base width to less than 100 nm; 2) emitter-base self-alignment and deep and shallow trench isolation, which can reduce the device size and capacitance; 3) self-alignment of a more heavily doped collector region of the substrate to further improve the speed. Nowadays, heterojunction bipolar transistors (HBTs) using BiCMOS technology have been widely used in automotive radars, high-speed wireless and optical data links, and high-precision analog circuits. The structure of HBT is similar to that of conventional VBT, except that the base is replaced by SiGe doped with a small amount of C. Advanced CMOS technology and SiGe BiCMOS technology may meet the future 5G communication standard with frequencies up to 40 GHz, which is a strong competitor for high-data-rate wireless or fiber optic backhaul.

[0003] However, for the radio frequency performance of SiGe HBT, the base resistance of SiGe HBT is an important factor affecting its radio frequency performance. To obtain a SiGe HBT with high radio frequency performance, it is necessary to reduce the base resistance of SiGe HBT. Summary of the Invention

[0004] In view of the above need to reduce the base resistance of SiGe HBT, the purpose of the present invention is to provide a BiCMOS device and a method for manufacturing a heterojunction bipolar transistor therein. In the present invention, when forming a raised non-intrinsic base region, C and B are doped in-situ in epitaxial silicon, and at the same time a metal catalyst is doped, and then C is subjected to plasma treatment and laser annealing to form a graphene region in the Si epitaxial layer. Since graphene has good mobility, the base resistance of SiGe HBT can be reduced, and its radio frequency performance can be improved.

[0005] To achieve the above object and other related objects, the present invention provides a method for manufacturing a heterojunction bipolar transistor in a BiCMOS device, the method comprising:

[0006] A method for manufacturing a heterojunction bipolar transistor in a BiCMOS device, characterized by comprising the following steps:

[0007] Providing a substrate, the substrate including a CMOS device region and an HBT device region;

[0008] A well region is formed in the substrate, and shallow trench isolation is formed between adjacent well regions;

[0009] A collector region of a first conductivity type is formed above the well region in the HBT device region;

[0010] An intrinsic base region of a second conductivity type is formed above the collector region;

[0011] An emitter region of a first conductivity type is formed above the intrinsic base region;

[0012] Lifted non-intrinsic base regions of a second conductivity type are formed on both sides of the emitter region, and a graphene region is formed in the non-intrinsic base regions.

[0013] Optionally, forming a collector region of a first conductivity type above the well region in the HBT device region further includes the following steps:

[0014] Etch the hard mask layer on the surface of the substrate in the HBT device region to form a collector region window;

[0015] Form an epitaxial silicon layer in the collector region window;

[0016] Form an ion implantation window above the epitaxial silicon layer;

[0017] Perform P ion implantation on the epitaxial silicon layer through the ion implantation window to form a self-aligned doped collector region.

[0018] Optionally, forming an emitter region of a first conductivity type above the intrinsic base region further includes the following steps:

[0019] Form a mask layer above the intrinsic base region;

[0020] Pattern the mask to form an emitter region window;

[0021] Perform doped silicon epitaxial growth through the emitter window to form an emitter region.

[0022] Optionally, performing doped silicon epitaxial growth through the emitter window includes performing silicon epitaxial growth and in-situ As doping in the emitter region window.

[0023] Optionally, forming an intrinsic base region above the collector region includes:

[0024] Form a silicon buffer layer and a SiGe layer above the emitter region;

[0025] Perform C doping and B doping on the SiGe layer;

[0026] Form a silicon cap layer above the SiGe layer.

[0027] Optionally, forming an elevated extrinsic base region of the second conductivity type on both sides of the emitter region includes the following steps:

[0028] Selectively epitaxially grow a silicon layer on both sides of the emitter region;

[0029] Dope C and B in the silicon layer;

[0030] Perform plasma treatment on the doped C;

[0031] Perform laser annealing on the doped silicon layer to form a graphene region in the silicon layer.

[0032] Optionally, when doping C and B in the silicon layer, it further includes implanting a metal catalyst in the silicon layer.

[0033] Optionally, the doping concentration of C is less than 10%, and the doping concentration of B is less than 5%.

[0034] Optionally, the metal catalyst is Ti or Zr, and the implantation concentration of the metal catalyst is less than 3%.

[0035] Optionally, the annealing temperature for performing laser annealing on the doped silicon layer is greater than 700 °C.

[0036] Optionally, form a MOS device in the CMOS device region.

[0037] According to another aspect of the present invention, a BiCMOS device is provided, and the BiCMOS device includes:

[0038] A substrate, the substrate includes a CMOS device region and an HBT device region;

[0039] A well region formed in the substrate, and shallow trench isolation is formed between adjacent well regions;

[0040] A heterojunction bipolar transistor formed in the HBT device region, and the heterojunction bipolar transistor includes:

[0041] A collector region of the first conductivity type, located above the well region of the HBT device region;

[0042] An intrinsic base region of the second conductivity type, located above the collector region;

[0043] An emitter region of the first conductivity type, located above the intrinsic base region;

[0044] An elevated extrinsic base region of the first conductivity type, located on both sides of the emitter region, and a graphene region is formed in the extrinsic base region.

[0045] Optionally, the collector region includes an epitaxial silicon layer and a self-aligned doped collector region formed in the epitaxial silicon layer.

[0046] Optionally, the intrinsic base region includes a silicon buffer layer, a C-doped SiGe layer, and a silicon cap layer formed above the collector region.

[0047] Optionally, the material of the emitter region is an As-doped silicon layer.

[0048] Optionally, the BiCMOS device further includes: MOS devices formed in the CMOS device region.

[0049] As described above, the BiCMOS provided by the present invention and the manufacturing method of the heterojunction bipolar transistor therein have at least the following beneficial technical effects:

[0050] In the present invention, when forming the raised extrinsic base region of the heterojunction bipolar transistor, C and B are first doped in situ in the epitaxial silicon, and a metal catalyst is doped simultaneously. Then, plasma treatment and laser annealing are performed on C to form a graphene region in the Si epitaxial layer. Since graphene has good mobility, the base resistance of the SiGe HBT can be reduced, and its radio frequency performance can be improved. The above method can form a graphene region in the extrinsic base region by performing plasma treatment and laser annealing on the doped C on the basis of the traditional BiCMOS device process. The whole process is easy to control and easy to integrate with the traditional BiCMOS device process.

[0051] The extrinsic base region of the heterojunction bipolar transistor formed by the above method has a graphene region with better mobility, so it has a smaller base resistance, which makes the heterojunction bipolar transistor have better video performance. Description of the Drawings

[0052] Figure 1 It shows a schematic flow chart of the manufacturing method of the heterojunction bipolar transistor provided in Embodiment 1 of the present invention.

[0053] Figure 2 It shows a schematic diagram of the substrate.

[0054] Figure 3 It shows a gate stack formed on the substrate surface before forming the collector region.

[0055] Figure 4 It shows a schematic structural diagram of forming a collector region above the HBT device region.

[0056] Figure 5 It shows a schematic structural diagram of forming the intrinsic base region.

[0057] Figure 6Schematic diagram showing the formation of an emitter window above the intrinsic base region.

[0058] Figure 7 Schematic diagram showing the formation of an emitter.

[0059] Figure 8 Shown as etching Figure 7 Schematic diagram of the structure until the oxygen-containing layer is exposed by etching the structure shown.

[0060] Figure 9 Shown as etching Figure 8 Schematic diagram of the structure where the hard mask in the gate stack exposes the intrinsic base region shown.

[0061] Figure 10 Schematic diagram showing the formation of a raised extrinsic base region.

[0062] Figure 11 Shown as in Figure 10 Schematic diagram of the structure where emitter contacts, base contacts, and collector contacts are formed in the structure shown.

[0063] List of reference numerals

[0064] 100 Substrate 105 Intrinsic base region

[0065] 101 Shallow trench isolation 1051 Silicon buffer layer

[0066] 102 Well region 1052 SiGe layer

[0067] 103 Gate stack 1053 Silicon cap layer

[0068] 1031 Gate oxide layer 106 Mask layer

[0069] 1032 Polysilicon 107 Emitter

[0070] 1033 Silicon oxynitride layer 1070 Emitter contact

[0071] 1034 Silicon dioxide layer 108 Oxide layer

[0072] 1040 Collector window 109 Extrinsic base region

[0073] 104 Collector 1090 Base contact

[0074] 1041 Self-aligned doped collector 110 Dielectric layer

[0075] 1042 Collector contact 111 Spacer sidewall Detailed implementation manners

[0076] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0077] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, positional relationship, and ratio of each component in actual implementation can be arbitrarily changed on the premise of implementing the technical solution of the present invention, and the component layout form may also be more complex.

[0078] Embodiment 1

[0079] Graphene is an allotrope of carbon and consists of a single layer of carbon atoms connected by sp2 hybrid bonds. Due to its unique electrical, thermal, and mechanical properties, it has attracted research attention. An important application of graphene is as a potential substitute for indium tin oxide (ITO) as the next-generation large-area transparent conductive electrode (TCE). A special advantage of using graphene (assuming no defects) is its unique 2D electron gas property at room temperature, resulting in extremely high mobility. Currently, the common method for growing large-area graphene is by chemical vapor deposition (CVD). However, this method requires a deposition temperature of approximately 1000 °C. In addition, the resulting graphene film needs to be transferred to a special substrate. This greatly increases the preparation cost of graphene. To overcome these limitations, the latest method studies the growth of graphene in amorphous carbon (α-C) through plasma surface treatment at 600 °C. Therefore, understanding the graphitization mechanism of α-C is crucial for producing high-quality graphene. In 2013, Barreiro et al. reported the growth of graphene in α-C without a catalyst by current-induced annealing. They observed the structural evolution through in-situ TEM and molecular dynamics simulations. At the same time, α-C clusters were simulated. Excitingly, at high temperatures, long fibers composed of these clusters were formed. These clusters with fibers act as a carbon source and can repair defects on the graphene sheets.

[0080] In view of the good electrical properties of graphene and the research on its formation method, this embodiment provides a manufacturing method for a heterojunction bipolar transistor in a BiCMOS device, forming a non-intrinsic base region with a graphene region in the heterojunction bipolar transistor to reduce the base resistance and improve the radio frequency performance of the device. As Figure 1 shown, the method includes the following steps:

[0081] Step S101: Provide a substrate, which includes a CMOS device region and an HBT device region;

[0082] Step S102: Form well regions in the substrate, and form shallow trench isolation between adjacent well regions;

[0083] The substrate of this embodiment can be selected according to the actual requirements of the device. For example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a SOI (Silicon-on-insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. As Figure 2 shown, in the preferred embodiment of this embodiment, the provided substrate 100 is a silicon substrate. This substrate can be divided into a CMOS device region C for forming MOS devices and an HBT device region H for forming HBT devices. The CMOS device region C and the HBT device region H can be divided according to specific device integration requirements. Attached Figure 2 is only a simple example.

[0084] Similarly, as Figure 2 shown, an isolation structure 101 is formed in the substrate 100. For example, a silicon nitride layer can be first formed above the substrate 100 as a barrier layer and a stop layer for subsequent etching and other processes, then photoresist is spin-coated, and exposure and development are performed to define the active region. The photoresist is removed, and the substrate 100 is dry-etched using the above-mentioned silicon nitride layer as a hard mask to form shallow trenches. After forming the shallow trenches, oxidation is performed to form a thin layer of silicon oxide in the shallow trenches, and then silicon oxide is filled in the shallow trenches by chemical vapor deposition (CVD) to form shallow trench isolation 101. Rapid thermal annealing (RTA) can also be performed on the silicon oxide to make it more dense and repair the damage caused to the substrate in the previous steps.

[0085] After forming the above-mentioned shallow trench isolation 101, a thermal oxide layer and a sacrificial oxide layer (not shown in detail) are grown on the substrate surface as a masking layer for forming well regions. The masking layer is etched to define the range of the well regions, doping ions are pushed into the silicon substrate by ion implantation, and the doping ions are activated by rapid thermal annealing process and the lattice damage caused by ion implantation is repaired. The above-mentioned well regions include N-well regions and P-well regions.

[0086] Step S103: Form a collector region of a first conductivity type above the well region in the HBT device region;

[0087] Taking the formation of an npn-type heterojunction bipolar transistor as an example in this embodiment, the well region formed in the HBT device region H in the substrate is an n-type well region. An N-type collector region is formed above this N-type well region. Specifically as follows:

[0088] First, still referring toFigure 3 , a gate stack 103 is formed on the substrate surface. For example, first, the sacrificial oxide layer and the thermal oxide layer of the mask layer for forming the well region are removed, the substrate surface is cleaned, and then a first gate oxide layer is formed on the substrate surface by thermal oxidation; afterwards, the first gate oxide layer and a part of the silicon substrate surface are removed by wet etching, and a second gate oxide layer is formed by a second thermal oxidation in the core device region, thereby forming a gate oxide layer 1031 above the substrate. Then, polysilicon 1032 and a hard mask are deposited above the substrate, and the hard mask includes a silicon oxynitride layer 1033 and a silicon dioxide layer 1034 formed in sequence.

[0089] Under the action of the hard mask (the silicon oxynitride layer 1033 and the silicon dioxide layer 1034) in the above-mentioned gate stack 103, the polysilicon 1032 and the gate oxide layer 1031 in the gate stack are etched until the substrate surface is exposed, forming a collector region window 1040. Selective silicon epitaxial growth is carried out in the collector region window to form a collector region 104, and in this embodiment, the collector region 104 is undoped single-crystalline silicon or polysilicon.

[0090] Similarly referring to Figure 4 , after forming the above-mentioned collector region 104, under the shielding of the mask, the collector region is selectively doped to form an N-type self-aligned collector implant 1041 (SCI) in the collector region 104. Optionally, the collector region 104 can be doped with P ions to form the above-mentioned SIC.

[0091] Step S104: Form an intrinsic base region of the second conductivity type above the collector region;

[0092] After forming the above-mentioned SIC, referring to Figure 5 , non-selective epitaxial growth is carried out in the collector region window 1040 to form an intrinsic base region 105, and in this embodiment, the intrinsic base region is formed of a P-type semiconductor material. For example, first, a silicon buffer layer 1051 is epitaxially grown, then a SiGe epitaxial layer 1052 is grown, and carbon is doped in the SiGe epitaxial layer to form a SiGe:C layer. Optionally, B can also be doped simultaneously. Then, a silicon cap layer 1053 is formed above the SiGe epitaxial layer 1052. Thus, the intrinsic base region 105 is formed, where the content ratio of Ge in SiGe:C is about 10-15%, and the content ratio of C is about 1-5%.

[0093] Step S105: Form an emitter region of the first conductivity type above the intrinsic base region;

[0094] First, as Figure 6 shown, in Figure 5A mask layer 106 is formed above the structure shown, and then the mask layer is etched until it stops at the silicon capping layer of the intrinsic base region, or a part of the silicon capping layer can also be etched to form an opening. Then, spacer sidewalls 111 are formed on the sidewalls of the opening to the emitter region window 1070. Then, as Figure 7 shown, silicon epitaxial growth is carried out within the emitter region window to form an emitter region 107. In this embodiment, the emitter region 107 is formed as n-type doped epitaxial silicon, such as polysilicon doped with As. The height of the emitter region ranges from 10 nm to 30 nm.

[0095] Step S106: Raised non-intrinsic base regions of the second conductivity type are formed on both sides of the emitter region, and graphene regions are formed within the non-intrinsic base regions.

[0096] As Figure 8 shown, first, an oxide layer 108 covering the emitter region is formed above the Figure 7 structure shown. Under the shielding of this oxide layer, etching is carried out downward until it stops at the gate oxide layer 1031; afterwards, as Figure 9 shown, the hard mask in the gate stack is removed by wet etching, that is, the silicon dioxide layer 1034 and the silicon oxynitride layer 1033 are sequentially removed to expose the silicon buffer layer 1051 and the SiGe layer 1052 in the intrinsic base region. Then, as Figure 10 shown, selective silicon epitaxial layer is carried out to form a raised silicon epitaxial structure. In-situ heavy doping of C and B is carried out in this silicon epitaxial structure, and at the same time, a catalyst metal is doped. Then, C plasma treatment is carried out and annealing is carried out, thereby forming graphene regions in the silicon outer structure. This silicon epitaxial structure with graphene regions finally forms a raised non-intrinsic base region 109. In an alternative embodiment, the C doping amount in the silicon epitaxial structure is less than 10%, the B doping amount is less than 5%, the metal catalysis can be Ti or Zr, and the doping amount of the metal catalyst is less than 3%. After the C plasma treatment, laser annealing is carried out at a temperature higher than 700 °C to form graphene regions in the silicon epitaxial structure.

[0097] Since graphene has good mobility, it can reduce the base resistance of the SiGe HBT and improve its radio frequency performance.

[0098] After forming the above-mentioned emitter region, non-intrinsic base region and collector region, as Figure 11 shown, the gate oxide layer 1031 on the surface of the substrate is removed, a dielectric layer 110 is formed on the surface and sidewalls of the device, and then a metal layer or a metal silicide layer is deposited in the dielectric layers corresponding to the emitter region, non-intrinsic base region and collector region through processes such as etching and deposition, thereby forming an emitter contact 1071, a base contact 1090 and a collector contact 1042.

[0099] After forming the above HBT device, an MOS device is further formed above the substrate corresponding to the CMOS device region C of the substrate. For example, the polysilicon in the gate stack above the CMOS device region C is patterned to form polysilicon covering the channel region, and a spacer layer is formed on the sidewalls of the polysilicon. Under the action of the spacer layer, the fin is halo-doped to form an n-type or p-type doped region. Then, epitaxial SiGe is formed on both sides of the crystalline silicon, and in-situ doping or p-type heavy doping is performed to form p-type source and drain regions. Alternatively, epitaxial Si is formed on both sides of the polysilicon, and in-situ doping or n-type heavy doping is performed to form n-type source and drain regions. Then, an interlayer dielectric layer is deposited and planarized to expose the polysilicon. Then, the polysilicon is removed to form a gate opening, a high-k gate dielectric layer is deposited in the gate opening, work function metal layers suitable for nMOS or pMOS devices are respectively formed above the gate dielectric layer, and finally a gate metal layer is formed. Then, the source, drain, and gate are respectively formed.

[0100] Taking the formation of an npn-type heterojunction bipolar transistor as an example, this embodiment details the method for forming a heterojunction bipolar transistor in the BiCMOS device process. It should be understood that this method is also applicable to the formation of a pnp-type heterojunction bipolar transistor.

[0101] As described above, in this embodiment's method, C and B are in-situ doped in the epitaxial silicon, and a metal catalyst is doped simultaneously. Then, C is subjected to plasma treatment and laser annealing to form a graphene region in the Si epitaxial layer, thereby forming a non-intrinsic base region with a graphene region. Since graphene has good mobility, it can reduce the base resistance of the SiGe HBT and improve its radio frequency performance. The above method can form a graphene region in the non-intrinsic base region by performing plasma treatment and laser annealing on the doped C based on the traditional BiCMOS device process. The whole process is easy to control and easy to integrate with the traditional BiCMOS device process.

[0102] The above method is easy to integrate into the Fin FET technology platform, easy to implement, and the formed heterojunction bipolar transistor has good electrical properties.

[0103] Embodiment 2

[0104] This embodiment provides a BiCMOS device, also referring to Figures 2 to 11 , the heterojunction bipolar transistor includes:

[0105] A substrate, the substrate includes a CMOS device region and an HBT device region;

[0106] The substrate 100 may include a silicon substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, and so on. As Figure 2 shown, in a preferred embodiment of the present embodiment, the provided substrate 100 is a silicon substrate. The substrate may be divided into a CMOS device region C for forming MOS devices and an HBT device region H for forming HBT devices. The CMOS device region C and the HBT device region H may be divided according to specific device integration requirements, and the following is only a simple example. Figure 2 For example only.

[0107] Well regions are formed in the substrate, and shallow trench isolation is formed between adjacent well regions;

[0108] As Figure 2 and Figure 11 shown, well regions 102 are formed in the substrate 100, and the doping ions can be pushed into the silicon substrate by ion implantation to form the above well regions. The above well regions include N-well regions and P-well regions. A well region 102 serving as a collector region is formed between the well regions. In the present embodiment, the well region 105 is an n-type doped well region.

[0109] A heterojunction bipolar transistor formed in the HBT device region. In the present embodiment, taking the formation of an npn-type heterojunction bipolar transistor as an example, the well region formed in the HBT device region H of the substrate is an n-type well region. The heterojunction bipolar transistor includes:

[0110] A collector region of a first conductivity type, located above the well region of the HBT device region; in the present embodiment, the collector region 104 is an N-type collector region, in which an N-type self-aligned collector implant (SCI) 1041 is formed. Optionally, the collector region 104 can be doped with P ions to form the above SIC.

[0111] An intrinsic base region of a second conductivity type, located above the collector region; the intrinsic base region 105 is a P-type intrinsic base region, which includes a silicon buffer layer 1051, a SiGe epitaxial layer 1052, and a silicon cap layer 1053 located above the SiGe epitaxial layer 1052. The SiGe epitaxial layer is doped with C ions to form a SiGe:C layer. Optionally, B ions can also be doped simultaneously. The content ratio of Ge in SiGe:C is about 10-15%, and the content ratio of C is about 1-5%.

[0112] An emitter region of a first conductivity type, located above the intrinsic base region; in this embodiment, the emitter region 107 is formed as epitaxial silicon doped with n-type, such as polysilicon doped with As. The height of the emitter region is between 10 nm and 30 nm.

[0113] An elevated non-intrinsic base region of a first conductivity type, located on both sides of the emitter region, and a graphene region is formed in the non-intrinsic base region. By in-situ co-doping C and B in the epitaxial structure, and simultaneously doping a catalyst metal, and then performing C plasma treatment and annealing, a graphene region is formed in the non-intrinsic base region 109. In an alternative embodiment, the C doping amount in the silicon epitaxial structure is less than 10%, the B doping amount is less than 5%, the metal catalyst can be Ti or Zr, and the doping amount of the metal catalyst is less than 3%. After performing plasma treatment on C, laser annealing is performed at a temperature higher than 700 °C to form a graphene region in the silicon epitaxial structure.

[0114] The BiCMOS device of this embodiment further includes MOS devices formed in the CMOS device region C of the substrate. The MOS devices include nMOS and / or pMOS devices. The MOS devices include a channel region formed in the well region of the CMOS device region C, and source and drain regions located on both sides of the channel region. A gate structure is formed on the outer layer of the channel region, and source and drain electrodes are respectively formed outside the source and drain regions.

[0115] This embodiment is also described with an npn-type heterojunction bipolar transistor. It should be understood that the above heterojunction bipolar transistor can also be a pnp-type heterojunction bipolar transistor.

[0116] As described above, the BiCMOS provided by the present invention and the manufacturing method of the heterojunction bipolar transistor therein have at least the following beneficial technical effects:

[0117] In the present invention, when forming the elevated non-intrinsic base region of the heterojunction bipolar transistor, C and B are first in-situ doped in the epitaxial silicon, and a metal catalyst is simultaneously doped, and then plasma treatment and laser annealing are performed on C to form a graphene region in the Si epitaxial layer. Since graphene has good mobility, the base resistance of the SiGe HBT can be reduced, and its radio frequency performance can be improved. The above method can form a graphene region in the non-intrinsic base region by performing plasma treatment and laser annealing on the doped C on the basis of the traditional BiCMOS device process. The whole process is easy to control and easy to integrate with the traditional BiCMOS device process.

[0118] The non-intrinsic base region of the heterojunction bipolar transistor formed by the above method has a graphene region with better mobility, so it has a smaller base resistance, thereby enabling the heterojunction bipolar transistor to have better video performance.

[0119] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a heterojunction bipolar transistor in a BiCMOS device, characterized in that, It includes the following steps: Provide a substrate, the substrate including a CMOS device region and an HBT device region; Form well regions in the substrate, with shallow trench isolation formed between adjacent well regions; Form a collector region of a first conductivity type above the well region in the HBT device region; Form an intrinsic base region of a second conductivity type above the collector region; Form an emitter region of a first conductivity type above the intrinsic base region; Form raised non-intrinsic base regions of a second conductivity type on both sides of the emitter region through the following steps: Selectively epitaxially grow silicon layers on both sides of the emitter region; Dope C and B in the silicon layers; Perform plasma treatment on the doped C; Perform laser annealing on the doped silicon layers to form graphene regions in the silicon layers.

2. The manufacturing method according to claim 1, characterized in that, Forming a collector region of a first conductivity type above the well region in the HBT device region further includes the following steps: Etch the hard mask layer on the surface of the substrate in the HBT device region to form a collector region window; Form an epitaxial silicon layer in the collector region window; Form an ion implantation window above the epitaxial silicon layer; Perform P ion implantation on the epitaxial silicon layer through the ion implantation window to form a self-aligned doped collector region.

3. The manufacturing method according to claim 1, wherein Forming an emitter region of a first conductivity type above the intrinsic base region further includes the following steps: Form a mask layer above the intrinsic base region; Pattern the mask to form an emitter region window; Perform doped silicon epitaxial growth through the emitter region window to form an emitter region.

4. The manufacturing method according to claim 3, characterized in that, Performing doped silicon epitaxial growth through the emitter region window includes performing silicon epitaxial growth and in-situ As doping in the emitter region window.

5. The manufacturing method according to claim 1, characterized in that, Forming an intrinsic base region above the collector region includes: Form a silicon buffer layer and a SiGe layer above the emitter region; Perform C doping and B doping on the SiGe layer; Form a silicon cap layer above the SiGe layer.

6. The manufacturing method according to claim 1, characterized in that, When doping C and B in the silicon layers, it further includes injecting a metal catalyst into the silicon layers.

7. The manufacturing method according to claim 1, wherein The doping concentration of C is less than 10%, and the doping concentration of B is less than 5%.

8. The manufacturing method according to claim 6, characterized in that, The metal catalyst is Ti or Zr, and the injection concentration of the metal catalyst is less than 3%.

9. The manufacturing method according to claim 1, characterized in that, The annealing temperature for performing laser annealing on the doped silicon layers is greater than 700 °C.

10. The manufacturing method according to claim 1, characterized in that, Form MOS devices in the CMOS device region.

11. A BiCMOS device, characterized in that, It includes: A substrate, the substrate including a CMOS device region and an HBT device region; Well regions formed in the substrate, with shallow trench isolation formed between adjacent well regions; A heterojunction bipolar transistor formed in the HBT device region, the heterojunction bipolar transistor including: A collector region of a first conductivity type, located above the well region in the HBT device region; An intrinsic base region of a second conductivity type, located above the collector region; An emitter region of a first conductivity type, located above the intrinsic base region; Raised non-intrinsic base regions of a second conductivity type, including selectively epitaxially grown silicon layers located on both sides of the emitter region, the silicon layers being doped with C and B, the doped C being subjected to plasma treatment, and the doped silicon layers being subjected to laser annealing to form graphene regions in the silicon layers.

12. The BiCMOS device according to claim 11, wherein, The collector region includes an epitaxial silicon layer and a self-aligned doped collector region formed in the epitaxial silicon layer.

13. The BiCMOS device according to claim 11, wherein The intrinsic base region includes a silicon buffer layer, a C-doped SiGe layer, and a silicon cap layer formed above the collector region.

14. The BiCMOS device according to claim 11, wherein, The material of the emitter region is an As-doped silicon layer.

15. The BiCMOS device according to claim 11, wherein It further includes: MOS devices formed in the CMOS device region.

Images