Transistor Device, Electronic Device and Forming Method with Self-Aligned Contact Structure

Abstract

The present invention discloses a method for forming a transistor device with a self-aligned contact structure, comprising the following steps: forming a plurality of gate structures on a semiconductor substrate, the gate structures including gates and sidewall spacers formed on opposite sidewalls of the gates; depositing an insulating material layer above the gate structures to form an insulating layer; cutting the insulating layer to form a covering layer located above the gate structures; cutting the covering layer to form self-aligned contact elements above the semiconductor substrate, wherein the width of the covering layer is greater than the width of the gate structures, and the self-aligned contact elements are electrically insulated from the gate structures through the covering layer and the sidewall spacers. Thus, the problems in the prior art, such as the presence of metal residues on the sidewall spacers, the difficulty in controlling the high load of the finally formed NMOS / PMOS gates, and the difficulty in maintaining the chamber doors used in the process of the recessed gate structure (rich in polymers), are avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a transistor device with a self-aligned contact structure, a method for forming the same, and an electronic device including the transistor device. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. The technological development of integrated circuit design and materials has produced several generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. In the process of the development of integrated circuits, the geometric dimensions have gradually shrunk.

[0003] As the size of the integrated circuit shrinks, the distance between the self-aligned contact structure and the gate becomes smaller, so the probability of short-circuit generating leakage current increases. Conventionally, when manufacturing a transistor device with a self-aligned contact structure, after forming a gate structure 102 on a semiconductor substrate 101 through a gate polishing process, a recess operation needs to be performed on the gate structure; then an insulating layer 103 is deposited on the recessed gate structure; then a polishing process is performed; finally, a self-aligned contact element 104 is formed by cutting on the polished gate structure. Thus, the Figure 1 transistor device as shown is formed. The transistor device generated by this method has the following problems:

[0004] 1. There are residues of the metal gate on the sidewall spacer 105;

[0005] 2. It is difficult to control the height load of the finally formed NMOS / PMOS gate;

[0006] On the one hand, due to the etching selectivity of the metal material and the high-K dielectric material in the metal gate, the heights of the metal material and the high-K dielectric material in the same metal gate are different; on the other hand, due to the presence of a gate dense area (Dense) and a sparse area (Iso) on the semiconductor substrate, the volume ratios of the metal material and the high-K dielectric material in different regions are different, resulting in different heights of the same material in different metal gates. As Figure 2 shown, three different heights appear during the gate etch-back process.

[0007] 3. By-products (such as metal fluorides, Ti x F y or Ta x F y ) are generated during the process of recessing the gate structure, resulting in difficult maintenance of the etching chamber used.

[0008] During the etching process, the metal material reacts with the etching gas, and the generated by-products are likely to deposit above the metal gate, affecting the etching effect; the generated by-products are likely to deposit in the etching chamber, affecting the use of the etching equipment. Summary of the Invention

[0009] The object of the present invention is to provide a method for forming a transistor device with a self-aligned contact structure.

[0010] The technical solution adopted by the present invention is: constructing a method for forming a transistor device with a self-aligned contact structure, including the following steps:

[0011] Form a plurality of gate structures on a semiconductor substrate, where the gate structures include gates and sidewall spacers formed on opposite sidewalls of the gates;

[0012] Deposit an insulating material on top of the gate structures to form an insulating layer;

[0013] Cut the insulating layer to form a covering layer on top of the gate structures;

[0014] Form self-aligned contact elements above the semiconductor substrate. Among them, the width of the covering layer is greater than the width of the gate structures, and the self-aligned contact elements are electrically insulated from the gate structures through the covering layer and the sidewall spacers.

[0015] In the method for forming a transistor device with a self-aligned contact structure provided by the present invention, the step of cutting the insulating layer to form a covering layer on top of the gate structures includes:

[0016] Form a photoresist layer on top of the insulating layer;

[0017] Form one or more openings in the photoresist layer through an etching process;

[0018] Cut the insulating layer through the one or more openings to form the covering layer.

[0019] In the method for forming a transistor device with a self-aligned contact structure provided by the present invention, the step of cutting the covering layer to form self-aligned contact elements above the semiconductor substrate includes:

[0020] Deposit an interlayer dielectric layer on top of the covering layer;

[0021] Form a photoresist layer on the interlayer dielectric layer;

[0022] Form one or more openings in the photoresist layer through an etching process;

[0023] Cut the covering layer through the one or more openings to form the self-aligned contact elements.

[0024] According to another aspect of the present invention, there is also provided a transistor device with a self-aligned contact structure, including:

[0025] A plurality of gate structures located above a semiconductor substrate, each of the gate structures including a gate and sidewall spacers formed on opposite sidewalls of the gate;

[0026] A covering layer formed on the surface of the gate structure; and

[0027] Self-aligned contact elements located above the semiconductor substrate, wherein the width of the covering layer is greater than the width of the gate structure, and the self-aligned contact elements are electrically insulated from the gate structure through the covering layer and the sidewall spacers.

[0028] In the transistor device with a self-aligned contact structure provided by the present invention, the sidewall spacers include sidewalls and an etch stop layer.

[0029] In the transistor device with a self-aligned contact structure provided by the present invention, the sidewalls are silicon dioxide, silicon nitride or a composition thereof. The etch stop layer is silicon nitride.

[0030] In the transistor device with a self-aligned contact structure provided by the present invention, the gate is a metal gate, including a high-K material layer and a metal layer.

[0031] In the transistor device with a self-aligned contact structure provided by the present invention, the covering layer is silicon nitride.

[0032] The transistor device with a self-aligned contact structure of the present invention and its forming method have the following beneficial effects: The present invention deposits an insulating layer above the gate structure, cuts the insulating layer to form a covering layer with a width greater than that of the gate structure, and then cuts the covering layer to form self-aligned contact elements. The self-aligned contact elements formed thereby partially overlap with the gate structure and are electrically insulated from the gate structure through the covering layer and the sidewall spacers, thus avoiding the problem of metal residues on the sidewall spacers in the prior art; the NMOS / PMOS gate height load formed finally is difficult to control; and the chamber door of the cavity used in the process of the recessed gate structure is difficult to maintain (rich in polymers). BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts:

[0034] Figure 1 Shown is a cross-sectional view of a transistor device with a self-aligned contact structure formed by the prior art;

[0035] Figure 2The following is a flowchart of a method for forming a transistor device with a self-aligned contact structure provided by an embodiment of the present invention;

[0036] Figures 3 - 9 are cross-sectional schematic diagrams of each stage of a method for forming a self-aligned contact structure according to the invention. Detailed implementation manners

[0037] The following discloses many different implementation methods or examples to implement different features of the embodiments of the present invention. The following describes embodiments of specific components and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration and should not limit the scope of the embodiments of the present invention. For example, when it is mentioned in the specification that a first feature is formed on a second feature, it includes embodiments where the first feature and the second feature are in direct contact, and also includes embodiments where there are other features between the first feature and the second feature. That is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or markings may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0038] In addition, spatially relative terms may be used, such as "below", "beneath", "lower", "above", "higher", and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one (or some) element or feature and another (or some) element or feature in the drawings. These spatially relative terms include different orientations of the device during use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

[0039] Although the steps in some of the described embodiments are performed in a specific order, these steps may also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and some other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor element structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.

[0040] An embodiment of the present invention provides a method for forming a transistor device with a self-aligned contact structure. An insulating layer is deposited above the gate structure, the insulating layer is cut to form a covering layer with a width greater than the gate structure, and then a self-aligned contact element is formed. The self-aligned contact element formed in this way is electrically insulated from the gate structure through the covering layer and sidewall spacers, thus avoiding the problems of metal residues on the sidewall spacers in the prior art; the NMOS / PMOS gate height load formed finally is difficult to control; and the chamber doors used in the process of forming the recessed gate structure are difficult to maintain (rich in polymers).

[0041] Figure 2 Shown is a flowchart of a method 20 for forming a transistor device with a self-aligned contact structure provided by an embodiment of the present invention; Figures 3 - 9 are cross-sectional schematic diagrams of each stage of a method for forming a self-aligned contact structure according to the invention. The following will <* Figure 2 the flowchart of Figures 3 to 9 the cross-sectional schematic diagram of to illustrate the embodiments of the present invention.

[0042] As Figure 2 and Figure 3 shown, the method 20 starts with step 201, providing a substrate 301 on which a gate structure is formed, and the gate structure includes a gate and sidewall spacers.

[0043] In some embodiments, Figure 3 the substrate 301 in may be a semiconductor substrate, which may include elemental semiconductors such as silicon (Si), germanium (Ge), etc.; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors such as silicon-germanium alloy (SiGe), gallium arsenide phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), gallium indium arsenide alloy (GaInAs), gallium indium phosphide alloy (GaInP), gallium indium arsenide phosphide alloy (GaInAsP), or a combination of the above materials.

[0044] Next, a gate structure is formed on the substrate 301. The gate structure includes a gate and sidewall spacers formed on the opposite sidewalls of the gate. In some embodiments, the gate may include polysilicon, a metal (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, their analogs, or a combination thereof), a metal alloy, a metal nitride (such as tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, their analogs, or a combination thereof), a metal silicide (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, their analogs, or a combination thereof), a metal oxide (ruthenium oxide, indium tin oxide, their analogs, or a combination thereof), other suitable materials, or a combination of the above. The gate can be formed on the substrate 301 using a chemical vapor deposition process (such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD)), a physical vapor deposition process (PVD) (such as resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition process, other suitable processes, or a combination of the above to form the electrode material, and then the gate electrode is patterned by photolithography and etching processes.

[0045] In some embodiments, sidewall spacers are formed on the opposite sidewalls of the gate. The sidewall spacers can be oxides, nitrides, oxynitrides, high-k materials, low-k materials, or a combination of the above. The precursor materials or reaction gases for forming the sidewall spacers may include triethoxysilane (TRIES), tetraethoxysilane (TEOS), bis-tertbutylaminor silane (BTBAS), O2, N2O, NO, other gases or materials, or a combination of the above. In some embodiments, chemical vapor deposition (such as high density plasma chemical vapor deposition (HDPCVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition, or plasma enhanced chemical vapor deposition), atomic layer deposition, other suitable techniques, or a combination of the above can be used to conformally deposit the spacer material on the gate structure and the substrate, and then the spacer material is anisotropically etched back to leave sidewall spacers on both sides of the gate.

[0046] In a preferred embodiment of the present invention, the gate is a metal gate, and the metal gate includes a high-K material layer 3021 and a metal layer 3022; the sidewall spacer includes a sidewall 3031 and an etch stop layer 3032. The sidewall is silicon dioxide, silicon nitride, or a combination thereof. The etch stop layer is silicon nitride. Among them, the formation process of the metal gate structure is as follows: 1) Deposit a polysilicon gate layer on the semiconductor substrate; 2) Use photolithography and etching techniques to form a semiconductor substrate with a polysilicon pattern based on the polysilicon gate mask; 3) Form sidewall spacers adjacent to the gate on the semiconductor substrate in step 2); 4) Etch the polysilicon and deposit the metal gate.

[0047] As Figure 2 and Figure 4 illustrated, method 20 then proceeds to step 202 to deposit and form an insulating layer 304 above the gate structure. In some embodiments, the insulating layer 304 is a silicon nitride material. The insulating layer 304 can be formed using a suitable deposition process (such as chemical vapor deposition (CVD) or atomic layer deposition (ALD)), other suitable processes, or a combination of the above.

[0048] As Figure 2 and Figure 7 illustrated, method 20 then proceeds to step 203 to cut the insulating layer 304 to form a capping layer 305 above the gate structure. As Figure 7 shown, the width of the capping layer 305 is greater than the width of the gate structure. The capping layer is silicon nitride. The reason for using silicon nitride is that silicon nitride has a good etch ratio with the interlayer dielectric layer material. Specifically, as Figure 5 shown, first, a three-layer photoresist layer 306 is formed above the insulating layer 304; in some embodiments, chemical vapor deposition (such as high-density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition process, electroplating method, spin-on coating, other suitable techniques, or a combination of the above can be used to form a three-layer mask layer on the insulating layer; then as Figure 6 shown, one or more openings 307 are formed in the top layer of the three-layer photoresist layer through an etching process; finally, the insulating layer is cut through the one or more openings to form the capping layer 305.

[0049] In the above "cutting the insulating layer to form a covering layer above the gate structure", the covering layer mask used can directly use the above "polysilicon gate mask", and only the horizontal position of the mask needs to be changed during use. The present invention changes the existing manufacturing process, but its materials and equipment can generally use the original materials, resulting in less fluctuation in the transformation of the production line. It should be noted that the preparation method of the present invention can correct the size of the covering layer by etching on the basis of using the polysilicon gate mask.

[0050] As Figure 2 and Figure 9 shown, method 20 then proceeds to step 204 to form a self-aligned contact element 308 above the semiconductor substrate 301, as Figure 9 shown, the self-aligned contact element 308 is electrically insulated from the gate structure through the covering layer 305 and the sidewall spacers. Specifically, as Figure 8 shown, first, an interlayer dielectric layer 310 is deposited above the covering layer 305; then a three-layer photoresist layer is formed above the interlayer dielectric layer 310; in some embodiments, chemical vapor deposition (such as high-density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition process, electroplating method, spin-on coating, other suitable techniques, or a combination of the above can be used to form a three-layer photoresist layer on the insulating layer; then one or more openings 309 are formed in the top layer of the three-layer photoresist layer through an etching process. In some embodiments, the etching process may include a dry etching process (such as reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination of the above; finally, the covering layer is cut through the one or more openings to form the self-aligned contact element 308.

[0051] The self-aligned contact element of the present invention as described above is connected to the source / drain of the semiconductor substrate.

[0052] The present invention also provides an electronic device, which includes a transistor device having a self-aligned contact structure manufactured by the method according to an exemplary embodiment of the present invention. The electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the transistor device. The electronic device has better performance due to the use of the transistor device.

[0053] The present invention has been described by the above embodiments. However, it should be understood that the above embodiments are only for the purpose of illustration and exemplification, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A method for forming a transistor device with a self-aligned contact structure, characterized in that, Including the following steps: Forming a plurality of gate structures on a semiconductor substrate, the gate structures including gates and sidewall spacers formed on opposite sidewalls of the gates; wherein, the step of forming a plurality of gate structures on the semiconductor substrate includes: depositing a polysilicon gate layer on the semiconductor substrate; providing a polysilicon gate mask; based on the polysilicon gate mask, forming a semiconductor substrate with a polysilicon pattern by lithography and etching; forming sidewall spacers adjacent to the gates on the semiconductor substrate with the polysilicon pattern; etching the polysilicon and depositing the gates; Depositing an insulating material layer above the gate structures to form an insulating layer; Cutting the insulating layer to form a capping layer above the gate structures; wherein, the step of cutting the insulating layer to form a capping layer above the gate structures includes: Forming a photoresist layer above the insulating layer; Based on the polysilicon gate mask, forming one or more openings in the photoresist layer by etching; Cutting the insulating layer through the one or more openings to form the capping layer; Forming self-aligned contact elements above the semiconductor substrate, wherein the width of the capping layer is greater than the width of the gate structures, and the self-aligned contact elements are electrically insulated from the gate structures through the capping layer and the sidewall spacers.

2. The method for forming a transistor device with a self-aligned contact structure according to claim 1, wherein The step of forming self-aligned contact elements above the semiconductor substrate includes: Depositing an interlayer dielectric layer above the capping layer; Forming a photoresist layer on the interlayer dielectric layer; Forming one or more openings in the photoresist layer by etching; Cutting the capping layer through the one or more openings to form the self-aligned contact elements.

3. A transistor device with a self-aligned contact structure formed by the method for forming a transistor device with a self-aligned contact structure according to claim 1 or 2, characterized in that, Including: A plurality of gate structures located above a semiconductor substrate, each of the gate structures including a gate and sidewall spacers formed on opposite sidewalls of the gate; A capping layer formed on the surface of the gate structures; And Self-aligned contact elements, located above the semiconductor substrate, wherein the width of the capping layer is greater than the width of the gate structures, and the self-aligned contact elements are electrically insulated from the gate structures through the capping layer and the sidewall spacers.

4. The transistor device with a self-aligned contact structure according to claim 3, characterized in that, The sidewall spacers include sidewalls and etch stop layers.

5. The transistor device with a self-aligned contact structure according to claim 4, characterized in that, The sidewalls are silicon dioxide, silicon nitride or a combination thereof; the etch stop layer is silicon nitride.

6. The transistor device with a self-aligned contact structure according to claim 3, characterized in that, The gates are metal gates, including a high-K material layer and a metal layer.

7. The transistor device with a self-aligned contact structure according to claim 3, characterized in that, The capping layer is silicon nitride.

8. An electronic device, characterized in that, Including the transistor device according to any one of claims 3-7.

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