Vertical memory device

Abstract

A vertical memory device includes a cell stack structure, a support structure, and a cell contact plug on a substrate. The cell stack structure includes gate patterns spaced apart from each other in a vertical direction and insulating layers between the gate patterns. The gate patterns extend in a first direction, and edges of the gate patterns along the first direction include stepped portions of a step shape. The support structure passes through the stepped portions of one of the cell stack structure and the gate patterns, and includes a spacer layer of a cup shape, a first metal pattern of a ring shape, and a second metal pattern filling an inner space of the spacer layer. The cell contact plug is on the stepped portions. The first metal pattern is at a same vertical height of the gate patterns. Sidewalls of the first metal pattern are adjacent to sidewalls of the gate patterns.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Korean Patent Application No. 10-2020-0184668, filed on December 28, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to vertical storage devices, and more specifically to vertical storage devices having a stable structure. Background Technology

[0004] Vertical memory devices, in which memory cells are vertically stacked on a substrate surface, have recently been developed. As the number of stacked memory cells in vertical memory devices increases, it becomes more difficult to form memory cells with a stable structure. Summary of the Invention

[0005] An embodiment of the present invention provides a vertical memory device including a cell stack structure, a support structure, and cell contact plugs. The cell stack structure includes gate patterns on a substrate and an insulating layer. The gate patterns are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the insulating layer is located between the gate patterns in the vertical direction. The gate patterns extend in a first direction parallel to the upper surface of the substrate, and the edges of the gate patterns along the first direction are stepped portions in a stepped shape. The support structure passes through the cell stack structure and through a stepped portion of one of the stepped portions of the gate patterns. The support structure includes a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern filling the internal space of the first spacer layer. Each first metal pattern has an annular shape surrounding the outer wall of the first spacer layer. Cell contact plugs are respectively located on the stepped portions of the gate patterns. The first metal patterns are respectively disposed at the vertical height of the corresponding gate pattern in the gate patterns. The sidewall of each first metal pattern is adjacent to the sidewall of the corresponding gate pattern in the gate patterns.

[0006] An embodiment of the present invention provides a vertical memory device including circuit patterns on a substrate, a cell stack structure, a channel structure, a support structure, via contacts, cell contact plugs, and a barrier layer. The substrate includes a first region, a second region, and a third region. The cell stack structure is formed above the circuit patterns in the first and second regions. The cell stack structure includes gate patterns and an insulating layer. The gate patterns are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the insulating layer is located between the gate patterns in a vertical direction. The gate patterns extend in a first direction parallel to the upper surface of the substrate, and the edges of the gate patterns along the first direction are stepped portions in a stepped shape. The channel structure passes through the cell stack structure in the first region. The support structure passes through the cell stack structure in the second region and through a stepped portion of one of the stepped portions of the gate patterns. The support structure includes a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern filling the internal space of the first spacer layer. Each first metal pattern has an annular shape surrounding the outer wall of the first spacer layer. The via contacts are spaced apart from the cell stack structure. The via contacts extend in a vertical direction. Cell contact plugs are placed on the stepped portion of the gate pattern. A barrier layer surrounds the surface of each gate pattern. First metal patterns are respectively disposed at the vertical height of the corresponding gate pattern in the gate pattern, and the barrier layer is located between the sidewall of the first metal pattern and the sidewall of the adjacent gate pattern.

[0007] An embodiment of the present invention provides a vertical memory device including a circuit pattern on a substrate, a lower cell stack structure, an upper cell stack structure, a channel structure, a support structure, via contacts, and cell contact plugs. The substrate includes a first region, a second region, and a third region. The lower cell stack structure is located above the circuit pattern on the first and second regions. The lower cell stack structure includes a first gate pattern and a first insulating layer. The first gate patterns are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the first insulating layer is located between the first gate patterns in the vertical direction. The first gate patterns extend in a first direction parallel to the upper surface of the substrate, and the edges of the first gate patterns along the first direction have stepped portions in a stepped shape. The upper cell stack structure is formed on the lower cell stack structure. The upper cell stack structure includes a second gate pattern and a second insulating layer. The second gate patterns are spaced apart from each other in a vertical direction, and the second insulating layer is located between the second gate patterns in the vertical direction. The second gate patterns extend in a first direction parallel to the upper surface of the substrate, and the edges of the second gate patterns along the first direction have stepped portions in a stepped shape. The channel structure passes through the lower cell stack structure and the upper cell stack structure in the first region. Each channel structure includes a bend at the boundary between the lower and upper cell stack structures. A support structure passes through the structure including the upper and lower cell stack structures in the second region, and through a stepped portion of one of the first and second gate patterns. The support structure includes a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern filling the internal space of the first spacer layer. Each first metal pattern has an annular shape surrounding the outer wall of the first spacer layer. Through-hole contacts are spaced apart from the upper and lower cell stack structures. The through-hole contacts extend vertically and are electrically connected to the circuit pattern. Cell contact plugs are respectively located on the stepped portions of the first and second gate patterns. The first metal pattern is disposed at the vertical height of the corresponding gate pattern in the first and second gate patterns. The through-hole contacts and the second metal pattern may comprise the same material.

[0008] According to an example embodiment, the vertical storage device may include a support structure, such that the vertical storage device can have a stable structure. Attached Figure Description

[0009] Embodiments of the present invention will become clearer from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A cross-sectional view of a vertical storage device according to an embodiment of the present invention is shown;

[0011] Figure 2AAn enlarged cross-sectional view of the stepped portion and the through-hole portion of a vertical storage device according to an embodiment of the present invention is shown;

[0012] Figure 2B It shows Figure 2A A cross-sectional view of the stepped portion of a vertical storage device in the horizontal direction;

[0013] Figure 3A An enlarged cross-sectional view of the stepped portion and the through-hole portion of a vertical storage device according to an embodiment of the present invention is shown;

[0014] Figure 3B It shows Figure 3A A cross-sectional view of the stepped portion of a vertical storage device in the horizontal direction;

[0015] Figure 4A An enlarged cross-sectional view of the stepped portion of a vertical storage device according to an embodiment of the present invention is shown;

[0016] Figure 4B It shows Figure 4A A cross-sectional view of the stepped portion in the horizontal direction in a vertical storage device;

[0017] Figure 5 A cross-sectional view in the horizontal direction of the stepped portion of a vertical storage device according to an embodiment of the present invention is shown;

[0018] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 A cross-sectional view illustrating a method for manufacturing a vertical storage device according to an embodiment of the present invention is shown;

[0019] Figure 26 A cross-sectional view of a vertical storage device according to an embodiment of the present invention is shown;

[0020] Figure 27 An enlarged cross-sectional view of the stepped portion and the through-hole portion of a vertical storage device according to an embodiment of the present invention is shown;

[0021] Figure 28 A schematic diagram of an electronic system including semiconductor devices according to an embodiment of the present invention is shown;

[0022] Figure 29 A schematic perspective view of an electronic system including semiconductor devices according to an embodiment of the present invention is shown;

[0023] Figure 30 A cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present invention is shown; and

[0024] Figure 31 A schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention is shown. Detailed Implementation

[0025] In the following description, a direction substantially perpendicular to the upper surface of the substrate is defined as the vertical direction, and two intersecting directions in the horizontal direction substantially parallel to the upper surface of the substrate are defined as the first direction and the second direction, respectively. In an example embodiment, the first direction and the second direction may be perpendicular to each other.

[0026] Figure 1 A cross-sectional view of a vertical storage device according to an embodiment of the present invention is shown. Figure 2A and Figure 3A Each of the figures shows an enlarged cross-sectional view of the stepped portion and the through-hole portion in a vertical storage device according to an embodiment of the present invention. Figure 2B and 3B Each is a stepped portion in a vertical storage device, respectively along... Figure 2A Line 2B-2B and Figure 3A A cross-sectional view of line 3B-3B in the horizontal direction.

[0027] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The vertical storage device may include a circuit pattern formed on the substrate 100, a memory cell formed above the circuit pattern, and wiring that electrically connects the circuit pattern and the memory cell.

[0028] Substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V compounds such as GaP, GaAs, or GaSb. In some example embodiments, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The substrate 100 may include a first region A, a second region B, and a third region C. The first region A and the second region B may be memory cell regions. Specifically, the first region A may be a region where a memory cell array is formed, and the second region B may be an extension region extending from the memory cell array. The second region B may be the region where the cell pads of the gate pattern are located. The third region C may be a region where via contacts connected to lower peripheral circuitry are formed. Each of the first to third regions A, B, and C may include an upper surface of the substrate 100 and a portion extending from the upper surface of the substrate 100 in the vertical direction Z.

[0030] In an example embodiment, the vertical storage device may have a cell-over-periphery (COP) structure. That is, peripheral circuitry for driving the storage cells may be formed on the substrate 100 below the storage cells. Circuit patterns may be used as peripheral circuitry. Isolation patterns 102 may be formed in the substrate 100.

[0031] The circuit pattern may include a lower transistor 104, a lower contact plug 106, a lower wiring 108, etc. In the example embodiment, the lower contact plug 106 and the lower wiring 108 may be formed in multiple layers.

[0032] A lower interlayer insulating layer 110 may be formed on the substrate 100 to cover the circuit pattern. One or more of the lower contact plugs 106 may contact the impurity region, and although not shown, one or more of the lower contact plugs 106 may contact the gate of the lower transistor 104.

[0033] Some of the lower wirings 108 can be used as lower pad patterns 108a connected to the via contact 288, which will be described later. In an example embodiment, the lower pad pattern 108a may be one or more lower wirings 108 disposed on the uppermost layer of the lower wirings 108.

[0034] In the example embodiment, the lower pad pattern 108a may be formed in the third region C. However, although not shown, in some example embodiments, the via contact may be further formed in the first region A and the second region B. In this case, the lower pad pattern 108a may also be formed in the first region A and the second region B.

[0035] The substrate pattern 116 may be formed on the underlying interlayer insulating layer 110. In an example embodiment, the substrate pattern 116 may be formed in a first region A and a second region B. The substrate pattern 116 may include, for example, a polysilicon layer or a monocrystalline silicon layer.

[0036] The substrate insulating layer 118 may be formed on the lower interlayer insulating layer 110 in the third region C. The substrate insulating layer 118 may include, for example, silicon oxide. In an example embodiment, the upper surfaces of the substrate pattern 116 and the substrate insulating layer 118 may be substantially coplanar with each other.

[0037] Multiple memory cells can be formed on the substrate pattern 116. Hereinafter, the structure comprising multiple memory cells may be referred to as a cell stack structure. The cell stack structure may extend in a first direction X. The multiple cell stack structures may be arranged spaced apart from each other in a second direction Y. A first opening (not shown) extending in the first direction X may be formed between the cell stack structures. The first opening may also be referred to as a word line cutout area.

[0038] The following describes a single-cell stack structure. The cell stack structure may include a channel connection pattern 211, a support layer 212, and a cell structure.

[0039] The channel connection pattern 211 and the support layer 212 can be formed on the substrate pattern 116. The channel connection pattern 211 and the support layer 212 can include, for example, polysilicon.

[0040] The cell structure can be formed on the support layer 212. The cell structure may include a lower structure and an upper structure stacked on the lower structure. The lower structure may include alternating stacked first insulating layers 220 and gate patterns 297. The upper structure may include alternating stacked second insulating layers 240 and gate patterns 297.

[0041] The first insulating layer 220 and the second insulating layer 240 may include, for example, silicon oxide. Figure 2A and Figure 3A As shown, the gate pattern 297 may include a third barrier metal pattern 295 and a gate conductive pattern 296. The third barrier metal pattern 295 may be formed on the surface of the gate conductive pattern 296.

[0042] In an example embodiment, the gate conductive pattern 296 may include a metallic material, such as tungsten. The third blocking metal pattern 295 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0043] The second barrier layer pattern 292 may be formed on the surface of the gate pattern 297. The second barrier layer pattern 292 may include a metal oxide, such as aluminum oxide.

[0044] The edge of the unit structure located in the second region B in the first direction X can have a stepped shape.

[0045] In the following text, a stepped portion can be defined as an exposed portion of a structure having a stepped shape that is not covered by an upper step. An extended portion can be defined as an unexposed portion of a structure having a stepped shape that is covered by an upper step.

[0046] In the cell structure of the second region B, the upper surface of the stepped portion of the gate pattern 297 located at the edge in the first direction X can be higher than the upper surface of the extended portion of the gate pattern 297 connected thereto. In the cell structure of the second region, the lower surface of the stepped portion of the gate pattern 297 and the lower surface of the extended portion of the gate pattern 297 connected thereto can be substantially coplanar with each other. Therefore, in the cell structure of the second region, the vertical thickness of the stepped portion of the gate pattern 297 can be greater than the vertical thickness of the extended portion of the gate pattern 297 connected thereto.

[0047] The first interlayer insulating layer 230 and the second interlayer insulating layer 250 may be formed on the unit structure. In an example embodiment, the first interlayer insulating layer 230 and the second interlayer insulating layer 250 may cover the stepped portion of the unit structure. The first interlayer insulating layer 230 may cover the stepped portion of the lower structure, and the second interlayer insulating layer 250 may cover the stepped portion of the upper structure. The first interlayer insulating layer 230 and the second interlayer insulating layer 250 may include, for example, silicon oxide.

[0048] The channel hole 254 can pass through the unit structure, support layer 212, and channel connection pattern 211 in the first region, and the channel hole 254 can expose the upper part of the substrate pattern 116. The channel hole 254 may include a lower channel hole passing through the lower structure, support layer 212, and channel connection pattern 211, and an upper channel hole passing through the upper structure and communicating (i.e., connected) with the lower channel hole. Both the lower and upper channel holes may have beveled sidewalls such that the diameter gradually decreases from top to bottom. That is, in each of the lower and upper channel holes, the lower diameter may be smaller than the upper diameter. In an example embodiment, the upper diameter of the lower channel hole may be larger than the lower diameter of the upper channel hole. Therefore, each channel hole 254 may include a bent portion with a bent shape at the boundary between the lower and upper channel holes.

[0049] The channel structure 268a may include a charge storage structure 260a, a channel 262, a filling insulating pattern 264, and a cover pattern 266.

[0050] For example, channel 262 may extend to the upper part of substrate pattern 116, and channel 262 may be cup-shaped. Charge storage structure 260a may surround the outer wall of channel 262. Charge storage structure 260a may include tunnel insulating pattern, charge storage pattern, and first barrier layer pattern sequentially stacked on the outer wall of channel 262. The first barrier layer pattern may contact second barrier layer pattern 292.

[0051] The channel connection pattern 211 can directly contact the lower part of the channel 262. Therefore, the channels 262 provided in the channel hole 254 can be electrically connected to each other through the channel connection pattern 211. The charge storage structure 260a can be formed above and below the channel connection pattern 211. The charge storage structure 260a can be cut by the channel connection pattern 211. Therefore, the upper and lower parts of the charge storage structure 260a can be separated from each other.

[0052] The channel 262 may include, for example, polysilicon. The tunnel insulating pattern may include, for example, silicon oxide. The charge storage pattern may include, for example, silicon nitride. The first barrier layer pattern may include, for example, silicon oxide.

[0053] A fill insulating pattern 264 may be formed on the channel 262. The fill insulating pattern 264 may be columnar to fill the internal space of the channel 262. A cover pattern 266 may be formed on the fill insulating pattern 264 and the channel 262, and the cover pattern 266 may include polysilicon. The lower surface of the cover pattern 266 may be higher than the upper surface of the uppermost gate pattern 297. In an example embodiment, the upper surface of the cover pattern 266 may be coplanar with the upper surface of the second interlayer insulating layer 250.

[0054] The third interlayer insulating layer 270 may be formed on the unit structure, the channel structure 268a, and the second interlayer insulating layer 250. The third interlayer insulating layer 270 may include, for example, silicon oxide.

[0055] Virtual channel hole 272 (refer to) Figure 12 It can pass through the unit structure, support layer 212, channel connection pattern 21, and first to third interlayer insulation layers 230, 250, and 270 in the second region, and the dummy channel hole 272 can expose the upper part of the substrate pattern 116.

[0056] The dummy channel hole 272 may have a beveled sidewall, allowing its diameter to gradually decrease from top to bottom. The uppermost part of the dummy channel hole 272 may have a first upper diameter, and the lower part may have a first lower diameter smaller than the first upper diameter. The dummy channel hole 272 may not include the bend between the lower and upper structures.

[0057] First gap 276a (refer to) Figure 14 ) and second gap 276 (refer to) Figure 14The first gap 276a and the second gap 276 can be located on the sidewall of the dummy channel hole 272 to communicate with (i.e., connect to) the dummy channel hole 272. The first gap 276a can be located at the same height as the gate pattern 297. The first gap 276a can be located adjacent to the stepped portion of the gate pattern 297, while the second gap 276 can be located on the sidewall of the dummy channel hole 272 below the stepped portion. That is, the first gap 276a can be the uppermost gap connected to each dummy channel hole 272.

[0058] In an example embodiment, at least a portion of the width of the first gap 276a in the lateral direction (i.e., horizontal direction) may be greater than the width of the second gap 276 located below the first gap 276a in the lateral direction. In an example embodiment, at least a portion of the height of the first gap 276a may be greater than the height of the second gap 276 located below the first gap 276a.

[0059] In the example embodiment, the height and width of the first gap 276a may vary depending on the position within the first gap 276a.

[0060] The support structure can be formed inside the dummy channel hole 272 and the first gap 276a and the second gap 276. The support structure may include the first metal patterns 280 and 280a, the first spacer layer 282 and the second metal pattern 286.

[0061] The first metal patterns 280 and 280a may be formed only in the first gap 276a and the second gap 276.

[0062] In example embodiments, such as Figure 2A and Figure 3A As shown, the sides of the first metal patterns 280 and 280a can be located inside the entrances of the first gaps 276a and the second gap 276 (i.e., the sidewalls of the dummy channel holes 272). That is, the first metal patterns 280 and 280a may not protrude from the sidewalls of the dummy channel holes 272.

[0063] In some example embodiments, the first metal patterns 280 and 280a may fill the first gap 276a and the second gap 276 without protruding from the sidewall of the dummy channel hole 272.

[0064] In an example embodiment, the first metal patterns 280 and 280a may include a metal, such as tungsten. A first barrier metal pattern 279 may be further formed on the surfaces of the first metal patterns 280 and 280a. The first barrier metal pattern 279 may be conformally formed on the surfaces of the first gap 276a and the second gap 276. The first barrier metal pattern 279 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0065] A first spacer layer 282 may be formed on the sidewalls and bottom of the dummy channel hole 272. The first spacer layer 282 may be cup-shaped. First metal patterns 280 and 280a may surround the outer wall of the first spacer layer 282, and each first metal pattern 280 and 280a may be annular. The first spacer layer 282 may cover the inner sidewalls of the first metal patterns 280 and 280a. The first spacer layer 282 may include, for example, silicon oxide or silicon nitride.

[0066] The first spacer layer 282 can be formed along the upper sidewall of the dummy channel hole 272 without filling the upper part of the dummy channel hole 272. The first spacer layer 282 can fill the lower part of the dummy channel hole 272. Therefore, the thickness of the first spacer layer 282 measured vertically in the Z direction from the bottom of the dummy channel hole 272 can be greater than the thickness of the first spacer layer 282 measured horizontally from the sidewall of the dummy channel hole 272. Furthermore, the bottom of the dummy channel hole 272 may not be exposed by the first spacer layer 282.

[0067] A second metal pattern 286 may be formed on the first spacer layer 282 to fill the dummy channel hole 272. A second barrier metal layer 285 may be further formed on the sidewalls and bottom of the second metal pattern 286. The second metal pattern 286 does not contact the bottom of the dummy channel hole 272 (i.e., the base pattern 116), and therefore the second metal pattern 286 may float relative to the bottom of the dummy channel hole 272. Therefore, the second metal pattern 286 may be used only to fill the dummy channel hole 272. The second metal pattern 286 may not be electrically connected to any circuit and may not perform any specific electrical function.

[0068] The second metal pattern 286 may include a metal, such as tungsten. The second barrier metal layer 285 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0069] The upper surface of the support structure may not be coplanar with the upper surface of the channel structure 268a. In the example embodiment, the upper surface of the support structure may be higher than the upper surface of the channel structure 268a.

[0070] During the manufacturing process of a vertical storage device, a support structure can support the cell stack structure to prevent tilting or collapse (i.e., prevent the cell stack structure from tilting and / or collapsing). For example, the support structure can prevent the first insulating layer 220 and the second insulating layer 240 included in the cell stack structure from tilting downwards during the manufacturing process of the vertical storage device.

[0071] The upper diameter of the support structure can remain unchanged. However, a portion of the sidewalls of the support structure below the upper diameter can be extended laterally due to the first metal patterns 280 and 280a. Therefore, the first metal patterns 280 and 280a can be included in the support structure (i.e., as part of it) so that the unit stack structure can be more stably supported by the first metal patterns 280 and 280a without increasing the upper diameter of the dummy channel hole 272.

[0072] If the upper diameter of the dummy channel hole 272 increases, then the through hole 274 described subsequently (see...) Figure 12 The diameter of the via may also increase. In this case, it may be difficult to accurately form the via 274 on the lower pad pattern 108a without misalignment.

[0073] The first metal patterns 280 and 280a may include metal such that the upper surface of the first metal patterns 280 and 280a can be used as part of the cell pad area on which the cell contact plug, which will be described later, is formed.

[0074] The via 274 can pass through the third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the substrate insulating layer 118, and the lower interlayer insulating layer 110 in the third region C. The via 274 can extend from the third interlayer insulating layer 270 to the lower pad pattern 108a in the vertical direction Z. The via 274 can be spaced apart from the cell stack structure.

[0075] The through hole 274 may have a beveled sidewall, causing its diameter to gradually decrease from top to bottom. The through hole 274 may have a second upper diameter larger than the first upper diameter of the dummy channel hole 272 and a second lower diameter larger than the first lower diameter of the dummy channel hole 272. That is, the diameter of the through hole 274 may be larger than the diameter of the dummy channel hole 272.

[0076] The second spacer 284 may be formed on the sidewall of the through hole 274. The second spacer 284 may be formed only on the sidewall of the through hole 274, and may not be formed at the bottom of the through hole 274.

[0077] A through-hole contact 288 may be formed on the second spacer 284 to fill the through-hole 274. The through-hole contact 288 may be electrically connected to a circuit pattern.

[0078] The second spacer 284 may comprise a material substantially the same as that of the first spacer layer 282. The through-hole contact portion 288 may comprise a material substantially the same as that of the second metal pattern 286. For example, as... Figure 2A As shown, a second barrier metal layer 285 may be further formed on the sidewall and bottom of the through-hole contact portion 288.

[0079] In the example embodiment, the upper surface of the support structure and the upper surface of the through-hole contact portion 288 may be coplanar. In the example embodiment, the upper surface of the support structure and the upper surface of the through-hole contact portion 288 may be higher than the upper surface of the channel structure 268a.

[0080] In the example embodiment, the lower surface of the support structure may not be coplanar with the lower surface of the through-hole contact portion 288. In the example embodiment, the lower surface of the support structure may be higher than the lower surface of the through-hole contact portion 288.

[0081] The upper diameter of the structure including the through-hole contact portion 288 and the second spacer 284 can be larger than the upper diameter of the support structure.

[0082] The fourth interlayer insulation layer 298 can be formed on the third interlayer insulation layer 270, the channel structure 268a, the support structure, the second spacer 284 and the through-hole contact portion 288.

[0083] Cell contact plug 300 can pass through the fourth interlayer insulating layer 298, the third interlayer insulating layer 270, the second interlayer insulating layer 250, and the first interlayer insulating layer 230 in the second region B, and cell contact plug 300 can contact the stepped portion of the gate pattern 297. Furthermore, first contact plug 300a can pass through the fourth interlayer insulating layer 298 in the third region C and can contact the via contact 288. Cell contact plug 300 can at least contact the upper surface of the stepped portion of the gate pattern.

[0084] The fifth interlayer insulation layer 310 can be formed on the fourth interlayer insulation layer 298, the unit contact plug 300 and the first contact plug 300a.

[0085] The second contact plug 312 can pass through the fifth interlayer insulation layer 310, the fourth interlayer insulation layer 298, and the third interlayer insulation layer 270 in the first region A, and the second contact plug 312 can contact the overlay pattern 266 of the channel structure 268a. The third contact plug 314 and the fourth contact plug 316 can pass through the fifth interlayer insulation layer 310 in the second region B and the third region C. The third contact plug 314 can contact the unit contact plug 300, and the fourth contact plug 316 can contact the first contact plug 300a.

[0086] Although not shown, an upper interlayer insulation layer may be further formed on the fifth interlayer insulation layer 310. The upper wiring may pass through the upper interlayer insulation layer and may be electrically connected to the second to fourth contact plugs.

[0087] In the following text, reference will be made to Figure 2A , Figure 2B , Figure 3A and Figure 3BThe first metal pattern 280a and the gate pattern 297 included in the support structure are described in more detail.

[0088] Apart from the contact area at the bottom of the unit contact plug 300, Figure 2A and Figure 3A They are basically the same. Except for the contact area at the bottom of the unit contact plug 300, Figure 2B and Figure 3B They are basically the same.

[0089] Reference Figure 2A and Figure 2B The first metal patterns 280 and 280a included in the support structure can surround the outer wall of the first spacer layer 282. That is, each of the first metal patterns 280 and 280a can be annular.

[0090] The first metal patterns 280 and 280a formed on the first spacer layer 282 can be spaced apart from each other in the vertical direction Z. In the cross-sectional view, the plurality of first metal patterns 280 and 280a formed on the first spacer layer 282 can protrude from the sidewall of the first spacer layer 282, so the first metal patterns 280 and 280a and the first spacer layer 282 can be comb-shaped.

[0091] Each of the first metal patterns 280 and 280a can be disposed at the same vertical height as each of the gate patterns. The sidewalls of each of the first metal patterns 280 and 280a can be adjacent to the sidewalls of each of the gate patterns 297, with the second barrier layer pattern 292 located therebetween. That is, in the second region, the second barrier layer pattern 292 and the gate pattern 297 can be disposed on the sidewalls of each of the first metal patterns 280 and 280a included in the support structure. In an example embodiment, the second barrier layer pattern 292 can directly contact the third barrier metal pattern 295 of the gate pattern 297 and the first barrier metal pattern 279 surrounding the first metal patterns 280 and 280a.

[0092] The second barrier layer pattern 292 can be disposed at the boundary between the first metal patterns 280 and 280a and the gate pattern 297, so that the first metal patterns 280 and 280a and the gate pattern 297 can be clearly distinguished by the second barrier layer pattern 292.

[0093] like Figure 2AAs shown, the vertical thickness of the stepped portion of the gate pattern 297 can be greater than the vertical thickness of the extended portion of the gate pattern 297 connected to it. Therefore, the vertical thickness of the first metal pattern adjacent to the stepped portion of the gate pattern 297 (i.e., the uppermost first metal pattern 280a) can be greater than the vertical thickness of the first metal pattern 280 in the extended portion below the stepped portion. The width of the uppermost first metal pattern 280a can be greater than the width of the first metal pattern 280 in the extended portion below the uppermost first metal pattern 280a. However, in Figure 1 In order to avoid the complexity of the attached drawings, the width of the topmost first metal pattern 280a and the width of the first metal pattern 280 in the extension below the topmost first metal pattern 280a are shown to be substantially the same.

[0094] In the example embodiment, the uppermost first metal pattern 280a can be disposed at the step portion and extend continuously beyond the step portion in the horizontal direction. That is, the uppermost first metal pattern 280a can be disposed at the step portion and at a portion of the extension connected to the step portion. In this case, the uppermost first metal pattern located on the extension portion can have a relatively small vertical thickness and width. Therefore, the uppermost first metal pattern 280a can have different vertical thicknesses and different widths depending on its position.

[0095] The gate pattern 297 may extend in the first direction X. In the second region, the upper surface of the stepped portion may be used as a cell pad area on which the cell contact plug 300 is formed. In the example embodiment, the uppermost first metal pattern 280a, the second barrier layer pattern 292, and the gate pattern 297 may be disposed in the cell pad area.

[0096] In example embodiments, such as Figure 2A and Figure 2B As shown, the cell contact plug 300 can contact the gate pattern 297 in the cell pad area.

[0097] In some example embodiments, such as Figure 3A and Figure 3B As shown, the cell contact plug 300 can contact the gate pattern 297, the second barrier layer pattern 292, and the topmost first metal pattern 380a in the cell pad area.

[0098] The bottom of the cell contact plug 300 can at least contact the gate pattern 297. Furthermore, the bottom of the cell contact plug 300 can also contact the uppermost first metal pattern 280a. Therefore, the contact area of ​​the cell contact plug 300 can be sufficiently increased.

[0099] The vertical storage device may include a support structure at the stepped portion of the cell stack structure in the second region. Therefore, the cell stack structure can be stably supported by the support structure. Specifically, the support structure may include a first metal pattern 280 and 280a in annular shape surrounding the outer wall of the first spacer layer 282. Therefore, the cell stack structure can be supported more stably without increasing the upper diameter of the dummy channel hole 272.

[0100] Figure 4A An enlarged cross-sectional view of a stepped portion in a vertical storage device according to an embodiment of the present invention is shown. Figure 4B The stepped portion of the vertical storage device is shown along... Figure 4A A cross-sectional view of line 4B-4B in the horizontal direction.

[0101] In addition to the shape of the supporting structure, such as Figure 4A The vertical storage device shown can be compared with the reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The vertical storage devices shown are basically the same or similar.

[0102] Reference Figure 4A and 4B The stepped portion can be wide enough. Therefore, a first gap 276a communicating (i.e., connecting) with the sidewall of the dummy channel hole 272 can be formed by etching the silicon nitride of the stepped portion (see...). Figure 14 That is, the first gap 276a may be formed only in the step portion, and the first gap 276a may not extend beyond the step portion to reach the extension portion.

[0103] The vertical thickness of the first metal pattern (i.e., the uppermost first metal pattern 280a) formed in the first gap 276a can be greater than the vertical thickness of the extension of the gate pattern 297 connected to the uppermost first metal pattern 280a. Furthermore, the width of the uppermost first metal pattern 280a can be greater than the width of the first metal pattern 280 in the extension below the uppermost first metal pattern 280a.

[0104] The first metal patterns 280 and 280a can surround the first spacer layer, thus forming a ring. The uppermost first metal pattern 280a can have the same height and the same width depending on its position.

[0105] Figure 5 A cross-sectional view in the horizontal direction of the stepped portion of a vertical storage device according to an embodiment of the present invention is shown.

[0106] In addition to the number of supporting structures Figure 5The vertical storage device can be used with a reference Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B The vertical storage devices shown are basically the same or similar.

[0107] Reference Figure 5 Multiple support structures can be formed on each step portion. In an example embodiment, multiple support structures can pass through one of the step portions, and multiple support structures can be spaced apart from the unit contact plug 300.

[0108] Each supporting structure can be compared with the reference. Figure 1 , Figure 4A and Figure 4B The supporting structures shown are basically the same.

[0109] Figures 6 to 25 A cross-sectional view illustrating a method for manufacturing a vertical storage device according to an embodiment of the present invention is shown.

[0110] Specifically, Figure 13 , Figure 14 , Figure 16 , Figure 17 , Figure 19 , Figure 21 and Figure 23 This is an enlarged cross-sectional view showing the stepped portion and the through-hole portion in a vertical storage device according to an example embodiment.

[0111] Reference Figure 6 A circuit pattern consisting of peripheral circuits can be formed on the substrate 100. An interlayer insulating layer 110 can be formed to cover the circuit pattern.

[0112] Specifically, a shallow trench isolation process can be performed on the substrate 100 to provide a field region in which isolation patterns 102 are formed and an active region in which isolation patterns 102 are not formed. Lower transistors 104, lower contact plugs 106, lower wiring 108, etc., can be formed on the substrate 100.

[0113] Some of the lower wiring 108 can be used as lower pad patterns 108a for connection to the through-hole contacts, which will be described later. Although not shown, the lower contact plug 106 and the lower wiring 108 can be formed in multiple layers.

[0114] A substrate pattern 116 may be formed on the lower interlayer insulating layer 110 in the first region A and the second region B. A substrate insulating layer 118 may be formed on the lower interlayer insulating layer 110 in the third region C.

[0115] Reference Figure 7A lower sacrificial layer structure 210 and a support layer 212 can be formed on the substrate pattern 116 and the substrate insulating layer 118. The lower sacrificial layer structure 210 may include first to third lower sacrificial layers 204, 206, and 208 stacked in sequence. In this case, the first lower sacrificial layer 204 and the third lower sacrificial layer 208 may include, for example, oxides such as silicon oxide, and the second lower sacrificial layer 206 may include, for example, nitrides such as silicon nitride. The support layer 212 may be formed of a material that has etch selectivity relative to the first to third lower sacrificial layers 204, 206, and 208. For example, the support layer 212 may include undoped polysilicon or polysilicon doped with n-type impurities. Although not shown, a portion of the support layer 212 may extend through the lower sacrificial layer structure 210 and may contact the upper surface of the substrate pattern 116.

[0116] The first insulating layer 220 and the first sacrificial layer 222 may be alternately stacked on the support layer 212. The first insulating layer 220 may include, for example, silicon oxide. The first sacrificial layer 222 may include a material that has etch selectivity relative to the first insulating layer 220. The first sacrificial layer 222 may include a nitride, such as silicon nitride.

[0117] The first insulating layer 220, the first sacrificial layer 222, the support layer 212 and the lower sacrificial layer structure 210 can be patterned to form a first initial molded structure 226 having a stepped shape in the second region B.

[0118] In an example embodiment, each step portion of the first initial molding structure 226 may have a structure in which a first insulating layer 220 and a first sacrificial layer 222 are stacked. In an example embodiment, the first sacrificial layer 222 may be exposed on each step portion of the first initial molding structure 226.

[0119] Reference Figure 8 A first sacrificial pattern 224 can be formed on each step portion of the first initial molding structure 226 to form the first molding structure 226a. The first sacrificial layer 222 and the first sacrificial pattern 224 can be formed from substantially the same material. In each step portion of the first molding structure 226a, the first sacrificial layer 222 and the first sacrificial pattern 224 can serve as the first sacrificial structure 228.

[0120] In the first molding structure 226a of the second region B, the extension portion may have a structure including a first insulating layer 220 and a first sacrificial layer 222 stacked sequentially, while the step portion may have a first insulating layer 220, a first sacrificial layer 222, and a first sacrificial pattern 224 stacked sequentially. Therefore, the thickness of the step portion may be greater than the thickness of the other portions (i.e., the extension portion). The upper surface of the step portion may be higher than the upper surfaces of the other portions.

[0121] Reference Figure 9 An insulating layer can be formed to cover the first molded structure 226a. The upper surface of the insulating layer can be planarized to form a first interlayer insulating layer 230.

[0122] A lower channel hole 232 can be formed in the first region through the first molding structure 226a, and the lower channel hole 232 can extend to the substrate pattern 116. A filling sacrificial layer 234 can be formed in the lower channel hole 232.

[0123] Reference Figure 10 The second insulating layer 240 and the second sacrificial layer 242 can be alternately stacked on the first molded structure 226a, the filling sacrificial layer 234 and the first interlayer insulating layer 230.

[0124] The second insulating layer 240 and the second sacrificial layer 242 can be patterned to form a second initial molding structure. In the second region B, the second initial molding structure can have a stepped shape connected to the first molding structure 226a.

[0125] A second sacrificial pattern 244 can be formed on each step portion of the second initial molding structure to form a second molding structure 246a. The second sacrificial layer 242 and the second sacrificial pattern 244 can be formed from substantially the same material. In each step portion of the second molding structure 246a, the second sacrificial layer 242 and the second sacrificial pattern 244 can serve as a second sacrificial structure 248.

[0126] An insulating layer can be formed to cover the second molded structure 246a. The upper surface of the insulating layer can be planarized to form a second interlayer insulating layer 250.

[0127] Subsequently, an upper channel hole 252 passing through the second molding structure 246a can be formed in the first region A. The upper channel hole 252 can be configured to communicate with the lower channel hole 232.

[0128] Reference Figure 11 The filler sacrificial layer 234 filling the lower channel hole 232 can be removed to form the channel hole 254. The channel hole 254 may include the lower channel hole 232 and the upper channel hole 252 that are connected to each other.

[0129] An initial channel structure 268 may be formed in the channel aperture 254. In an example embodiment, the initial channel structure 268 may include an initial charge storage structure 260, a channel 262, a filling insulating pattern 264, and a cover pattern 266. The initial charge storage structure 260 may include an initial first barrier layer, an initial charge storage layer, and an initial tunnel insulating layer sequentially stacked from the sidewall of the channel aperture 254.

[0130] The subsequent process will be described with reference to the enlarged cross-sectional views of the stepped and through-hole sections.

[0131] Reference Figure 12 and Figure 13 A third interlayer insulation layer 270 can be formed on the second interlayer insulation layer 250 and the initial channel structure 268.

[0132] A dummy channel hole 272 can be formed in the second region B, passing through the third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the first molding structure 226a and the second molding structure 246a, the support layer 212, and the lower sacrificial layer structure 210. Each dummy channel hole 272 can pass through one of the stepped portions and can extend to the upper part of the substrate pattern 116. In the etching process of forming the dummy channel hole 272, a through hole 274 can also be formed in the third region C, passing through the third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the substrate insulating layer 118, and the lower interlayer insulating layer 110. The through hole 274 can extend to the upper surface of the lower pad pattern 108a.

[0133] The dummy channel hole 272 can have a beveled sidewall, so that its diameter gradually decreases from top to bottom. The through hole 274 can also have a beveled sidewall, so that its diameter gradually decreases from top to bottom.

[0134] The dummy channel hole 272 can have a first upper diameter and a first lower diameter. The through hole 274 can have a second upper diameter larger than the first upper diameter and a second lower diameter larger than the first lower diameter. The diameter of the through hole 274 can be larger than the diameter of the dummy channel hole 272 because the etching rate of the portion forming the through hole 274 can be higher than the etching rate of the portion forming the channel hole 272 in the etching process. Therefore, the same etching process can simultaneously form dummy channel holes 272 and through holes 274 with different vertical heights along the third direction Z at the bottom.

[0135] The dummy channel hole 272 can be configured to be spaced apart from the subsequently formed unit contact plug.

[0136] In the example embodiment, the unit contact plug may be located near the edge of the stepped portion in the first direction X, and the dummy channel hole 272 may be disposed inside the stepped portion in which the unit contact plug is formed. That is, the dummy channel hole 272 may be disposed at a position further away from the edge of the stepped portion in the first direction X than the unit contact plug.

[0137] The third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the first insulating layer 220, the first sacrificial layer 222, the second insulating layer 240, the second sacrificial layer 242, the first sacrificial pattern 224, the second sacrificial pattern 244, the support layer 212, the lower sacrificial layer structure 210, and the substrate pattern 116 can be exposed by the sidewalls of the dummy via. The third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the substrate insulating layer 118, and the lower interlayer insulating layer 110 can be exposed by the sidewalls of the via 274. That is, the silicon nitride structure, such as the first sacrificial layer 222, the first sacrificial pattern 224, the second sacrificial layer 242, and the second sacrificial pattern 244, can be kept from being exposed by the sidewalls of the via 274.

[0138] Reference Figure 14 The silicon nitride structure exposed by the sidewall of the dummy channel hole 272 can be partially removed to form a first gap 276a and a second gap 276. The first gap 276a may be the uppermost gap that communicates (i.e., connects) with the sidewall of the dummy channel hole 272 in the stepped portion, while the second gap 276 may be the gap that communicates with the sidewall of the dummy channel hole 272 below the stepped portion.

[0139] In the removal process, the first sacrificial layer 222, the second sacrificial layer 242, the first sacrificial pattern 224, and the second sacrificial pattern 244, exposed by the sidewalls of the dummy channel hole 272, can be partially etched to a predetermined thickness. The etching process can include an isotropic etching process. The isotropic etching process can include, for example, a wet etching process using hydrofluoric acid (HF) and / or phosphoric acid (H3PO4).

[0140] The thickness of silicon nitride in the stepped portion can be greater than the thickness of silicon nitride in the extended portion, so that the etching rate of silicon nitride in the stepped portion can be higher than the etching rate of silicon nitride in the extended portion during the etching process. Therefore, the width and height of at least a portion of the first gap 276a located in the stepped portion can be greater than the width and height of each of the second gaps 276 located below the stepped portion.

[0141] In the example embodiment, when the stepped portion is not wide, the sidewall of the dummy channel hole 272 in the stepped portion can be close to the extension portion. Therefore, a portion of the first gap 276a can be formed by etching silicon nitride in the stepped portion, while another portion of the first gap 276a can be formed by etching silicon nitride in the extension portion adjacent to the stepped portion. Thus, the first gap 276a can have different heights and widths depending on its location.

[0142] In some example embodiments, when the stepped portion is sufficiently wide, the sidewalls of the dummy channel hole 272 in the stepped portion may not be close to the extension. Therefore, the first gap 276a can be formed by etching only the silicon nitride in the stepped portion. The silicon nitride in the extension may not be etched. In this case, the first gap 276a can have the same height and the same width depending on its location. When the stepped portion is sufficiently wide, a reference can be fabricated by subsequent processes. Figure 4A and 4B The vertical storage device shown.

[0143] The shape of the first metal pattern formed by subsequent processes can be different depending on the width and height of the first gap 276a and the second gap 276.

[0144] Reference Figure 15 and Figure 16 A first metal layer can be formed to fill the first gap 276a and the second gap 276. A portion of the first metal layer can be etched so that the first metal layer remains only in the first gap 276a and the second gap 276 to form the first metal patterns 280 and 280a. During the etching process, the first insulating layer 220 and the second insulating layer 240, the support layer 212, the lower sacrificial layer structure 210, and the substrate pattern 116 can be exposed by the dummy channel via 272.

[0145] Etching processes can include isotropic etching processes, such as wet etching processes.

[0146] In an example embodiment, the first metal patterns 280 and 280a may include a metal such as tungsten. Furthermore, a first barrier metal pattern 279 may be formed on the surface of the first metal patterns 280 and 280a.

[0147] In the process of forming the first metal layer, the first metal layer can also be formed on the sidewall of the via 274. However, in the partial etching process of the first metal layer, the first metal layer formed on the sidewall of the via 274 can be completely removed.

[0148] Reference Figure 17 A spacer insulating layer may be conformally formed on the third interlayer insulating layer 270 and on the inner surfaces of the dummy channel holes 272 and vias 274. For example, the spacer insulating layer may include silicon oxide or silicon nitride.

[0149] The upper diameter of the dummy channel hole 272 can be larger than its lower diameter, allowing the spacer insulation layer to not fill the upper part of the dummy channel hole 272. However, the lower diameter of the dummy channel hole 272 can be relatively narrow, allowing the spacer insulation layer to fold at the lower sidewall of the dummy channel hole 272. Therefore, the spacer insulation layer can fill the lower part of the dummy channel hole 272. The vertical thickness of the spacer insulation layer from the bottom of the dummy channel hole 272 can be greater than the deposition thickness of the spacer insulation layer.

[0150] The diameter of the through-hole 274 can be larger than the diameter of the dummy channel hole 272, allowing the spacer insulating layer to be conformally formed on the sidewalls and bottom of the through-hole 274. That is, the spacer insulating layer may not fill the lower part of the through-hole 274. The vertical thickness of the spacer insulating layer from the bottom of the through-hole 274 can be substantially the same as the deposition thickness of the spacer insulating layer.

[0151] Subsequently, the spacer insulating layer can be anisotropically etched to form a first spacer layer 282 on the sidewalls and bottom of the dummy channel via 272, and a second spacer 284 on the sidewall of the via 274. When the spacer insulating layer is anisotropically etched, the spacer insulating layer at the bottom of the dummy channel via 272 may not be completely etched. Therefore, the first spacer layer 282 can be sufficiently retained at the bottom of the dummy channel via 272, so that the bottom of the dummy channel via 272 is not exposed. When the spacer insulating layer is anisotropically etched, the spacer insulating layer at the bottom of the via 274 can be completely etched. Therefore, the bottom of the via 274 can be exposed by the second spacer 284. The lower pad pattern can be exposed at the bottom of the via 274.

[0152] Reference Figure 18 and Figure 19 Metal layers can be formed on the first spacer layer 282, the second spacer 284, and the third interlayer insulating layer 270 to fill the dummy channel holes 272 and through holes 274. Thereafter, a planarization process can be performed until the upper surface of the third interlayer insulating layer 270 can be exposed to form a second metal pattern 286 and a through hole contact 288. The second metal pattern 286 can be formed in the dummy channel holes 272, and the through hole contact 288 can be formed in the through holes 274.

[0153] like Figure 19 As shown, a second barrier metal layer 285 can be further formed on the sidewalls and bottom of the second metal pattern 286 and the through-hole contact portion 288.

[0154] The second metal pattern 286 may not contact the bottom of the dummy channel hole 272, and the second metal pattern 286 may float relative to the bottom of the dummy channel hole 272. The second metal pattern 286 may only be used to fill the dummy channel hole 272, and the second metal pattern 286 may not be electrically connected to any circuit or perform any specific electrical function. Therefore, a process to remove the second metal pattern 286 is not required.

[0155] The through-hole contact 288 can be electrically connected to the lower pad pattern 108a. Therefore, the through-hole contact 288 can be electrically connected to the circuit pattern.

[0156] Thus, the first spacer layer 282 and the second metal pattern 286 can be formed in the dummy channel hole 272. The first metal patterns 280 and 280a can be formed in the first gap 276a and the second gap 276 and communicate (i.e., connect) with the dummy channel hole 272. The first metal patterns 280 and 280a can contact the outer wall of the first spacer layer 282. The first metal patterns 280 and 280a, the first spacer layer 282, and the second metal pattern 286 formed in the dummy channel hole 272, the first gap 276a, and the second gap 276 can serve as a support structure to support the subsequently formed unit stack structure.

[0157] First metal patterns 280 and 280a may surround the outer wall of the first spacer layer 282. In a cross-sectional view, multiple first metal patterns 280 and 280a may laterally protrude from the sidewall of the first spacer layer 282, thus having a comb-like shape. A support structure may include the first metal patterns 280 and 280a, such that the subsequently formed structure in the second region (i.e., the cell stack structure) can be more stably supported by the support structure. The uppermost first metal pattern 280a may be used as part of the cell pad area on which cell contact plugs are formed. Therefore, the cell pad area can be larger, and the contact tolerance of the cell contact plugs can be increased. Thus, cell contact plugs can be easily formed on the cell pad area in subsequent processes.

[0158] Reference Figure 20 and Figure 21 An etching mask can be formed on the third interlayer insulating layer 270. The etching mask can be used to etch the third interlayer insulating layer 270, the second interlayer insulating layer 250, the first interlayer insulating layer 230, the first molding structure 226a and the second molding structure 246a, the support layer 212, and the lower sacrificial layer structure 210 to form a first opening (not shown) extending along the first direction X. By performing the etching process, the stacked structure including the first molding structure 226a and the second molding structure 246a can be cut to separate it into a linear molding structure extending in the first direction X.

[0159] The first opening can extend along the first direction X in the first region A and the second region B. The first opening can also be used as a word line cut-out area.

[0160] In an example embodiment, at least one of the second insulating layer 240 and the second sacrificial layer 242 located on the upper part of the second molding structure may be etched to form a trench (not shown) extending in the first direction X. The trench may be an SSL cutout area for forming an SSL (String Select Line).

[0161] Spacers (not shown) can be formed on the sidewall above the first opening of the support layer 212. The lower sacrificial layer structure 210 can be selectively removed to form a third gap (not shown). The initial charge storage structure 260 exposed by the third gap can be etched to form a charge storage structure 260a. The lower part of the channel 262 can be exposed by the etching process. Therefore, a channel structure 268a can be formed in the channel hole 254.

[0162] A channel connection pattern 211 can be formed to fill the third gap. Channels 262 formed in the channel via 254 can be electrically connected to each other via the channel connection pattern 211. The channel connection pattern 211 may include polysilicon. In an example embodiment, a first metal pattern 280 may also be formed in the channel connection pattern 211.

[0163] The removable spacer allows the sidewalls of the molded structure to be exposed through the first opening. The first sacrificial layer 222 and the second sacrificial layer 242, as well as the first sacrificial pattern 224 and the second sacrificial pattern 244 included in the molded structure, can be removed to form a fourth gap 290 between the first insulating layer 220 and between the second insulating layer 240. In the second region, the outer walls of the first metal patterns 280 and 280a can be exposed through the fourth gap 290.

[0164] The removal process can include wet etching.

[0165] When the first sacrificial layer 222 and the second sacrificial layer 242, as well as the first sacrificial pattern 224 and the second sacrificial pattern 244, are removed, in the first region A, the molded structure including the fourth gap 290 can remain straight and can be supported by the channel structure 268a. Furthermore, when the first sacrificial layer 222 and the second sacrificial layer 242, as well as the first sacrificial pattern 224 and the second sacrificial pattern 244, are removed, in the second region B, the molded structure including the fourth gap 290 and having a stepped shape can remain straight and can be supported by the support structure. Specifically, the first metal patterns 280 and 280a can be included in the support structure to provide more stable support for the stepped molded structure.

[0166] Reference Figure 22 and Figure 23A second barrier layer may be conformally formed on the surface of the fourth gap 290. This second barrier layer may be formed to prevent back tunneling in subsequently formed memory cells. The second barrier layer may include a metal oxide, such as aluminum oxide.

[0167] The second barrier layer formed in the second region B can contact the outer wall of the first metal patterns 280 and 280a.

[0168] A third barrier metal layer may be conformally formed on the surface of the second barrier layer. A gate conductive layer may be formed on the third barrier metal layer to fill the fourth gap 290. The gate conductive layer may include a metal, such as tungsten, copper, or aluminum.

[0169] A portion of the second barrier layer, the third barrier metal layer, and the gate conductive layer can be removed, leaving only the second barrier layer, the third barrier metal layer, and the gate conductive layer within the fourth gap 290. That is, the second barrier layer, the third barrier metal layer, and the gate conductive layer formed in the first opening can be removed.

[0170] Therefore, a second barrier layer pattern 292 and a gate pattern 297 can be formed in the fourth gap 290. The gate pattern 297 may include a third barrier metal pattern 295 and a gate conductive pattern 296. The second barrier layer pattern 292 may surround the surface of the gate pattern 297.

[0171] In the second region B, the second barrier layer pattern 292 may be located between the sidewalls of the first metal patterns 280 and 280a included in the support structure and the sidewalls of the adjacent gate pattern 297. In an example embodiment, the second barrier layer pattern 292 may directly contact the third barrier metal pattern 295 of the gate pattern 297 and the first barrier metal pattern 279 surrounding the first metal patterns 280 and 280a.

[0172] In the second region B, the second barrier layer pattern 292 and the gate pattern 297 can be laterally disposed on the sidewalls of the first metal patterns 280 and 280a included in the support structure. The second barrier layer pattern 292 can be disposed between the first metal patterns 280 and 280a and the gate pattern 297, so that the first metal patterns 280 and 280a and the gate pattern 297 can be clearly distinguished by the second barrier layer pattern 292.

[0173] The gate pattern 297 may extend in the first direction X. In the second region B, the upper surface of the stepped portion may be used as a cell pad area on which the cell contact plug 300 is formed. In the example embodiment, the uppermost first metal pattern 280a, the second barrier layer pattern 292, and the gate pattern 297 may be disposed in the cell pad area.

[0174] Reference Figure 24A fourth interlayer insulation layer 298 can be formed on the third interlayer insulation layer 270, the channel structure 268a, the support structure, the second spacer 284, and the through-hole contact portion 288.

[0175] The fourth interlayer insulating layer 298, the third interlayer insulating layer 270, the second interlayer insulating layer 250, and the first interlayer insulating layer 230 in the second region B can be etched to form cell contact holes that at least expose the gate pattern 297 in the cell pad area. In an example embodiment, the gate pattern 297 may be exposed by the bottom of each cell contact hole.

[0176] In some example embodiments, the gate pattern 297, the second barrier layer pattern 292, and the uppermost first metal pattern 280a may be exposed together by the bottom of each cell contact hole.

[0177] The fourth interlayer insulating layer 298 in the third region C can be etched to form a first contact hole on the upper surface of the exposed through-hole contact portion 288.

[0178] A conductive layer may be formed on the fourth interlayer insulating layer 298 to fill the cell contact holes and the first contact hole. The conductive layer may be planarized until the upper surface of the fourth interlayer insulating layer 298 is exposed to form the cell contact plug 300 filling the cell contact hole and the first contact plug 300a filling the first contact hole. In some example embodiments, a barrier metal layer may be further formed on the fourth interlayer insulating layer 298, the cell contact hole, and the first contact hole before the conductive layer is formed.

[0179] Cell contact plug 300 may at least contact gate pattern 297. In some example embodiments, such as Figure 3A and Figure 3B As shown, the cell contact plug 300 can contact the gate pattern 297, the second barrier layer pattern 292, and the topmost first metal pattern 280a.

[0180] In this way, a portion of the unit contact plug can contact the first metal pattern 280a, thereby increasing the contact tolerance of the unit contact plug.

[0181] Reference Figure 25 A fifth interlayer insulation layer 310 can be formed on the fourth interlayer insulation layer 298, the unit contact plug 300 and the first contact plug 300a.

[0182] A second contact plug 312 may be formed in the first region A, passing through the fifth interlayer insulation layer 310, the fourth interlayer insulation layer 298, and the third interlayer insulation layer 270. The second contact plug 312 may contact the overlay pattern 266 of the channel structure 268a. A third contact plug 314 may be formed in the second region B, passing through the fifth interlayer insulation layer 310 and the contact unit contact plug 300. A fourth contact plug 316 may be formed in the third region C, passing through the fifth interlayer insulation layer 310 and contacting the first contact plug 300a.

[0183] In some example embodiments, an upper interlayer insulating layer may be further formed on the fifth interlayer insulating layer 310. Upper wiring may be further formed through the upper interlayer insulating layer. The upper wiring may be electrically connected to each of the second to fourth contact plugs. As described above, a vertical storage device can thus be manufactured.

[0184] Figure 26 A cross-sectional view of a vertical storage device according to an embodiment of the present invention is shown. Figure 27 It shows Figure 26 Enlarged cross-sectional view of the stepped portion and through-hole portion of the vertical storage device.

[0185] In addition to the support structure and gate pattern shape in the cell pad area Figure 26 The vertical storage device in the reference can be used with Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The vertical storage devices shown are basically the same or similar.

[0186] Reference Figure 26 and Figure 27 The vertical thickness of the stepped portion at the edge of the gate pattern 297 in the first direction X can be substantially the same as the vertical thickness of the extended portion of the gate pattern 297 connected thereto. That is, the upper and lower surfaces of the gate pattern 297 can be substantially flat, and the gate pattern 297 can extend in the first direction X.

[0187] The vertical thickness of the first metal pattern 280a (i.e., the uppermost first metal pattern) in the step portion can be substantially the same as the vertical thickness of the first metal pattern 280 in the extension portion below the step portion. Furthermore, the width of the first metal pattern 280a in the step portion can be substantially the same as the width of the first metal pattern 280 in the extension portion below the step portion.

[0188] like Figure 26 The vertical storage device shown can be used with reference Figures 6 to 25 The processes shown are essentially the same or similar to those used in manufacturing. However, when performing the reference... Figure 8During the aforementioned process, the first sacrificial pattern 224 is not formed on the stepped portion of the first initial molding structure 226. Furthermore, when performing the reference... Figure 10 During the process shown, the second sacrificial pattern 244 is not formed on the stepped portion of the second initial molding structure.

[0189] Figure 28 A schematic diagram of an electronic system including semiconductor devices according to an embodiment of the present invention is shown.

[0190] Reference Figure 28 The electronic system 1000 according to an example embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a memory device including one or more semiconductor devices 1100 or an electronic device including such a memory device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0191] Semiconductor device 1100 may be a non-volatile memory device. For example, semiconductor device 1100 may have a reference such as Figure 1 , Figure 4A , Figure 4B , Figure 5 or Figure 26 The NAND flash memory device with COP structure shown.

[0192] Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In an example embodiment, the first structure 1100F may be located next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may include a bit line BL, a common source line CSL, a word line WL, a first gate-on wiring UL1 and a second gate-on wiring UL2, a first gate-below wiring LL1 and a second gate-below wiring LL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL. The second structure 1100S can be used as a memory cell structure.

[0193] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT located between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways according to the example embodiment.

[0194] In the example embodiment, the upper transistors UT1 and UT2 may include string select transistors, while the lower transistors LT1 and LT2 may include ground select transistors. Gate lower wirings LL1 and LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the gate upper wirings UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0195] In an example embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 that can be connected in series. The upper transistors UT1 and UT2 may include a series select transistor UT1 and an upper erase control transistor UT2 that are connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 can be used to erase data stored in the memory cell transistor MCT, and the data can be erased by using gate-induced leakage current (GIDL).

[0196] The common source line CSL, the first gate lower wiring LL1 and the second gate lower wiring LL2, the word line WL, and the first gate upper wiring UL1 and the second gate upper wiring UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1110F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1110F to the second structure 1100S.

[0197] In the first structure 1110F, the decoder circuit 1110 and the page buffer 1120 can control at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1110F to the second structure 1100S.

[0198] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the electronic system 1000 may include multiple semiconductor devices 1100. In this case, the controller 1200 may control the multiple semiconductor devices 1100.

[0199] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to firmware. Processor 1210 can control NAND controller 1220 to enable access to semiconductor device 1100. NAND controller 1220 may include NAND interface (I / F) 1221 for communicating with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to the memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from the memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted through NAND interface 1221. Communication between electronic system 1000 and external host can be performed through host interface (I / F) 1230. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0200] Figure 29 A schematic perspective view of an electronic system including semiconductor devices according to an embodiment of the present invention is shown.

[0201] Reference Figure 29 The electronic system 2000 according to an example embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

[0202] The main board 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may be arranged according to the communication interface between the electronic system 2000 and the external host. In an example embodiment, the electronic system 2000 may communicate with the external host, for example, via one of the interfaces including Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. In an example embodiment, the electronic system 2000 may be operated by power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) (not shown) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0203] The controller 2002 can write data to the semiconductor package 2003, or the controller 2002 can read data from the semiconductor package 2003. The controller 2002 can improve the operating speed of the electronic system 2000.

[0204] DRAM 2004 can be a buffer memory used to reduce the speed difference between the semiconductor package 2003 (for storing data) and the speed of an external host. DRAM 2004 included in electronic system 2000 can also be used as a high-speed cache memory, and DRAM 2004 can provide space for temporarily storing data during control operations of semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 can include a DRAM controller for controlling DRAM 2004 and a NAND controller for controlling semiconductor package 2003.

[0205] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connected to the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 on the package substrate 2100 covering the semiconductor chips 2200 and the connection structure 2400.

[0206] The package substrate 2100 may be a printed circuit board including package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 28 Input / output pads 1101. Each semiconductor chip 2200 may include a cell stack structure 3210, a channel structure 3220, and a notch region 3230. Each semiconductor chip 2200 may include, for example, a reference... Figure 1 , Figure 4A , Figure 4B , Figure 5 or Figure 26 The COP structure shown is a vertical storage device.

[0207] In an example embodiment, the connection structure 2400 may be a bonding wire for electrical connection to the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires. The semiconductor chips 2200 may be electrically connected to the on-package pads 2130 on the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of bonding wires.

[0208] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In another example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected via wiring formed on the interposer substrate.

[0209] Figure 30 and Figure 31 A schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention is shown. Figure 30 and Figure 31 Each picture in the middle is Figure 29 An example embodiment of a semiconductor package is shown. Figure 30 and Figure 31 Each image in the middle conceptually shows along Figure 29 The part of the I-I' line in the middle.

[0210] Reference Figure 30 In semiconductor packaging 2003, the packaging substrate 2100 can be a printed circuit board. The packaging substrate 2100 may include a packaging substrate body portion 2120 and packaging pads disposed on the upper surface of the packaging substrate body portion 2120 (see reference). Figure 29 The upper pad 2130 is provided on or exposed through the lower surface of the main body portion 2120 of the packaging substrate 2120, and the lower pad 2125 is provided inside the main body portion 2120 of the packaging substrate 2130 for electrical connection to the upper pad 2130 and the lower pad 2125. The upper pad 2130 can be electrically connected to the connection structure 2400. The lower pad 2125 can be connected to, for example, through the conductive connection portion 2800. Figure 29 Wiring pattern 2005 of the main substrate 2001 in the electronic system 2000 shown.

[0211] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, which includes peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a cell stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation structure (not shown) passing through the cell stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line (see reference) electrically connected to the cell stack structure 3210. Figure 28 The gate connection wiring 3235 of WL) is used.

[0212] Furthermore, the support structure 3500 can pass through the cell stack structure and can be disposed between the connecting wires. The support structure 3500 can support the portion of the cell stack structure used to form the connecting wires. The support structure 3500 can be referenced. Figure 1 , Figure 4A , Figure 4B , Figure 5 or Figure 26 The supporting structures shown are basically the same.

[0213] In an example embodiment, each semiconductor chip 2200 may include, for example, having a reference Figure 1 , Figure 4A , Figure 4B , Figure 5 or Figure 26 The COP structure shown is a vertical storage device.

[0214] Each semiconductor chip 2200 may also include a through-hole contact 3245, which is electrically connected to the peripheral wiring 3110 of the first structure 3100 and extends into the interior of the second structure 3200.

[0215] Some via contacts 3245 may be disposed adjacent to the cell stack structure. Some via contacts 3245 may pass through the cell stack structure. Each semiconductor chip 2200 may also include input / output pads 2210 electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0216] Reference Figure 31 In semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100. The second structure 4200 may be bonded to the first structure 4100 by a wafer bonding process.

[0217] The first structure 4100 may include a peripheral circuit area in which peripheral wiring 4110 and a first bonding structure 4150 are formed.

[0218] The second structure 4200 may include a common source line 4205, a cell stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 passing through the cell stack structure 4210, a separation structure (not shown), and word lines electrically connected to the cell stack structure 4210 (see reference). Figure 28 The second bonding structure 4250 of each of the WL and channel structures 4220. For example, the second bonding structure 4250 can be electrically connected to the word line (see reference 4235) via the connection wiring 4235. Figure 28 , WL) and each of the gates.

[0219] Furthermore, the support structure 4500 can pass through the cell stack structure 4210 and can be disposed between the connection wirings 4235. The support structure 4500 can support the portion of the cell stack structure 4210 used to form the connection wirings 4235. The support structure 4500 can be referenced... Figure 1 , Figure 4A , Figure 4B , Figure 5 or Figure 26 The supporting structures shown are basically the same.

[0220] In an example embodiment, each semiconductor chip 2200a may include, for example, having a reference Figure 1 or Figure 25 The COP structure shown is a vertical storage device.

[0221] The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 can be joined to each other. The joining portion between the first joining structure 4150 and the second joining structure 4250 can be formed of, for example, copper (Cu).

[0222] Each semiconductor chip 2200a may also include input / output pads (2210, see reference) electrically connected to the peripheral wiring 4110 of the first structure 4100. Figure 29 ).

[0223] Figure 30 The semiconductor chip 2200 shown and Figure 31 The semiconductor chips 2200a shown can be electrically connected to each other via a connection structure 2400 having a wire bonding type. In some example embodiments, semiconductor chips in a semiconductor package, for example... Figure 30 The semiconductor chip 2200 shown and Figure 31The semiconductor chip 2200a shown can be electrically connected to each other through a connection structure 2400 including a through-silicon via.

[0224] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. While some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the exemplary embodiments without substantially departing from the novel doctrine and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device plus function clause is intended to encompass the structures described herein that perform the functions, and includes not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A vertical storage device, comprising: A cell stack structure includes gate patterns on a substrate and an insulating layer, the gate patterns being spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, the insulating layer being located between the gate patterns in a vertical direction, the gate patterns extending in a first direction parallel to the upper surface of the substrate, and the edges of the gate patterns along the first direction being stepped portions in a stepped shape. A support structure, passing through the cell stack structure and through a step portion of one of the gate patterns, the support structure comprising a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern filling the interior space of the first spacer layer, each of the first metal patterns having an annular shape surrounding the outer wall of the first spacer layer; as well as Cell contact plugs are respectively located on the stepped portions of the gate pattern. The first metal pattern is disposed at the vertical height of the corresponding gate pattern in the gate pattern, and the sidewall of each first metal pattern is adjacent to the sidewall of each corresponding gate pattern in the gate pattern.

2. The vertical storage device according to claim 1, wherein, The support structure fills the dummy channel holes passing through the unit stack structure and fills the gaps connecting to the sidewalls of the dummy channel holes, the gaps being vertically spaced apart, and the first metal pattern is within the gaps. The first spacer layer is on the sidewalls and bottom of the dummy channel hole, and on the sidewalls of the first metal pattern.

3. The vertical storage device according to claim 2, wherein, The upper diameter of the dummy channel hole is greater than the lower diameter of the dummy channel hole, and the diameter of the dummy channel hole gradually decreases from the top of the dummy channel hole to the bottom of the dummy channel hole.

4. The vertical storage device according to claim 1, wherein, The vertical thickness of the stepped portion of the gate pattern is greater than the vertical thickness of the extended portion of the gate pattern, the extended portion being an unexposed portion covered by the stepped portion stacked on top of the stepped portion.

5. The vertical storage device according to claim 4, wherein, The vertical thickness of the first metal pattern adjacent to the stepped portion of the gate pattern is greater than the vertical thickness of the first metal pattern below the stepped portion of the gate pattern.

6. The vertical memory device of claim 1, further comprising a barrier layer comprising a metal oxide surrounding the surface of each of the gate patterns, the barrier layer being between a sidewall of the first metal pattern and a sidewall of a gate pattern adjacent to the sidewall of the first metal pattern.

7. The vertical storage device according to claim 1, wherein, The bottom of the unit contact plug contacts the stepped portion of the gate pattern, or contacts the stepped portion of the gate pattern and the upper surface of the first metal pattern adjacent to the stepped portion of the gate pattern.

8. The vertical memory device of claim 1, further comprising a channel structure passing through the cell stack structure but not through the stepped portion of the gate pattern, wherein the upper surface of the channel structure is not coplanar with the upper surface of the support structure.

9. The vertical storage device according to claim 1, further comprising a through-hole contact portion spaced apart from the unit stack structure and extending in the vertical direction. in, The upper surface of the through-hole contact portion is coplanar with the upper surface of the support structure, while the lower surface of the through-hole contact portion is not coplanar with the lower surface of the support structure.

10. The vertical storage device according to claim 1, wherein, The first metal patterns are spaced apart from each other in the vertical direction on the outer wall of the first spacer layer, and the first metal patterns protrude from the outer wall of the first spacer layer and have a comb-like shape in the cross-sectional view.

11. A vertical storage device, comprising: Circuit patterns on a substrate, the substrate including a first region, a second region, and a third region; A cell stack structure, above the circuit patterns on the first region and the second region, the cell stack structure includes a gate pattern and an insulating layer, the gate patterns being spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, the insulating layer being located between the gate patterns in a vertical direction, the gate patterns extending in a first direction parallel to the upper surface of the substrate and the edges of the gate patterns along the first direction being stepped portions in a stepped shape; A channel structure that passes through the unit stack structure in the first region; A support structure, passing through the cell stack structure in the second region and through a step portion of one of the step portions of the gate patterns, the support structure comprising a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern filling the interior space of the first spacer layer, each of the first metal patterns having an annular shape surrounding the outer wall of the first spacer layer; The through-hole contact portion is spaced apart from the unit stack structure and extends in the vertical direction; Unit contact plugs are respectively located on the stepped portions of the gate pattern; as well as A barrier layer surrounds the surface of each of the gate patterns. The first metal pattern is disposed at the vertical height of the corresponding gate pattern in the gate pattern, and the barrier layer is located between the sidewall of the first metal pattern and the sidewall of the gate pattern adjacent to the sidewall of the first metal pattern.

12. The vertical storage device according to claim 11, wherein, The barrier layer comprises a metal oxide.

13. The vertical storage device according to claim 11, wherein, The upper surface of the through-hole contact portion is coplanar with the upper surface of the support structure, and the lower surface of the through-hole contact portion is lower than the lower surface of the support structure.

14. The vertical storage device of claim 11, further comprising a second spacer surrounding the sidewall of the through-hole contact portion, the second spacer and the first spacer layer comprising the same material.

15. The vertical storage device according to claim 14, wherein, The upper diameter of the structure including the through-hole contact portion and the second spacer is larger than the upper diameter of the support structure.

16. The vertical storage device according to claim 11, wherein, The through-hole contact portion and the second metal pattern are made of the same material.

17. The vertical storage device according to claim 11, wherein, The bottom of the unit contact plug contacts the stepped portion of the gate pattern, or contacts the stepped portion of the gate pattern and the upper surface of the first metal pattern adjacent to the stepped portion of the gate pattern.

18. A vertical storage device, comprising: A circuit pattern on a substrate, the substrate including a first region, a second region, and a third region; A lower cell stack structure, above the circuit patterns on the first region and the second region, the lower cell stack structure includes a first gate pattern and a first insulating layer, the first gate patterns being spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, the first insulating layer being located between the first gate patterns in a vertical direction, the first gate patterns extending in a first direction parallel to the upper surface of the substrate and the edges of the first gate patterns along the first direction being stepped portions in a stepped shape; The upper cell stack structure, on the lower cell stack structure, includes a second gate pattern and a second insulating layer. The second gate patterns are spaced apart from each other in the vertical direction, and the second insulating layer is located between the second gate patterns in the vertical direction. The second gate patterns extend in a first direction parallel to the upper surface of the substrate, and the edges of the second gate patterns along the first direction are stepped portions in a stepped shape. A channel structure passing through the lower unit stack structure and the upper unit stack structure in the first region, each channel structure including a bent portion at the boundary between the lower unit stack structure and the upper unit stack structure; The support structure passes through the structure including the upper unit stack structure and the lower unit stack structure in the second region, and through a step portion of the step portion of one of the first gate pattern and the second gate pattern. The support structure includes a cup-shaped first spacer layer, a first metal pattern, and a second metal pattern that fills the internal space of the first spacer layer. Each of the first metal patterns has an annular shape surrounding the outer wall of the first spacer layer. A through-hole contact portion is spaced apart from the upper unit stack structure and the lower unit stack structure, and the through-hole contact portion extends in the vertical direction and is electrically connected to the circuit pattern; as well as Cell contact plugs are located on the stepped portions of each of the first gate pattern and the second gate pattern, respectively. Wherein, the first metal pattern is respectively disposed at the vertical height of the corresponding gate pattern in the first gate pattern and the second gate pattern, and The through-hole contact portion and the second metal pattern are made of the same material.

19. The vertical storage device according to claim 18, wherein, The upper surface of each of the channel structures is not coplanar with the upper surface of the support structure.

20. The vertical memory device of claim 18, further comprising a barrier layer comprising a metal oxide surrounding a surface of each of the first gate pattern and the second gate pattern, the barrier layer being between a sidewall of the first metal pattern and a sidewall of the first gate pattern and the second gate pattern adjacent to the sidewall of the first metal pattern.

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