OLED display panel and manufacturing method thereof

Abstract

An OLED display panel comprises a substrate, a thin film transistor layer, a flat layer and a pixel definition layer arranged in sequence. The flat layer is provided with a first via hole, the pixel definition layer is provided with a second via hole and a through hole, and the first via hole and the second via hole are through each other. The OLED display panel further comprises a light emitting device layer comprising an anode, a light emitting layer and a cathode arranged in sequence on one side of the flat layer. The light emitting layer is arranged in the through hole, and the cathode covers the pixel definition layer, the first via hole, the second via hole and the light emitting layer, thereby cutting off the path of water and oxygen transmission between the light emitting layers, increasing the reliability of the display area and the service life of the display panel. The application further provides a manufacturing method of a flexible OLED display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel, in particular to an OLED display panel and a manufacturing method thereof. BACKGROUND

[0002] Organic light emitting diode (OLED) has the advantages of self-illumination, fast response, wide viewing angle, high brightness, bright color, lightness and thinness, etc. compared with liquid crystal display (LCD), and is considered as the next generation display technology. According to the light emitting direction, OLED is divided into two categories: bottom emission and top emission. The bottom emission is limited in high PPI (Pixels Per Inch) products due to its relatively low aperture ratio. The transparent cathode of large-size top emission device cannot be too thick, which causes the problem of IR drop. In addition, ink-jet printing (IJP) is also favored due to its low cost compared with evaporation, and is applied in the manufacturing of OLED. In the existing research and development process of top emission ink-jet printing technology, a planarization layer (PLN) and a pixel definition layer (PDL) need to be laid on the TFT device due to the demand for the planarity of RGB materials. However, when the planarization layer and the pixel definition layer are locally encapsulated, the water and oxygen / humidity from the outside can easily enter the TFT and RGB light emitting materials in the display area along the two layers, which affects the reliability and reliability of the device. SUMMARY

[0003] The present application relates to the technical field of display panel, in particular to an OLED display panel and a manufacturing method thereof.

[0004] To achieve the aforementioned object, the present application provides an OLED display panel, comprising a substrate, a thin film transistor layer, a planar layer and a pixel definition layer. The thin film transistor layer is arranged on one side of the substrate. The planar layer is arranged on the side of the thin film transistor layer away from the substrate. The pixel definition layer is arranged on the side of the planar layer away from the thin film transistor layer, wherein the planar layer is provided with a first via hole, the pixel definition layer is provided with a second via hole and a through hole, and the first via hole and the second via hole are through each other. The OLED display panel further comprises a light-emitting device layer, which comprises an anode, a light-emitting layer and a cathode arranged in sequence on the side of the planar layer away from the thin film transistor layer. The anode and the thin film transistor layer are electrically connected. The light-emitting layer is arranged in the through hole. The cathode covers the pixel definition layer, the first via hole, the second via hole and the light-emitting layer.

[0005] In the OLED display panel provided by the present application, the first via hole and the second via hole are arranged between the display area and the non-display area.

[0006] In the OLED display panel provided by the present application, the display area comprises a plurality of pixel units, and the first via hole and the second via hole are arranged between at least two adjacent pixel units.

[0007] In the OLED display panel provided by the present application, the OLED display panel further comprises an encapsulation layer, the planar layer and the pixel definition layer are arranged in the display area, the planar layer has a first side surface close to the non-display area, the pixel definition layer has a second side surface close to the non-display area, and the encapsulation layer covers the cathode, the first side surface and the second side surface of the display area.

[0008] In the OLED display panel provided by the present application, the OLED display panel further comprises a first metal layer arranged between the substrate and the thin film transistor layer. The thin film transistor layer comprises a plurality of arrayed thin film transistors and a third via hole arranged between the thin film transistors. The third via hole corresponds to the first via hole. The first metal layer comprises a light shielding layer corresponding to the thin film transistors and a first metal wiring layer corresponding to the first via hole. The cathode is electrically connected with the first metal wiring layer through the third via hole.

[0009] In the OLED display panel provided in the application, the thin film transistor layer comprises, in sequence, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a second metal layer arranged on the side of the first metal layer away from the substrate, the second metal layer comprises a source-drain layer connected with the semiconductor layer and a first metal wiring electrode arranged corresponding to the first metal wiring layer, and the first metal wiring electrode electrically connects the cathode and the first metal wiring layer through the third via hole.

[0010] In the OLED display panel provided in the application, the OLED display panel further comprises a third metal layer arranged on the side of the thin film transistor layer away from the substrate, the third metal layer comprises a second metal wiring electrode arranged in the same layer as the anode, the second metal wiring electrode is electrically connected with the first metal wiring electrode, the first via hole and the through second via hole expose at least part of the second metal wiring electrode, and the cathode is connected with the second metal wiring electrode through the first via hole, the second via hole and the second metal wiring electrode.

[0011] The application further provides a manufacturing method of the OLED display panel, comprising the following steps:

[0012] providing a substrate;

[0013] forming a thin film transistor layer on one side of the substrate;

[0014] forming a planar layer on the side of the thin film transistor layer away from the substrate;

[0015] forming a pixel definition layer on the side of the planar layer away from the thin film transistor layer;

[0016] wherein the planar layer is formed with a first via hole, the pixel definition layer is formed with a second via hole and a through hole, and the first via hole and the second via hole are through each other; the OLED display panel further comprises a light emitting device layer, the light emitting device layer comprises, in sequence, an anode, a light emitting layer and a cathode formed on the side of the planar layer away from the thin film transistor layer, the anode is electrically connected with the thin film transistor layer, the light emitting layer is formed in the through hole, and the cathode covers the pixel definition layer, the first via hole, the second via hole and the light emitting layer.

[0017] In the manufacturing method of the OLED display panel provided in the application, the OLED display panel comprises a display area and a non-display area formed at the periphery of the display area, the first via hole and the second via hole are formed between the display area and the non-display area; the display area comprises a plurality of pixel units, the first via hole and the second via hole are formed between at least two adjacent pixel units; the OLED display panel further comprises an encapsulation layer, the planar layer and the pixel definition layer are formed in the display area, the planar layer has a first side surface close to the non-display area, the pixel definition layer has a second side surface close to the non-display area, and the encapsulation layer covers the cathode, the first side surface and the second side surface of the display area.

[0018] In the manufacturing method of the OLED display panel provided in the application, the OLED display panel further comprises a first metal layer formed between the substrate and the thin film transistor layer, the thin film transistor layer comprises a plurality of arrayed thin film transistors and a third via hole formed between the thin film transistors, the third via hole corresponds to the first via hole, the first metal layer comprises a light shielding layer corresponding to the thin film transistor and a first metal wiring layer corresponding to the first via hole, and the cathode is electrically connected with the first metal wiring layer through the third via hole; the thin film transistor layer comprises, in sequence, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a second metal layer on the side of the first metal layer away from the substrate, the second metal layer comprises a source-drain electrode layer connected with the semiconductor layer and a first metal wiring electrode corresponding to the first metal wiring layer, and the first metal wiring electrode electrically connects the cathode with the first metal wiring layer through the third via hole.

[0019] The application also has the following effects: in the light-emitting layer (each pixel unit) of the display area, the pixel definition layer (PDL) and the planar layer (PLN) are respectively provided with through holes (i.e. the first through hole and the second through hole), so that the pixel definition layer and the planar layer on both sides of the through hole effectively cut off the path of water and oxygen transmission between each pixel unit, and the normal use of other pixel units is not affected even if a single pixel package fails, thereby increasing the reliability of the display area (AA) and the service life of the OLED display panel. The third through hole is arranged between the plurality of thin film transistors and the first through hole, and the cathode is electrically connected to the first metal wiring layer (as the VSS ground voltage wiring) arranged corresponding to the first through hole through the third through hole, which can effectively reduce the problem of power voltage drop (IR Drop) of the large-size OLED display panel top-emitting device, thereby making the display more uniform. In addition, the pixel definition layer and the planar layer can not be arranged in the non-display area (NDA), i.e. the encapsulation layer fully covers the non-display area, effectively isolates the external water and oxygen / humidity, thereby increasing the reliability and service life of most devices in the display area. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0021] Figure 1A is an embodiment diagram of the first cross section of the OLED display panel of the application;

[0022] Figure 1B is an embodiment diagram of the second cross section of the OLED display panel of the application;

[0023] Figure 2 is a plane schematic diagram of the OLED display panel of the application;

[0024] Figure 3 is Figure 1A or Figure 1B the cross-sectional structure diagram of the substrate of

[0025] Figure 4 is another embodiment diagram of the OLED display panel of the application;

[0026] Figures 5 to 16 is each cross-sectional structure diagram of the manufacturing method of the OLED display panel of the application; and

[0027] Figure 17 is a block flow chart of a manufacturing method of the OLED display panel of the present application. DETAILED DESCRIPTION

[0028] Reference to "embodiments" in the detailed description means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the same terminology in various places in the specification does not necessarily refer to the same embodiment, but can refer to different embodiments. Those of ordinary skill in the art will appreciate that the embodiments described in the present application can have other embodiments that are apparent to those of ordinary skill in the art in light of the technical solutions disclosed in the embodiments of the present application.

[0029] Please refer to Figure 1A and Figure 1B , which are the first and second cross-sectional views of the OLED display panel of the present application. The present application provides an OLED display panel 100 comprising a substrate 101, a thin film transistor layer (not labeled), a planar layer 150 and a pixel definition layer 160. The thin film transistor layer is arranged on one side of the substrate 101. The planar layer 150 is arranged on the side of the thin film transistor layer away from the substrate 101. The pixel definition layer 160 is arranged on the side of the planar layer 150 away from the thin film transistor layer. The planar layer 150 is provided with a first via hole 180, the pixel definition layer 160 is provided with a second via hole 182 and a through hole 184, and the first via hole 180 and the second via hole 182 are in communication.

[0030] The OLED display panel 100 further comprises a light emitting device layer 170, which comprises an anode 172, a light emitting layer 174 and a cathode 176 arranged in sequence on the side of the planar layer 150 away from the thin film transistor layer, the anode 172 is electrically connected to the thin film transistor layer, the light emitting layer 174 is arranged in the through hole 184, and the cathode 176 covers the pixel definition layer 160, the first via hole 180, the second via hole 182 and the light emitting layer 174. As shown in Figure 1A and Figure 1B In the embodiments shown in

[0031] Please refer to Figure 2As shown, it is a plan view of the OLED display panel of the present application. The display area AA includes a plurality of pixel units P, each pixel unit P including at least three sub-pixels, such as a red sub-pixel, a green sub-pixel and a blue sub-pixel. In an embodiment, the first via 180 and the second via 182 are arranged between at least two adjacent pixel units P. In the embodiment as shown, Figure 1A In the embodiment as shown, at least one first via 180 and second via 182 are arranged between two adjacent pixel units P. However, in the embodiment as shown, Figure 1B In the embodiment as shown, three first vias 180 and second vias 182 are arranged between two adjacent pixel units P to increase the effect of isolating the pixel units P from the external water and oxygen.

[0032] That is, the number of first vias 180 and second vias 182 near the non-display area NDA can be three (but not limited to), which is greater than the number of first vias 180 and second vias 182 arranged in the display area AA. However, in other different embodiments, the number of first vias 180 and second vias 182 near the non-display area NDA can be equal to the number arranged in the display area AA, which can be changed as needed. In the embodiments as shown, Figure 1A and Figure 2 As shown, the path of water and oxygen / humidity propagation is effectively isolated and cut off by the first via 180 and the second via 182, so that even if a single pixel unit P fails, it does not affect the normal use of other pixel units P, thereby increasing the reliability of the majority of pixel display in the display area AA and the service life of the OLED display panel 100.

[0033] As shown, Figure 1A and Figure 1B The OLED display panel 100 further includes an encapsulation layer 190, the flat layer 150 and the pixel definition layer 160 are arranged in the display area AA, the flat layer 150 has a first side 152 near the non-display area NDA, and the pixel definition layer 160 has a second side 166 near the non-display area NDA. The encapsulation layer 190 covers the cathode 176, the first side 152, and the second side 166 of the display area AA. Specifically, in the non-display area NDA, the pixel definition layer 160 and the flat layer 150 are not included, that is, the encapsulation layer 190 is fully covered in the non-display area NDA, effectively isolating the external water and oxygen / humidity from entering, thereby increasing the reliability of the majority of devices in the display area AA and the service life.

[0034] As shown, Figure 1A and Figure 1BThe encapsulation layer 190 shown further comprises a first inorganic encapsulation layer 192, an organic encapsulation layer 194, and a second inorganic encapsulation layer 196. However, in other different embodiments, the encapsulation layer 190 further comprises more than three layers or other different combinations, which are not limited. The materials of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 are preferably silicon oxide (SiO), and the material of the organic encapsulation layer 194 is preferably silicon nitride (SiN) or silicon oxynitride (SiNxOy).

[0035] For reference Figure 3 As shown, the substrate 101 of the embodiment can be a rigid layer or a flexible layer. When the substrate 101 is a rigid layer, it can be a simple glass, a PE resin or other suitable materials. When the substrate 101 is a flexible layer, a single layer or a multi-layer stack structure of polyimide (PI) and barrier layer (Barrier layer) can be provided on the simple glass, which is not limited. Specifically, as shown in FIG. 1B, the substrate 101 comprises a substrate 102 (simple glass), an amorphous silicon layer 103 (as a sacrificial layer), a first photoresist layer 104 (polyimide PI), a first barrier layer 105 (material such as silicon oxide), a second photoresist layer 106 (polyimide PI), a second barrier layer 107 (material such as SiO), or a combination thereof. Figure 3

[0036] The OLED display panel 100 further comprises a first metal layer 110 provided between the substrate 101 and the thin film transistor layer, the thin film transistor layer comprises a plurality of arrayed thin film transistors TFT and a third via hole 186 provided between the thin film transistors TFT, the third via hole 186 corresponds to the first via hole 180, the first metal layer 110 comprises a light shielding layer 111 corresponding to the thin film transistors TFT and a first metal trace layer 112 corresponding to the first via hole 180, and the cathode 176 is electrically connected to the first metal trace layer 112 through the third via hole 186.

[0037] Specifically, the thin film transistor layer comprises, in sequence from the side of the first metal layer 110 away from the substrate 101, a buffer layer 120, a semiconductor layer (IGZO / IGTO) 132, a gate insulating layer 134, a gate layer 136, an interlayer dielectric layer (ILD) 130, and a second metal layer 135. The second metal layer 135 comprises a source-drain layer 138 connected to the semiconductor layer 132 and a first metal trace electrode 139 corresponding to the first metal trace layer 112, and the first metal trace electrode 139 electrically connects the cathode 176 to the first metal trace layer 112 through the third via hole 186.

[0038] ​The OLED display panel 100 further comprises a third metal layer 178 arranged on the side of the thin film transistor layer away from the substrate 101, the third metal layer 178 comprises the anode 172 and a second metal trace electrode 177 arranged in the same layer as the anode 172, the second metal trace electrode 177 is electrically connected with the first metal trace electrode 139, the first via hole 180 and the through second via hole 182 expose at least part of the second metal trace electrode 177, and the cathode 176 is connected with the second metal trace electrode 177 through the first via hole 180 and the second via hole 182.

[0039] Therefore, in the embodiment, by arranging the third via hole 186 between the plurality of thin film transistors TFT, the cathode 176 is electrically connected with the first metal trace layer 112 (as VSS ground voltage trace) through the third via hole 186, which can effectively reduce the problem of power voltage drop (IR Drop) of the top emission device of the large-size OLED display panel 100, so as to make the display more uniform.

[0040] Please refer to Figure 4 As shown in the figure, it is another embodiment of the OLED display panel of the present application. In the embodiment, in order to better improve the effect of inkjet printing, the pixel definition layer 160 can be arranged as two layers, which comprises a hydrophilic organic layer 162 and a hydrophobic layer 164 deposited on the hydrophilic organic layer 162. Specifically, the bottom layer is the hydrophilic organic layer 162, so that the ink can spread to the maximum extent, and the hydrophobic layer 164 on it can make the ink not remain on the surface. The thickness of the hydrophilic organic layer 162 is greater than or equal to the thickness of the hydrophobic layer 164, and in a preferred embodiment, the thickness of the hydrophilic organic layer 162 is The thickness of the hydrophobic layer 164 is

[0041] Please refer to Figures 5 to 17 As shown in the figure, it is a cross-sectional schematic diagram and flow block diagram of the manufacturing method of the OLED display panel of the present application. The present application further provides a manufacturing method of a flexible OLED display panel 100, the manufacturing method comprises the following steps:

[0042] Step S10, providing a substrate 101; step S20, forming a thin film transistor layer (not labeled) on one side of the substrate 101. Step S30, forming a planar layer 150 on the side of the thin film transistor layer away from the substrate 101. Step S40, forming a pixel definition layer 160 on the side of the planar layer 150 away from the thin film transistor layer. The planar layer 150 is formed with a first via 180, the pixel definition layer 160 is formed with a second via 182 and a through hole 184, the first via 180 and the second via 182 are through. The OLED display panel 100 further comprises a light emitting device layer 170, the light emitting device layer 170 comprises an anode 172, a light emitting layer 174 and a cathode 176 formed on the side of the planar layer 150 away from the thin film transistor layer in sequence, the anode 172 and the thin film transistor layer are electrically connected, the light emitting layer 174 is formed in the through hole 184, and the cathode 176 covers the pixel definition layer 160, the first via 180, the second via 182 and the light emitting layer 174.

[0043] As Figure 1A and Figure 1B shown, the OLED display panel 100 includes a display area AA and a non-display area NDA formed on the periphery of the display area AA, and the first via 180 and the second via 182 are formed between the display area AA and the non-display area NDA. The display area AA includes a plurality of pixel units P, and the first via 180 and the second via 182 are formed between at least two adjacent pixel units P. Each pixel unit P includes at least three sub-pixels, such as red, green and blue sub-pixels. The number of through first vias 180 and second vias 182 near the non-display area NDA can be 3 (but not limited to), which is greater than the number of first vias 180 and second vias 182 arranged in the display area AA. However, in other different embodiments, the number of first vias 180 and second vias 182 near the non-display area NDA can also be equal to the number arranged in the display area AA, which can be changed as needed. Since the path of water and oxygen / humidity propagation is effectively cut off by the first via 180 and the second via 182, even if a single pixel unit P is encapsulated, it does not affect the normal use of other pixel units P, thereby increasing the reliability of most pixel display in the display area AA and the service life of the OLED display panel 100.

[0044] In step S10 of providing the substrate 101, as Figure 3As shown, the substrate 101 can be a rigid layer or a flexible layer. When the substrate 101 is a rigid layer, it can be made of plain glass, PE resin, or other suitable materials. When the substrate 101 is a flexible layer, several single-layer or multi-layer stacked structures of polyimide (PI) and barrier layers can be formed on the plain glass, without limitation. Specifically, as... Figure 3 As shown, the substrate 101 further includes a substrate 102 (plain glass), an amorphous silicon layer 103 (Asi as a sacrificial layer) deposited on the substrate 102 by chemical vapor deposition (CVD), a first photoresist layer 104 (polyimide PI, formed after drying by VCD), a first barrier layer 105 (material such as silicon oxide) deposited by VCD, a second photoresist layer 106 (polyimide PI, formed after drying by VCD), and a second barrier layer (material such as silicon oxide) deposited by VCD. However, in other different embodiments, the substrate 101 may also include materials such as... Figure 3 The multi-layered structure or combination thereof in the embodiments is not limited.

[0045] In step S20, where a thin-film transistor layer is formed on one side of the substrate 101, as follows: Figures 5 to 9 In the OLED display panel 100, a first metal layer 110 is further formed between the substrate 101 and the thin-film transistor layer. The thin-film transistor layer includes a plurality of arrayed thin-film transistor TFTs and a third via 186 formed between the thin-film transistor TFTs. The third via 186 is formed corresponding to the first via 180. The first metal layer 110 includes a light-shielding layer 111 formed corresponding to the thin-film transistor TFTs and a first metal wiring layer 112 formed corresponding to the first via 180. The cathode 176 is electrically connected to the first metal wiring layer 112 through the third via 186.

[0046] In such Figures 5 to 9 In the illustrated embodiment, the thin-film transistor layer includes a buffer layer 120, a semiconductor layer 132, a gate insulating layer 134, a gate layer 136, an interlayer dielectric layer 130, and a second metal layer 135, sequentially arranged on the side of the first metal layer 110 away from the substrate 101. The second metal layer 135 includes a source / drain layer 138 connected to the semiconductor layer 132 and a first metal trace electrode 139 formed corresponding to the first metal trace layer 112. The first metal trace electrode 139 electrically connects the cathode 176 to the first metal trace layer 112 through the third via 186.

[0047] Specifically, the material of the first metal layer 110, such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), etc., single layer, multi-layer combination or alloy thereof, is deposited on the substrate 101 by physical vapor deposition (PVD) as a light shielding layer 111 (LS layer), and then photoresist coating, exposure, development, etching, film stripping and other operations are performed to form a cross-sectional view as shown in Figure 5 The first metal layer 110 can be used to shield light from the outside and prevent leakage current from being generated in the thin film transistor layer. In the embodiment as shown in Figure 5 A buffer layer 120 is further deposited by CVD, which can be silicon nitride, silicon oxide or a combination of the two, to form a cross-sectional view as shown in Figure 6

[0048] In the embodiment as shown in Figure 7 A semiconductor material, such as indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), etc., single layer, multi-layer combination or alloy thereof, is deposited by PVD to form the semiconductor layer 132, and then photoresist coating, exposure, development, etching, film stripping and other operations are performed to form a cross-sectional view as shown in Figure 8 In the embodiment as shown in Figure 8 The gate insulating layer 134 is further deposited by CVD, which can be silicon nitride, silicon oxide or a combination of the two. The material of the gate 136, such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), etc., single layer, multi-layer combination or alloy thereof, is deposited by PVD, and then photoresist coating, exposure, development, etching, film stripping and other operations are performed to form a cross-sectional view as shown in Figure 8 It should be noted that the above etching step is to first etch the pattern of the gate 136 by wet etching process, and then etch the pattern of the gate insulating layer 134 by dry etching process, and then induce conductive by helium (He) to form an embodiment as shown in Figure 8

[0049] In the embodiment as shown in Figure 8 The dielectric layer 130 (ILD) is further deposited by CVD, which can be silicon nitride, silicon oxide or a combination of the two, and then photoresist coating, exposure, development, etching, film stripping and other operations are performed to form a cross-sectional view as shown in Figure 9 In particular, the mask used to make the dielectric layer 130 is a half-tone mask, which is used to etch the dielectric layer 130 and the buffer layer 120 simultaneously. In the embodiment as shown in Figure 9 ​​In the embodiment shown, the material of the second metal layer 135 is single layer, multi-layer combination or alloy thereof of copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al) and the like, and is deposited by PVD, and then is subjected to photoresist coating, exposure, development, etching, stripping and the like to form a cross-sectional view as shown in Figure 10 The cross-sectional view is shown in

[0050] It should be noted that the thin film transistor layer includes a plurality of arrayed thin film transistors TFT and third vias 186 formed between the thin film transistors TFT. The third vias 186 are formed corresponding to the first vias 180, and the first metal layer 110 includes light shielding layers 111 formed corresponding to the thin film transistors TFT and first metal trace layers 112 formed corresponding to the first vias 180. The cathode 176 is electrically connected to the first metal trace layers 112 through the third vias 186. In addition, the second metal layer 135 includes source / drain layers 138 connected to the semiconductor layers 132 and first metal trace electrodes 139 formed corresponding to the first metal trace layers 112. The first metal trace electrodes 139 are made of the same material as the source / drain layers 138, for example, and the first metal trace electrodes 139 electrically connect the cathode 176 to the first metal trace layers 112 through the third vias 186.

[0051] In step S30 of forming a planarization layer 150 on the side of the thin film transistor layer away from the substrate 101, the planarization layer 150 is formed by CVD deposition, as shown in Figure 10 The passivation layer 140 is formed by CVD deposition, and its material can be silicon nitride, silicon oxide or a combination of the two, and is formed by photoresist coating, exposure, development, etching, stripping and the like, as shown in Figure 11 The cross-sectional view is shown in Figure 11 In the embodiment shown, the planarization layer 150 is coated by a coating machine, and is subjected to exposure, development, baking and the like to form a cross-sectional view as shown in Figure 12 The cross-sectional view is shown in

[0052] The OLED display panel 100 further includes a third metal layer 178 formed on the side of the thin-film transistor layer away from the substrate 101. The third metal layer 178 includes a second metal trace electrode 177 formed in the same layer as the anode 172. The second metal trace electrode 177 is made of the same material and layer as the anode 172 and is electrically connected to the first metal trace electrode 139. The first via 180 and the through-hole second via 182 expose at least a portion of the second metal trace electrode 177. The cathode 176 is connected to the second metal trace electrode 177 through the first via 180 and the second via 182. Therefore, in this embodiment, by providing a third via 186 between multiple thin-film transistors (TFTs), and electrically connecting the cathode 176 to the first metal trace layer 112 (as a VSS ground voltage trace) through the third via 186, the problem of power supply voltage drop (IR Drop) of the top emitter of the large-size OLED display panel 100 can be effectively reduced, thereby making the display more uniform.

[0053] In such Figure 12 In the illustrated embodiment, the anode 172 (such as a double-layer sandwich structure of ITO / Ag / ITO, IZO / Ag / IZO or other transparent conductive layers and silver (Ag)) is further continuously deposited using PVD as another electrode trace for the pixel electrode, auxiliary electrode, and / or touch electrode of the OLED display panel 100. Then, photoresist coating, exposure, development, etching, and stripping processes are performed to form a structure as shown in the figure. Figure 13 The cross-sectional view shown.

[0054] In step S40, when forming the pixel definition layer 160 on the side of the planarization layer 150 away from the thin-film transistor layer, as follows: Figure 13 As shown, the pixel definition layer 160 (PDL / BANK) is coated using a coating machine, and then exposed, developed, and baked to form a layer as shown. Figure 14 The cross-sectional view shown is illustrated. Specifically, the planarization layer 150 and the pixel definition layer 160 are formed in the display area AA. The planarization layer 150 has a first side surface 152 near the non-display area NDA, and the pixel definition layer 160 has a second side surface 166 near the non-display area NDA. The encapsulation layer 190 covers the cathode 176, the first side surface 152, and the second side surface 166 of the display area AA. Specifically, the non-display area NDA does not include the pixel definition layer 160 and the planarization layer 150; that is, the encapsulation layer 190 completely covers the non-display area NDA, effectively isolating it from external water / oxygen / humidity intrusion, thereby increasing the reliability and lifespan of most devices in the display area AA.

[0055] In suchFigure 14 In the illustrated embodiment, the materials of the hole injection layer, the hole transport layer, the light emitting layer, the electron injection layer, and the electron injection layer are further injected by using the inkjet printing method and baked by using the VCD baking method to form the light emitting layer 174 as shown in Figure 15 In particular, the materials of the hole injection layer, the hole transport layer, the light emitting layer, the electron injection layer, and the electron injection layer in the light emitting layer 174 in the present embodiment are preferably injected by using the inkjet printing method. However, in other different embodiments, the light emitting layer 174 can include a combination of the above-mentioned 5-layer structure or other multi-layer structure, and is not limited. As shown in Figure 15 In the illustrated embodiment, the cathode 176 is further evaporated by using the evaporation method (as shown in Figure 16 Due to the design of the second metal trace electrode 177, the cathode 176 has great designability, which can effectively reduce the problem of power supply voltage drop (IR Drop) of the top emission device of the large-size OLED display panel 100, thereby making the display more uniform.

[0056] The OLED display panel 100 further includes an encapsulation layer 190, the planar layer 150 and the pixel definition layer 160 are formed in the display area AA, the planar layer 150 has a first side 152 close to the non-display area NDA, and the pixel definition layer 160 has a second side 166 close to the non-display area NDA. The encapsulation layer 190 covers the cathode 176, the first side 152, and the second side 166 of the display area AA. Specifically, in the non-display area NDA, the pixel definition layer 160 and the planar layer 150 are not included, i.e., the non-display area NDA is fully covered by the encapsulation layer 190, which effectively prevents the invasion of external water / oxygen / humidity, thereby increasing the reliability and service life of most devices in the display area AA.

[0057] The encapsulation layer 190 further includes a first inorganic encapsulation layer 192, an organic encapsulation layer 194 (TEF), and a second inorganic encapsulation layer 196. However, in other different embodiments, the encapsulation layer 190 further includes more than three layers or other different combinations, and is not limited. The materials of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 are preferably silicon oxide (SiO), and the material of the organic encapsulation layer 194 is preferably silicon nitride (SiN) or silicon oxynitride (SiNxOy).

[0058] In the step of preparing the encapsulation layer 190 on the cathode 176, a first inorganic encapsulation layer 192 is deposited by CVD, an organic encapsulation layer 194 is inkjet-printed on the first inorganic encapsulation layer 192, and a second inorganic encapsulation layer 196 is deposited on the organic encapsulation layer 194. However, in other different embodiments, the encapsulation layer 190 can also include more than three layers or other different combinations, which are not limited. The materials of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 are preferably silicon oxide, and the material of the organic encapsulation layer 194 is preferably silicon nitride or silicon oxynitride, as shown in Figure 16

[0059] It should be noted that, in order to better improve the effect of inkjet printing, the pixel definition layer 160 can be provided as two layers (as shown in Figure 4 The pixel definition layer 160 includes a hydrophilic organic layer 162 and a hydrophobic layer 164 deposited on the hydrophilic organic layer 162. Specifically, the bottom layer is the hydrophilic organic layer 162, so that the ink can spread to the maximum extent, and the hydrophobic layer 164 on it can prevent the ink from remaining on the surface. The thickness of the hydrophilic organic layer 162 is greater than or equal to the thickness of the hydrophobic layer 164. In a preferred embodiment, the thickness of the hydrophilic organic layer 162 is The thickness of the hydrophobic layer 164 is

[0060] In the light-emitting layer 174 (each pixel unit P) of the display area AA, through-holes (i.e., first through-holes 180 and second through-holes 182) are respectively formed in the pixel definition layer 160 and the planarization layer 150, so that the pixel definition layer 160 and the planarization layer 150 on both sides of the through-holes effectively block the path of water and oxygen transmission between each pixel unit P, that is, even if a single pixel unit P fails to be encapsulated, it will not affect the normal use of other pixel units, thereby increasing the reliability of the display of most pixel units P in the display area (AA) and the service life of the OLED display panel 100.

[0061] A third through-hole 186 is arranged between a plurality of thin film transistors TFT corresponding to the first through-hole 180, and the cathode 176 is electrically connected to the first metal wiring layer 112 (as a VSS ground voltage wiring) arranged corresponding to the first through-hole 180 through the third through-hole 186, which can effectively reduce the problem of power voltage drop (IR Drop) of the top-emitting device of a large-size OLED display panel 100, thereby making the display more uniform. In addition, the pixel definition layer 160 and the planarization layer 150 can also not be arranged in the non-display area NDA, that is, the non-display area NDA is fully covered by the encapsulation layer, which effectively isolates the invasion of external water and oxygen / humidity, thereby increasing the reliability and service life of most devices in the display area AA.​

[0062] To the extent necessary to the apprehension of the descriptions, examples, or further embodiments, terminology can be used that shall include, where applicable: artificial intelligence, machine learning, deep learning, neural networks, artificial neural networks, recurrent neural networks, convolutional neural networks, generative adversarial networks, reinforcement learning, supervised learning, unsupervised learning, semi-supervised learning, self-supervised learning, transfer learning, federated learning, federated reinforcement learning, federated transfer learning, federated self-supervised learning, federated unsupervised learning, federated semi-supervised learning, federated supervised learning, federated learning of federated models, federated learning of heterogeneous federated models, federated learning of heterogeneous federated models with different learning

Claims

1. An OLED display panel, characterized in that, include: Substrate; A thin-film transistor layer is disposed on one side of the substrate; A planarization layer is disposed on the side of the thin-film transistor layer away from the substrate; A pixel definition layer is disposed on the side of the planarization layer away from the thin-film transistor layer; The planarization layer has a first via, and the pixel definition layer has a second via and a through-hole, with the first via and the second via communicating with each other. The OLED display panel also includes a light-emitting device layer, which includes an anode, a light-emitting layer, and a cathode sequentially disposed on the side of the planarization layer away from the thin-film transistor layer. The anode is electrically connected to the thin-film transistor layer, the light-emitting layer is disposed in the through-hole, and the cathode covers the pixel definition layer, the first via, the second via, and the light-emitting layer. A first metal layer is disposed between the substrate and the thin-film transistor layer, and the first metal layer includes a first metal trace layer disposed corresponding to the first via. The OLED display panel includes a display area, which includes a plurality of pixel units, and the first via and the second via are disposed between at least two adjacent pixel units; The thin-film transistor layer includes a plurality of thin-film transistors arranged in an array and a third via disposed between the thin-film transistors, wherein the third via is disposed corresponding to the first via. The cathode covers the inner walls of the first and second vias and is electrically connected to the first metal trace layer through the third via.

2. The OLED display panel according to claim 1, characterized in that, The OLED display panel also includes a non-display area disposed around the display area, and the first via and the second via are disposed between the display area and the non-display area.

3. The OLED display panel according to claim 2, characterized in that, The OLED display panel further includes an encapsulation layer, the planarization layer and the pixel definition layer are disposed in the display area, the planarization layer has a first side near the non-display area, the pixel definition layer has a second side near the non-display area, and the encapsulation layer covers the cathode, the first side and the second side of the display area.

4. The OLED display panel according to claim 1, characterized in that, The first metal layer also includes a light-shielding layer disposed corresponding to the thin-film transistor.

5. The OLED display panel according to claim 1, characterized in that, The thin-film transistor layer includes a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a second metal layer, which are sequentially disposed on the side of the first metal layer away from the substrate. The second metal layer includes a source / drain layer connected to the semiconductor layer and a first metal trace electrode disposed corresponding to the first metal trace layer. The first metal trace electrode electrically connects the cathode to the first metal trace layer through the third via.

6. The OLED display panel according to claim 5, characterized in that, The OLED display panel further includes a third metal layer disposed on the side of the thin film transistor layer away from the substrate. The third metal layer includes the anode and a second metal trace electrode disposed on the same layer as the anode. The second metal trace electrode is electrically connected to the first metal trace electrode. The first via and the through-hole of the second via expose at least a portion of the second metal trace electrode. The cathode is connected to the second metal trace electrode through the first via and the second via.

7. A method for manufacturing an OLED display panel, characterized in that, Includes the following steps: Provide substrate; A thin-film transistor layer is formed on one side of the substrate; A planarization layer is formed on the side of the thin-film transistor layer away from the substrate; A pixel definition layer is formed on the side of the planar layer away from the thin-film transistor layer; The OLED display panel includes a first via formed on the planarization layer, a second via and a through-hole formed on the pixel definition layer, wherein the first via and the second via are interconnected; the OLED display panel further includes a light-emitting device layer, which includes an anode, a light-emitting layer and a cathode formed sequentially on the side of the planarization layer away from the thin-film transistor layer, wherein the anode and the thin-film transistor layer are electrically connected, the light-emitting layer is formed in the through-hole, and the cathode covers the pixel definition layer, the first via, the second via and the light-emitting layer; The OLED display panel includes a display area, which includes a plurality of pixel units, and the first via and the second via are formed between at least two adjacent pixel units; The OLED display panel further includes a first metal layer forming between the substrate and the thin-film transistor layer. The thin-film transistor layer includes a plurality of arrayed thin-film transistors and a third via formed between the thin-film transistors. The third via is formed corresponding to the first via. The first metal layer includes a first metal trace layer formed corresponding to the first via. The cathode is electrically connected to the first metal trace layer through the third via.

8. The method for manufacturing an OLED display panel according to claim 7, characterized in that, The OLED display panel further includes a non-display area formed around the display area, and the first via and the second via are formed between the display area and the non-display area; the OLED display panel further includes an encapsulation layer, the planarization layer and the pixel definition layer are formed in the display area, the planarization layer has a first side surface near the non-display area, the pixel definition layer has a second side surface near the non-display area, and the encapsulation layer covers the cathode, the first side surface and the second side surface of the display area.

9. The method for manufacturing an OLED display panel according to claim 7, characterized in that, The first metal layer includes a light-shielding layer formed corresponding to the thin-film transistor; the thin-film transistor layer includes a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a second metal layer arranged sequentially on the side of the first metal layer away from the substrate; the second metal layer includes a source / drain layer connected to the semiconductor layer and a first metal trace electrode formed corresponding to the first metal trace layer; the first metal trace electrode electrically connects the cathode to the first metal trace layer through the third via.

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