Electronic device, semiconductor device and method for manufacturing the same

Abstract

The present application relates to an electronic device, a semiconductor device and a preparation method thereof, comprising: a substrate having a first conductivity type; a first buried layer having a second conductivity type, formed in the substrate, the second conductivity type being opposite to the first conductivity type; a second buried layer having a second conductivity type, formed on the upper surface of the first buried layer, the doping concentration of the second buried layer being lower than the doping concentration of the first buried layer; a second conductivity type well region, formed on the second buried layer, the bottom of which is in contact with the second buried layer; a device layer, formed in an area surrounded by the second buried layer and the second conductivity type well region, the device layer comprising a first conductivity type well region, the first conductivity type well region being formed on the upper surface of the second buried layer near the second conductivity type well region. The breakdown voltage of a planar junction formed by the second conductivity type well region and the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electronic device, a semiconductor device and a method for manufacturing the same. Background Art

[0002] The typical method for preparing semiconductor devices is divided into two steps: the first step is to form an isolation island structure on a P-type substrate through DN (Deep N well) and BN (Buried N layer). The second step is to form a device layer in the isolation island structure. The above structure needs to ensure that the substrate current of the P-type substrate is small enough, and the breakdown voltage of the DP / BN planar junction in the DP (Deep P well) in contact with BN in the device layer is high enough.

[0003] The higher the doping concentration of BN, the lower the substrate current of the P-type substrate. However, the breakdown voltage of the DP / BN planar junction decreases with the increase of the doping concentration of BN. Therefore, while keeping the breakdown voltage of the DP / BN planar junction unchanged, the substrate current of the P-type substrate cannot be reduced by increasing the doping concentration of BN in the substrate. Summary of the invention

[0004] Based on this, it is necessary to provide an electronic device, a semiconductor device and a method for preparing the same to address the problem in the prior art that the substrate current of a P-type substrate cannot be reduced by increasing the doping concentration of BN in the substrate while maintaining the breakdown voltage of the DP / BN planar junction.

[0005] In order to achieve the above object, on the one hand, the present invention provides a semiconductor device, comprising:

[0006] a substrate having a first conductivity type;

[0007] A first buried layer having a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type;

[0008] A second buried layer, having a second conductivity type, is formed on an upper surface of the first buried layer, and the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer;

[0009] A second conductive type well region is formed on the second buried layer, and a bottom of the second conductive type well region is in contact with the second buried layer;

[0010] The device layer is formed in the area surrounded by the second buried layer and the second conductive type well region, and the device layer includes a first conductive type well region formed on the upper surface of the second buried layer close to the second conductive type well region.

[0011] In one embodiment, the semiconductor device further comprises:

[0012] The first epitaxial layer is formed on the upper surface of the substrate. A second buried layer is formed in the first epitaxial layer. The upper surface of the second buried layer is flush with the upper surface of the first epitaxial layer.

[0013] In one embodiment, the semiconductor device further comprises:

[0014] A second epitaxial layer is formed on the upper surface of the first epitaxial layer, wherein a second conductivity type well region and a device layer are formed in the second epitaxial layer;

[0015] A first shallowly doped region has a second conductivity type and is formed in a well region of the second conductivity type, wherein a lower surface of the first shallowly doped region is higher than a lower surface of the well region of the second conductivity type;

[0016] A first heavily doped region, having a second conductivity type, is formed in the first lightly doped region, and a lower surface of the first heavily doped region is higher than a lower surface of the first lightly doped region;

[0017] A second shallowly doped region has a first conductivity type and is formed in the first conductivity type well region, wherein a lower surface of the second shallowly doped region is higher than a lower surface of the first conductivity type well region;

[0018] A second heavily doped region, having the first conductivity type, is formed in the second lightly doped region, and a lower surface of the second heavily doped region is higher than a lower surface of the second lightly doped region;

[0019] A first shallow trench isolation structure is formed on the upper surface layer of the second epitaxial layer and is located between the first conductive type well region and the second conductive type well region. The lower surface of the first shallow trench isolation structure is higher than the lower surfaces of the first shallowly doped region and the second shallowly doped region, and is lower than the lower surfaces of the first heavily doped region and the second heavily doped region.

[0020] In one embodiment, the semiconductor device further comprises:

[0021] A substrate lead-out region, having a first conductivity type and formed on the substrate, the substrate lead-out region being connected to the substrate and used for leading out the substrate;

[0022] A third shallowly doped region, having the first conductivity type, is formed in the substrate lead-out region, and a lower surface of the third shallowly doped region is higher than a lower surface of the substrate lead-out region;

[0023] A third heavily doped region, having the first conductivity type, is formed in the third shallowly doped region, and a lower surface of the third heavily doped region is higher than a lower surface of the third shallowly doped region;

[0024] A second shallow trench isolation structure is formed on the upper surface of the second epitaxial layer and is located between the substrate lead-out region and the second conductive type well region. The lower surface of the second shallow trench isolation structure is higher than the lower surfaces of the first shallowly doped region and the third shallowly doped region, and is lower than the lower surfaces of the first heavily doped region and the third heavily doped region.

[0025] In one embodiment, the depths of the first buried layer and the second buried layer are both greater than or equal to 0.04 micrometers and less than or equal to 0.06 micrometers, and the doping concentration of the first buried layer is greater than or equal to 1*10 14 cm -3 and less than or equal to 1*10 15 cm -3 , the doping concentration of the second buried layer is greater than or equal to 1*10 13 cm -3 and less than or equal to 1*10 14 cm -3 .

[0026] An electronic device comprises any one of the semiconductor devices described above.

[0027] In the above semiconductor device and electronic device, a first buried layer of a second conductive type is formed in a substrate of a first conductive type, a second buried layer of a second conductive type is formed on the upper surface of the first buried layer, and the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer, a well region of a second conductive type is formed on the second buried layer, and the bottom of the well region of the second conductive type is in contact with the second buried layer; a device layer is formed in an area surrounded by the second buried layer and the well region of the second conductive type, and the device layer includes a well region of a first conductive type, and the well region of the first conductive type is formed on the upper surface of the second buried layer near the well region of the second conductive type. Compared with a semiconductor device in which a second buried layer is directly formed in a substrate, the doping concentration of the first buried layer in the semiconductor device of the present application is higher than the doping concentration of the second buried layer, the substrate current of the semiconductor device is lower, and the breakdown voltage of the planar junction formed by the well region of the first conductive type and the second buried layer on the upper surface of the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced.

[0028] A method for preparing a semiconductor device, comprising:

[0029] providing a substrate of a first conductivity type;

[0030] forming a first buried layer of a second conductivity type in the substrate, the second conductivity type being opposite to the first conductivity type;

[0031] forming a second buried layer of a second conductivity type on the upper surface of the first buried layer, wherein the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer;

[0032] A second conductive type well region and a device layer are formed on the second buried layer, the bottom of the second conductive type well region is in contact with the second buried layer, the device layer is formed in the area surrounded by the second buried layer and the second conductive type well region, the device layer includes a first conductive type well region, and the first conductive type well region is formed on the upper surface of the second buried layer close to the second conductive type well region.

[0033] In one embodiment, the step of forming a second buried layer of the second conductivity type on the upper surface of the first buried layer comprises:

[0034] forming a first epitaxial layer on the upper surface of the substrate;

[0035] Ions of the second conductivity type are implanted to form a second buried layer in the first epitaxial layer, wherein the upper surface of the second buried layer is flush with the upper surface of the first epitaxial layer.

[0036] In one embodiment, the step of forming a second conductivity type well region and a device layer on the second buried layer comprises:

[0037] forming a second epitaxial layer on an upper surface of the first epitaxial layer;

[0038] forming a second conductivity type well region in the second epitaxial layer;

[0039] A device layer is formed in a region surrounded by the second conductivity type well region and the second buried layer.

[0040] In one embodiment, the method for preparing a semiconductor device further includes:

[0041] A substrate lead-out region of a first conductivity type is formed on the substrate, and the substrate lead-out region is electrically connected to the substrate for leading out the substrate.

[0042] The method for preparing the semiconductor device comprises the following steps: forming a first buried layer having a second conductivity type in a substrate of a first conductivity type, wherein the second conductivity type is opposite to the first conductivity type; forming a second buried layer of the second conductivity type on the upper surface of the first buried layer, wherein the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer; forming a second conductivity type well region and a device layer on the second buried layer, wherein the bottom of the second conductivity type well region contacts the second buried layer, and the device layer is formed in the region surrounded by the second buried layer and the second conductivity type well region, wherein the device layer comprises a first conductivity type well region, and the first conductivity type well region is formed on the upper surface of the second buried layer near the second conductivity type well region. Compared with directly forming the second buried layer in the substrate, the doping concentration of the first buried layer in the semiconductor device of the present application is higher than the doping concentration of the second buried layer, the substrate current of the semiconductor device is lower, and the breakdown voltage of the planar junction formed by the first conductivity type well region and the second buried layer on the upper surface of the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a schematic flow chart of a method for preparing a semiconductor device in an embodiment;

[0045] Figure 2 is a cross-sectional schematic diagram of a semiconductor device after a first buried layer is formed in one embodiment;

[0046] Figure 3 is a cross-sectional schematic diagram of a semiconductor device after a second buried layer is formed in one embodiment;

[0047] Figure 4 is a schematic cross-sectional view of a semiconductor device after a device layer is formed in one embodiment;

[0048] Figure 5 FIG. 4 is a schematic cross-sectional view of a semiconductor device in an embodiment. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0055] The typical method for preparing a semiconductor device is divided into the following steps: The first step is to implant a buried layer: an N-type buried layer is formed by implanting on a P-type substrate, and the upper surface of the N-layer buried layer is flush with the upper surface of the substrate. The second step is to form an epitaxial layer: an epitaxial layer is generated on the upper surface of the substrate. The third step is to form an N-type well region: an N-type well region whose bottom is in contact with the N-type buried layer is formed in the epitaxial layer on the N-type buried layer. The fourth step is to form a device layer: a device layer is formed in the epitaxial layer in the area surrounded by the N-type well region and the N-type buried layer, and the device layer includes a deep P-well region DP formed on the upper surface of the N-type buried layer near the N-type well region. The fourth step is to form a substrate lead-out region: a substrate lead-out region electrically connected to the substrate is formed on the P-type substrate, and is used to lead the substrate out to the surface of the semiconductor device. The substrate current of the P-type substrate is related to the doping concentration of the N-type buried layer, and decreases with the increase of the doping concentration. However, the increase of the doping concentration of the N-type buried layer will reduce the breakdown voltage of the DP / BN planar junction formed by the deep P-well region DP and the N-type buried layer BN. Therefore, without changing the breakdown voltage of the planar junction DP / BN, it is impossible to reduce the substrate current of the P-type substrate by increasing the doping concentration of the N-type buried layer, thereby reducing the influence of the substrate current on the working state of adjacent semiconductor devices on the substrate (semiconductor devices formed on the buried layer in the substrate).

[0056] See also Figure 1 , is a schematic flow chart of a method for preparing a semiconductor device in one embodiment.

[0057] In order to solve the above problems, the present application provides a method for preparing a semiconductor device, such as Figure 1 , the preparation method comprises:

[0058] S102, providing a substrate of a first conductivity type.

[0059] The substrate may be single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc., with a first conductive type doped layer formed on the surface, or single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc., doped with first conductive type impurities. As an example, in the present embodiment, the substrate is a single crystal silicon substrate doped with first conductive type impurities, and its specific doping concentration is not limited by the present application.

[0060] S104, forming a first buried layer of a second conductivity type in the substrate.

[0061] A first buried layer is formed in a substrate of a first conductive type, wherein the first buried layer has a second conductive type, which is opposite to the first conductive type; when the first conductive type is P type, the second conductive type is N type, and when the first conductive type is N type, the second conductive type is P type. In this embodiment, the first conductive type is P type and the second conductive type is N type. Figure 2 , is a schematic cross-sectional view of a semiconductor device after a first buried layer is formed in one embodiment.

[0062] like Figure 2 In one embodiment, step S104 is specifically: injecting doping ions or doping atoms of the second conductivity type into the substrate 102 through an ion implantation process to form a first buried layer 104 with the second conductivity type in the substrate 102, and the upper surface of the first buried layer 104 is flush with the upper surface of the substrate 102.

[0063] In one embodiment, step S104 is specifically: injecting doping ions or doping atoms of the second conductivity type into the substrate through an ion implantation process to form a first buried layer of the second conductivity type in the substrate, wherein the upper surface of the first buried layer is lower than the upper surface of the substrate.

[0064] In one embodiment, the depth of the first buried layer 104 is greater than or equal to 0.04 micrometers and less than or equal to 0.06 micrometers, for example, 0.05 micrometers. In practical applications, the depth of the first buried layer 104 can be set as needed.

[0065] In one embodiment, the doping concentration of the first buried layer 104 is greater than or equal to 1*10 14 cm -3 and less than or equal to 1*10 15 cm -3 In actual process, the doping concentration of the first buried layer 104 can be adjusted according to process requirements.

[0066] S106, forming a second buried layer of a second conductivity type on an upper surface of the first buried layer.

[0067] A second buried layer having a second conductivity type is formed on an upper surface of the first buried layer, wherein a doping concentration of the second buried layer is lower than a doping concentration of the first buried layer.

[0068] See also Figure 3 , is a schematic cross-sectional view of a semiconductor device after a second buried layer is formed in one embodiment.

[0069] like Figure 3 In one embodiment, step S106 includes:

[0070] In the first step, a first epitaxial layer is formed on the upper surface of the substrate.

[0071] In one embodiment, the first epitaxial layer 106 is formed on the upper surface of the substrate 102 by an epitaxial process. In other embodiments, the first epitaxial layer 106 is formed on the upper surface of the substrate 102 by a chemical vapor deposition process. The thickness of the first epitaxial layer 106 is greater than or equal to the depth of the second buried layer 108 formed in the next step.

[0072] In the second step, ions of the second conductivity type are implanted to form a second buried layer in the first epitaxial layer, wherein the upper surface of the second buried layer is flush with the upper surface of the first epitaxial layer.

[0073] Specifically, dopant ions or dopant atoms of the second conductivity type are implanted into the first epitaxial layer 106 through an ion implantation process to form a second buried layer 108 of the second conductivity type in the region of the first epitaxial layer 106 above the first buried layer 104 , and the upper surface of the second buried layer 108 is flush with the upper surface of the first epitaxial layer 106 .

[0074] In one embodiment, the depth of the second buried layer 108 is greater than or equal to 0.04 micrometers and less than or equal to 0.06 micrometers, for example, 0.05 micrometers. In practical applications, the depth of the second buried layer 108 can be set as needed.

[0075] In one embodiment, the depth of the second buried layer 108 is 0.05 microns, and the thickness of the first epitaxial layer is 0.05 microns.

[0076] In one embodiment, the doping concentration of the second buried layer 108 is greater than or equal to 1*10 13 cm -3 and less than or equal to 1*10 14 cm -3In an actual process, the doping concentration of the second buried layer 108 can be adjusted according to process requirements, as long as the doping concentration of the second buried layer 108 is lower than the doping concentration of the first buried layer 104 .

[0077] S108, forming a second conductivity type well region and a device layer on the second buried layer.

[0078] Specifically, a second conductive type well region and a device layer are formed on the second buried layer, the bottom of the second conductive type well region contacts the second buried layer, the device layer is formed in the area surrounded by the second buried layer and the second conductive type well region, the device layer includes a first conductive type well region, and the first conductive type well region is formed on the upper surface of the second buried layer close to the second conductive type well region. That is, the device layer is formed on the upper surface of the second buried layer in the area surrounded by the second buried layer and the second conductive type well region, the device layer includes a first conductive type well region, the first conductive type well region is formed on the upper surface of the second buried layer close to the second conductive type well region, and the first conductive type well region and the second conductive type well region are adjacent.

[0079] Through this arrangement, the first buried layer 104 and the second buried layer 108 coexist under the device layer subsequently formed on the upper surface of the second buried layer 108, so that the substrate current of the semiconductor device corresponding to the device layer is affected by the doping concentration of the first buried layer 104, and the breakdown voltage of the planar junction formed by the first conductive type well region and the second buried layer in the device layer 112 is only affected by the doping concentration of the second buried layer 108. The substrate current of the semiconductor device corresponding to the device layer 112 can be reduced by increasing the doping concentration of the first buried layer 104, while the breakdown voltage of the planar junction will not be affected.

[0080] See also Figure 4 , is a schematic cross-sectional view of a semiconductor device after a device layer is formed in one embodiment.

[0081] like Figure 4 In one embodiment, step S108 includes:

[0082] In the first step, a second epitaxial layer 110 is formed on the upper surface of the first epitaxial layer 106 .

[0083] In one embodiment, the first epitaxial layer 106 and the second epitaxial layer 110 have the same doping concentration and are both epitaxial layers of the first conductivity type.

[0084] In one embodiment, the thickness of the second epitaxial layer 110 is greater than the thickness of the first epitaxial layer 106. For example, the thickness of the second epitaxial layer 110 is greater than or equal to 4 microns and less than or equal to 8 microns, such as 5 microns, 6 microns, 7 microns, etc. In practical applications, the second epitaxial layer 110 with different thicknesses can be selected according to the needs of the subsequently formed device layer 112.

[0085] In the second step, a second conductivity type well region 111 is formed in the second epitaxial layer 110 .

[0086] A second conductivity type well region 111 is formed in the second epitaxial layer 110 , and the bottom of the second conductivity type well region 111 is flush with the upper surface of the second buried layer 108 .

[0087] In the third step, a device layer 112 is formed in the area surrounded by the second conductivity type well region 111 and the second buried layer 108 .

[0088] In one embodiment, the device layer 112 formed in the region surrounded by the second conductivity type well region 111 and the second buried layer 108 is a device layer in a high voltage semiconductor device.

[0089] Specifically, the upper surface of the second buried layer 108 is flush with the upper surface of the first epitaxial layer 106. After the second epitaxial layer 110 is formed on the upper surface of the first epitaxial layer 106 by a common film forming process, a second conductive type well region 111 is formed in the second epitaxial layer 110 on the upper surface of the second buried layer 108 by an ion implantation process, wherein the bottom of the second conductive type well region 111 is in contact with the edge of the upper surface of the second buried layer 108. A device layer 112 is formed in the region of the second epitaxial layer 110 surrounded by the second conductive type well region 111 and the second buried layer 108 by photolithography, etching, implantation, and thin film processes, wherein the lower surface of the device layer 112 is flush with the lower surface of the second epitaxial layer 110.

[0090] In one embodiment, the projection of the second buried layer 108 on the upper surface of the substrate 102 overlaps with the upper surface of the first buried layer 104, or the projection of the second buried layer 108 on the upper surface of the substrate 102 is surrounded by the upper surface of the first buried layer 104. By adjusting the size of the second buried layer 108 located on the upper surface of the first buried layer 104, the surface area of ​​the device layer 112 can be adjusted.

[0091] In one embodiment, the method for preparing a semiconductor device further includes:

[0092] A substrate lead-out region of a first conductivity type is formed on the substrate 102 , and the substrate lead-out region is electrically connected to the substrate for leading out the substrate.

[0093] like Figure 4In one embodiment, the first epitaxial layer 106, the second epitaxial layer 110, and the substrate 102 all have the first conductivity type, the upper surface of the second buried layer 108 is flush with the upper surface of the first epitaxial layer 106, and the projection of the second buried layer 108 on the upper surface of the substrate 102 overlaps with the first buried layer. A substrate lead-out region 114 is formed in the area of ​​the second epitaxial layer 110 that is not on the upper surface of the second buried layer, wherein the lower surface of the substrate lead-out region 114 is flush with the upper surface of the first epitaxial layer 106 (the upper surface of the second buried layer 108), the substrate lead-out region 114 has the first conductivity type, and the substrate lead-out region 114 is a deep well doping region, the doping concentration of the substrate lead-out region 114 is greater than the doping concentration of the first epitaxial layer 106, the second epitaxial layer 110, and the substrate 102, the projection of the substrate lead-out region 114 on the surface of the substrate 102 is adjacent to the first buried layer 104, and the substrate lead-out region 114 corresponds one-to-one to the semiconductor devices included in the device layer. The substrate 102 can be brought out to the surface through the substrate lead-out region 114 to facilitate metal interconnection in subsequent processes.

[0094] In one embodiment, the first epitaxial layer 106 and the second epitaxial layer 110 can be an epitaxial layer formed simultaneously in the step of forming the first epitaxial layer 106, the second buried layer 108 is located in the epitaxial layer, and the upper surface of the second buried layer 108 is lower than the upper surface of the epitaxial layer, and the upper surface of the first epitaxial layer 106 is a plane in the epitaxial layer that is flush with the upper surface of the second buried layer 108.

[0095] See also Figure 5 , is a cross-sectional schematic diagram of a semiconductor device in one embodiment.

[0096] like Figure 5 Taking the first conductivity type as P type and the second conductivity type as N type as an example, the step of forming the device layer 112 in the area surrounded by the second conductivity type well region 111 and the second buried layer 108 includes: first, forming a first conductivity type well region 118 on the upper surface of the second buried layer 108, the first conductivity type well region 118 is located in the area surrounded by the second conductivity type well region 111 and the second buried layer 108, and is adjacent to the second conductivity type well region 111, and then, forming other functional structures of the device layer 112.

[0097] The method for preparing the semiconductor device comprises the following steps: forming a first buried layer having a second conductivity type in a substrate of a first conductivity type, wherein the second conductivity type is opposite to the first conductivity type; forming a second buried layer of the second conductivity type on the upper surface of the first buried layer, wherein the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer; forming a second conductivity type well region and a device layer on the second buried layer, wherein the bottom of the second conductivity type well region contacts the second buried layer, and the device layer is formed in the region surrounded by the second buried layer and the second conductivity type well region, wherein the device layer comprises a first conductivity type well region, and the first conductivity type well region is formed on the upper surface of the second buried layer near the second conductivity type well region. Compared with directly forming the second buried layer in the substrate, the doping concentration of the first buried layer in the semiconductor device of the present application is higher than the doping concentration of the second buried layer, the substrate current of the semiconductor device is lower, and the breakdown voltage of the planar junction formed by the first conductivity type well region and the second buried layer on the upper surface of the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced.

[0098] like Figure 4 As shown, in one embodiment, a semiconductor device is provided, comprising:

[0099] The substrate 102 has a first conductivity type; the substrate 102 may be single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc., with a first conductivity type doped layer formed on the surface, or single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc., doped with first conductivity type impurities. As an example, in the present embodiment, the substrate 102 is a single crystal silicon substrate doped with first conductivity type impurities, and its specific doping concentration is not limited by the present application.

[0100] The first buried layer 104 has a second conductivity type and is formed in the substrate 102. The second conductivity type is opposite to the first conductivity type. When the first conductivity type is P type, the second conductivity type is N type. When the first conductivity type is N type, the second conductivity type is P type. In this embodiment, the first conductivity type is P type and the second conductivity type is N type.

[0101] The second buried layer 108 has a second conductivity type and is formed on the upper surface of the first buried layer 104 . The doping concentration of the second buried layer 108 is lower than that of the first buried layer 104 .

[0102] The second conductive type well region 111 is formed on the second buried layer 108 , and the bottom of the second conductive type well region 111 is in contact with the second buried layer 108 .

[0103] The device layer 112 is formed in the area surrounded by the second buried layer 108 and the second conductive type well region 111 . The device layer 112 includes a first conductive type well region 118 . The first conductive type well region 118 is formed on the upper surface of the second buried layer 108 close to the second conductive type well region 111 .

[0104] In the above semiconductor device, a first buried layer of a second conductive type is formed in a substrate of a first conductive type, a second buried layer of a second conductive type is formed on the upper surface of the first buried layer, and the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer, a well region of a second conductive type is formed on the second buried layer, and the bottom of the well region of the second conductive type is in contact with the second buried layer; a device layer is formed in an area surrounded by the second buried layer and the well region of the second conductive type, and the device layer includes a well region of a first conductive type, and the well region of the first conductive type is formed on the upper surface of the second buried layer near the well region of the second conductive type. Compared with a semiconductor device in which a second buried layer is directly formed in a substrate, the doping concentration of the first buried layer in the semiconductor device of the present application is higher than the doping concentration of the second buried layer, the substrate current of the semiconductor device is lower, and the breakdown voltage of the planar junction formed by the well region of the first conductive type and the second buried layer on the upper surface of the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced.

[0105] In one embodiment, the upper surface of the first buried layer 104 is flush with the upper surface of the substrate 102 .

[0106] In one embodiment, the semiconductor device further comprises:

[0107] The first epitaxial layer 106 is formed on the upper surface of the substrate 102. A second buried layer 108 is formed in the first epitaxial layer 106. The upper surface of the second buried layer 108 is flush with the upper surface of the first epitaxial layer 106. A second buried layer 108 of a second conductivity type is formed in the region of the first epitaxial layer 106 located above the first buried layer 104. The upper surface of the second buried layer 108 is flush with the upper surface of the first epitaxial layer 106.

[0108] In one embodiment, the thickness of the first epitaxial layer is greater than or equal to the depth of the second buried layer 108 .

[0109] In one embodiment, the depth of the first buried layer 104 is greater than or equal to 0.04 micrometers and less than or equal to 0.06 micrometers, for example, 0.05 micrometers. In practical applications, the depth of the first buried layer 104 can be set as needed.

[0110] In one embodiment, the doping concentration of the first buried layer 104 is greater than or equal to 1*10 14 cm -3 and less than or equal to 1*10 15 cm -3 In actual process, the doping concentration of the first buried layer 104 can be adjusted according to process requirements.

[0111] In one embodiment, the depth of the second buried layer 108 is 0.05 microns, and the thickness of the first epitaxial layer 106 is 0.05 microns.

[0112] In one embodiment, the doping concentration of the second buried layer 108 is greater than or equal to 1*10 13 cm -3 and less than or equal to 1*10 14 cm -3 In an actual process, the doping concentration of the second buried layer 108 can be adjusted according to process requirements, as long as the doping concentration of the second buried layer 108 is lower than the doping concentration of the first buried layer 104 .

[0113] In one embodiment, the projection of the second buried layer 108 on the upper surface of the substrate 102 overlaps with the upper surface of the first buried layer 104, or the projection of the second buried layer 108 on the upper surface of the substrate 102 is surrounded by the upper surface of the first buried layer 104. By adjusting the size of the second buried layer 108 located on the upper surface of the first buried layer 104, the surface area of ​​the device layer 112 can be adjusted.

[0114] In one embodiment, the semiconductor device further comprises:

[0115] The second epitaxial layer 110 is formed on the upper surface of the first epitaxial layer 106 . A second conductivity type well region 111 and a device layer 112 are formed in the second epitaxial layer 110 .

[0116] In one embodiment, the first epitaxial layer 106 and the second epitaxial layer 110 have the same doping concentration and are both epitaxial layers of the first conductivity type.

[0117] like Figure 5 , in one embodiment, the semiconductor device further comprises:

[0118] A first shallowly doped region 201 has a second conductivity type and is formed in the second conductivity type well region 111 , wherein a lower surface of the first shallowly doped region 201 is higher than a lower surface of the second conductivity type well region 111 ;

[0119] A first heavily doped region 202 having a second conductivity type and formed in the first lightly doped region 201 , wherein a lower surface of the first heavily doped region 202 is higher than a lower surface of the first lightly doped region 201 ;

[0120] The second shallowly doped region 203 has the first conductivity type and is formed in the first conductivity type well region 118 , and the lower surface of the second shallowly doped region 203 is higher than the lower surface of the first conductivity type well region 118 ;

[0121] A second heavily doped region 204 , having the first conductivity type, is formed in the second lightly doped region 203 , and a lower surface of the second heavily doped region 204 is higher than a lower surface of the second lightly doped region 203 ;

[0122] The first shallow trench isolation structure 205 is formed on the upper surface of the second epitaxial layer 110 and is located between the first conductive type well region 118 and the second conductive type well region 111. The lower surface of the first shallow trench isolation structure 205 is higher than the lower surfaces of the first shallowly doped region 201 and the second shallowly doped region 203, and is lower than the lower surfaces of the first heavily doped region 202 and the second heavily doped region 204.

[0123] In one embodiment, the thickness of the second epitaxial layer 110 is greater than the thickness of the first epitaxial layer 106, for example, the thickness of the second epitaxial layer 110 is greater than or equal to 4 microns and less than or equal to 8 microns, for example, 5 microns, 6 microns, 7 microns, etc. In practical applications, the second epitaxial layer 110 with different thicknesses can be selected according to the needs of the device layer 112 to be formed subsequently.

[0124] In one embodiment, the device layer 112 formed in the region surrounded by the second conductivity type well region 111 and the second buried layer 108 is a device layer in a high voltage semiconductor device.

[0125] In one embodiment, the semiconductor device further comprises:

[0126] The substrate lead-out region 114 has a first conductivity type and is formed on the substrate 102 . The substrate lead-out region 114 is connected to the substrate 102 and is used to lead out the substrate 102 .

[0127] In one embodiment, the substrate lead-out region 114 is formed in a region of the second epitaxial layer 110 that is not on the upper surface of the second buried layer, wherein the lower surface of the substrate lead-out region 114 is flush with the upper surface of the first epitaxial layer 106 (the upper surface of the second buried layer 108), the substrate lead-out region 114 has a first conductivity type, and the substrate lead-out region 114 is a deep well doping region, the doping concentration of the substrate lead-out region 114 is greater than the doping concentrations of the first epitaxial layer 106, the second epitaxial layer 110, and the substrate 102, the projection of the substrate lead-out region 114 on the surface of the substrate 102 is adjacent to the first buried layer 104, and the substrate lead-out region 114 corresponds one-to-one to the semiconductor devices included in the device layer. The substrate 102 can be led to the surface through the substrate lead-out region 114, which is convenient for metal interconnection in subsequent processes.

[0128] In one embodiment, the semiconductor device further comprises:

[0129] A third shallowly doped region 206 , having the first conductivity type, is formed in the substrate lead-out region 114 , and a lower surface of the third shallowly doped region 206 is higher than a lower surface of the substrate lead-out region 114 ;

[0130] A third heavily doped region 207 , having the first conductivity type, is formed in the third shallowly doped region 206 , and a lower surface of the third heavily doped region 207 is higher than a lower surface of the third shallowly doped region 206 ;

[0131] The second shallow trench isolation structure 208 is formed on the upper surface of the second epitaxial layer 110 and is located between the substrate lead-out region 114 and the second conductive type well region 111. The lower surface of the second shallow trench isolation structure 208 is higher than the lower surfaces of the first shallowly doped region 201 and the third shallowly doped region 206, and is lower than the lower surfaces of the first heavily doped region 202 and the third heavily doped region 207.

[0132] In one embodiment, the bottom surfaces of the first shallow trench isolation structure 205 and the second shallow trench isolation structure 208 are flush with each other, and the depths of the first shallow trench isolation structure 205 and the second shallow trench isolation structure 208 are both 4000 angstroms.

[0133] In one embodiment, the bottom surfaces of the first shallowly doped region 201 , the second shallowly doped region 203 and the third shallowly doped region 206 are flush, and the bottom surfaces of the first heavily doped region 202 , the second heavily doped region 204 and the third heavily doped region 207 are flush.

[0134] In one embodiment, the first conductivity type well region 118 is located in a region surrounded by the second conductivity type well region 111 and the second buried layer 108 , and is adjacent to the second conductivity type well region 111 .

[0135] In one embodiment, the lower surface of the device layer 112 is flush with the lower surface of the second epitaxial layer 110 .

[0136] The present application also provides an electronic device, comprising any of the semiconductor devices described above.

[0137] The semiconductor device in the above electronic device forms a first buried layer of a second conductive type in a substrate of a first conductive type, a second buried layer of a second conductive type is formed on the upper surface of the first buried layer, and the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer, a well region of a second conductive type is formed on the second buried layer, and the bottom of the well region of the second conductive type is in contact with the second buried layer; the device layer is formed in the area surrounded by the second buried layer and the well region of the second conductive type, the device layer includes a well region of a first conductive type, and the well region of the first conductive type is formed on the upper surface of the second buried layer near the well region of the second conductive type. Compared with a semiconductor device in which the second buried layer is directly formed in the substrate, the doping concentration of the first buried layer in the semiconductor device of the present application is higher than the doping concentration of the second buried layer, the substrate current of the semiconductor device is lower, and the breakdown voltage of the planar junction formed by the well region of the first conductive type and the second buried layer on the upper surface of the second buried layer is related to the doping concentration of the second buried layer, and when the doping concentration of the first buried layer is increased to reduce the substrate current, the breakdown voltage of the planar junction will not be reduced.

[0138] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0139] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; a first buried layer having a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type; A second buried layer, having a second conductivity type, formed on an upper surface of the first buried layer, wherein a doping concentration of the second buried layer is lower than a doping concentration of the first buried layer; A second conductive type well region is formed on the second buried layer, and a bottom of the second conductive type well region is in contact with the second buried layer; a device layer formed in a region surrounded by the second buried layer and a second conductive type well region, the device layer comprising a first conductive type well region, the first conductive type well region being formed on an upper surface of the second buried layer close to the second conductive type well region; a first epitaxial layer formed on the upper surface of the substrate, wherein the second buried layer is formed in the first epitaxial layer; A second epitaxial layer is formed on the upper surface of the first epitaxial layer, wherein the second conductive type well region and the device layer are formed in the second epitaxial layer, wherein the device layer includes a second epitaxial layer formed in an area surrounded by the second buried layer and the second conductive type well region and in contact with the first conductive type well region; the first epitaxial layer and the second epitaxial layer are both epitaxial layers of the first conductive type.

2. The semiconductor device according to claim 1, wherein: An upper surface of the second buried layer is flush with an upper surface of the first epitaxial layer.

3. The semiconductor device according to claim 2, characterized in that Also includes: A first shallowly doped region, having a second conductivity type, is formed in a well region of the second conductivity type, wherein a lower surface of the first shallowly doped region is higher than a lower surface of the well region of the second conductivity type; A first heavily doped region, having a second conductivity type, is formed in the first lightly doped region, wherein a lower surface of the first heavily doped region is higher than a lower surface of the first lightly doped region; A second shallowly doped region, having a first conductivity type, is formed in a well region of the first conductivity type, wherein a lower surface of the second shallowly doped region is higher than a lower surface of the well region of the first conductivity type; A second heavily doped region, having a first conductivity type, is formed in the second lightly doped region, wherein a lower surface of the second heavily doped region is higher than a lower surface of the second lightly doped region; A first shallow trench isolation structure is formed on the upper surface layer of the second epitaxial layer and is located between the first conductive type well region and the second conductive type well region. The lower surface of the first shallow trench isolation structure is higher than the lower surfaces of the first shallowly doped region and the second shallowly doped region, and is lower than the lower surfaces of the first heavily doped region and the second heavily doped region.

4. The semiconductor device according to claim 3, characterized in that Also includes: A substrate lead-out region, having a first conductivity type and formed on the substrate, wherein the substrate lead-out region is electrically connected to the substrate and is used to lead out the substrate; A third shallowly doped region, having a first conductivity type, is formed in the substrate lead-out region, and a lower surface of the third shallowly doped region is higher than a lower surface of the substrate lead-out region; A third heavily doped region, having the first conductivity type, is formed in the third lightly doped region, and a lower surface of the third heavily doped region is higher than a lower surface of the third lightly doped region; A second shallow trench isolation structure is formed on the upper surface of the second epitaxial layer and is located between the substrate lead-out region and the second conductive type well region. The lower surface of the second shallow trench isolation structure is higher than the lower surfaces of the first shallowly doped region and the third shallowly doped region, and is lower than the lower surfaces of the first heavily doped region and the third heavily doped region.

5. The semiconductor device according to claim 1, wherein: The depths of the first buried layer and the second buried layer are both greater than or equal to 0.04 micrometers and less than or equal to 0.06 micrometers, and the doping concentration of the first buried layer is greater than or equal to 1*10 14 cm -3 and less than or equal to 1*10 15 cm -3 , the doping concentration of the second buried layer is greater than or equal to 1*10 13 cm -3 and less than or equal to 1*10 14 cm -3 .

6. A method for preparing a semiconductor device, characterized in that: include: providing a substrate of a first conductivity type; forming a first buried layer of a second conductivity type in the substrate, the second conductivity type being opposite to the first conductivity type; forming a second buried layer of a second conductivity type on an upper surface of the first buried layer, wherein the doping concentration of the second buried layer is lower than the doping concentration of the first buried layer; forming a second conductive type well region and a device layer on the second buried layer, wherein the bottom of the second conductive type well region contacts the second buried layer, the device layer is formed in a region surrounded by the second buried layer and the second conductive type well region, the device layer includes a first conductive type well region, and the first conductive type well region is formed on an upper surface of the second buried layer close to the second conductive type well region; in, The step of forming a second buried layer of a second conductivity type on the upper surface of the first buried layer comprises: forming a first epitaxial layer on the upper surface of the substrate; Performing ion implantation of a second conductivity type to form the second buried layer in the first epitaxial layer; The step of forming a second conductivity type well region and a device layer on the second buried layer comprises: forming a second epitaxial layer on an upper surface of the first epitaxial layer; forming a second conductivity type well region in the second epitaxial layer; The device layer is formed in the area surrounded by the second conductive type well region and the second buried layer; the device layer includes a second epitaxial layer formed in the area surrounded by the second buried layer and the second conductive type well region and in contact with the first conductive type well region; the first epitaxial layer and the second epitaxial layer are both epitaxial layers of the first conductive type.

7. The preparation method according to claim 6, characterized in that: An upper surface of the second buried layer is flush with an upper surface of the first epitaxial layer.

8. The preparation method according to claim 6, characterized in that: Also includes: A substrate lead-out region of a first conductivity type is formed on the substrate, wherein the substrate lead-out region is electrically connected to the substrate and is used to lead out the substrate.

9. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 5.

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