Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device having high withstand voltage, excellent productivity, and a surge voltage at the time of recovery or cutoff being suppressed, and a manufacturing method thereof. A first buffer layer (7) having a higher concentration than the drift layer (2) into which protons are implanted is provided between the drift layer (2) and the second diffusion layer (5). A second buffer layer (8) having a higher concentration than the drift layer (2) is provided between the first buffer layer (7) and the second diffusion layer (5). The peak concentration of the second buffer layer (8) is higher than the peak concentration of the first buffer layer (7). The impurity concentration of the first buffer layer (7) gradually decreases toward the back surface. The length from the peak position of the first buffer layer (7) to the boundary between the drift layer (2) and the first buffer layer (7) is set as Xa, and the length from the peak position to the boundary between the first buffer layer (7) and the second buffer layer (8) is set as Xb, Xb > 5Xa.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] If a reverse bias is applied to a semiconductor device of a vertical type, a depletion layer extends from an interface between a P-type region formed on a substrate surface side and an N-type drift layer toward a back surface side. There is a technique in which the depletion layer is stopped at a prescribed depth by a deep buffer layer, thereby suppressing a surge voltage at the time of cutoff (for example, refer to Patent Literature 1).

[0003] Patent Literature 1: Japanese Patent Application Laid-Open No. 2009-176892

[0004] When donorization on the back surface side of the deep buffer layer is insufficient, a defect region is generated. In the related art, in order not to form the defect region, multi-stage implantation or high concentration implantation is performed, and thus productivity is low. In addition, since the depletion layer is stopped within the deep buffer layer, there is a problem in which a withstand voltage decreases. SUMMARY

[0005] The present application has been made to solve the above-described problems, and has an object to provide a semiconductor device and a manufacturing method thereof in which a withstand voltage is high, productivity is excellent, and a surge voltage at the time of recovery or cutoff can be suppressed.

[0006] The semiconductor device according to the present application is characterized by including: a semiconductor substrate having a surface, a back surface on the opposite side of the surface, and a drift layer of a first conductive type between the surface and the back surface; a first diffusion layer of a second conductive type provided between the drift layer and the surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductive type provided between the drift layer and the second diffusion layer, implanted with protons, and having a higher concentration than the drift layer; and a second buffer layer of the first conductive type between the first buffer layer and the second diffusion layer, having a higher concentration than the drift layer, a peak concentration of the second buffer layer being higher than a peak concentration of the first buffer layer, an impurity concentration of the first buffer layer gradually decreasing toward the back surface, a length from a peak position of the first buffer layer to a boundary between the drift layer and the first buffer layer being set as Xa, and a length from the peak position to a boundary between the first buffer layer and the second buffer layer being set as Xb, Xb > 5Xa.

[0007] EFFECT OF THE INVENTION

[0008] In the present application, a high concentration second buffer layer is provided between the first buffer layer and the second diffusion layer. The length from the peak position of the first buffer layer to the boundary of the drift layer and the first buffer layer is set to Xa, and the length from the peak position to the boundary of the first buffer layer and the second buffer layer is set to Xb, Xb > 5Xa. Thus, a semiconductor device having high withstand voltage, excellent productivity, and suppressed surge voltage at recovery or cutoff can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0010] Figure 2 is a graph showing the impurity concentration distribution on the back surface side of the semiconductor device according to an embodiment.

[0011] Figure 3 is a graph showing the Xb / Xa dependence of the surge voltage Vka at recovery.

[0012] Figure 4 is a graph showing the integral of the donor concentration from the surface toward the back surface of the semiconductor substrate.

[0013] Figure 5 is a graph showing the concentration dependence of the second buffer layer on the leakage current of the diode.

[0014] Figure 6 is a simulation result showing the peak depth dependence of the second buffer layer on the withstand voltage BV.

[0015] Figure 7 is a graph showing the impurity concentration distribution of the first buffer layer at each activation annealing temperature of a 1200V class diode.

[0016] Figure 8 is a graph showing the impurity concentration distribution of the first buffer layer at each activation annealing temperature of a 1200V class diode.

[0017] Figure 9 is a cross-sectional view showing a modification 1 of the semiconductor device according to an embodiment.

[0018] Figure 10 is a graph showing Figure 9 the depth dependence of the first buffer layer on the surge voltage Vka at recovery of the diode of

[0019] Figure 11 is a graph showing Figure 9 the concentration dependence of the first buffer layer on the surge voltage at recovery of the diode of

[0020] Figure 12is a cross-sectional view showing Modification 2 of the semiconductor device to which the embodiment is applied. DETAILED DESCRIPTION

[0021] Figure 1 is a cross-sectional view showing the semiconductor device to which the embodiment is applied. The semiconductor device is a diode of a 4500 V voltage class. Figure 1 is a cross-sectional view of the diode unit portion. The semiconductor substrate 1 is a silicon substrate, has a surface, a back surface on the opposite side of the surface, and an n-type drift layer 2 between the surface and the back surface. The thickness of the semiconductor substrate 1 is, for example, 430 to 530 μm. In the case of a 4500 V voltage class, the impurity concentration of the drift layer 2 is, for example, 7.0E12 to 2.0E13 cm -3 . The impurity of the drift layer 2 is P (phosphorus), As (arsenic), or Sb (antimony).

[0022] The anode layer 3 of p-type is provided between the drift layer 2 and the surface of the semiconductor substrate 1. The impurity of the anode layer 3 is B (boron) or Al (aluminum). The anode electrode 4 is provided on the surface of the semiconductor substrate 1 and is connected to the anode layer 3.

[0023] The cathode layer 5 of n-type is provided between the drift layer 2 and the back surface of the semiconductor substrate 1. The impurity of the cathode layer 5 is P (phosphorus) or As (arsenic). The cathode electrode 6 is provided on the back surface of the semiconductor substrate 1 and is connected to the cathode layer 5.

[0024] The first buffer layer 7 of n-type is provided between the drift layer 2 and the cathode layer 5. The first buffer layer 7 is a layer in which protons are implanted and donorized by annealing, and is higher in concentration than the drift layer 2. The second buffer layer 8 of n-type is provided between the first buffer layer 7 and the cathode layer 5. The second buffer layer 8 is a layer in which phosphorus is ion-implanted and donorized by annealing, and is higher in concentration than the drift layer 2.

[0025] Figure 2 is a graph showing the impurity concentration distribution on the back surface side of the semiconductor device to which the embodiment is applied. The peak concentration of the first buffer layer 7 is less than or equal to 1E15 cm -3 . The position of the peak concentration of the first buffer layer 7, that is, the peak position, is present in a range of 10 to 30 μm in depth from the back surface. The peak position of the second buffer layer 8 is present in a range of 0.5 to 3.0 μm in depth from the back surface. The peak concentration of the second buffer layer 8 is higher than the peak concentration of the first buffer layer 7. The impurity concentration of the first buffer layer 7 gradually decreases toward the back surface.

[0026] In this embodiment, the length from the peak position of the first buffer layer 7 to the boundary of the drift layer 2 and the first buffer layer 7 is set to Xa, and the length from the peak position to the boundary of the first buffer layer 7 and the second buffer layer 8 is set to Xb, and the impurity concentration distribution is set in a manner of Xb > 5Xa. Since a large amount of hydrogen is supplied from the peak position of the first buffer layer 7 toward the back surface, the generation of a defect region generated in a case where the donorization of the first buffer layer 7 is insufficient can be suppressed. In addition, even if the drift layer 2 is low in concentration, the generation of a defect region can be suppressed, and thus the first buffer layer 7 can be formed deep without performing a multi-stage implantation or a high concentration implantation, and thus the productivity of implantation can be improved.

[0027] In addition, since it is assumed from the result of the impurity distribution that an acceptor exists in the defect region, the defect region is an acceptor region. Therefore, the second buffer layer 8 having a high concentration is provided between the first buffer layer and the cathode layer 5. The defect region of several μm or so on the back surface side can be compensated for by donorization by the second buffer layer 8. Therefore, even in a case where the impurity concentration of the first buffer layer 7 is reduced, it is difficult to generate a defect region. Therefore, the impurity concentration of the first buffer layer 7 can be reduced, and the depletion layer can be gently prevented. As a result, the surge voltage at the time of recovery can be suppressed, and the withstand voltage can be improved. Figure 3 is a graph showing the Xb / Xa dependence of the surge voltage Vka at the time of recovery. It is known that the surge voltage can be suppressed in a case where Xb > 5Xa.

[0028] In addition, the value of the electric field strength at which an avalanche breakdown occurs is called a critical electric field strength. The avalanche breakdown depends on the constituent elements of a semiconductor, impurities doped into the semiconductor, and the concentration of the impurities. If the donor concentration is set to N D , the critical electric field strength is set to E C , if the ionization integration is performed using the collision ionization coefficient of silicon, the critical electric field strength E C is 2.5 x 105 V / cm. The critical electric field strength E D is represented by mathematical formula 1.

[0029] [Formula 1]

[0030] Ec = 4010 • (N 1 / 8 )

[0031] From mathematical formula 1, as long as the donor concentration N D is determined, the critical electric field strength E C is determined. In addition, the Poisson formula is represented by mathematical formula 2 in a case where only a one-dimensional direction (set to the x direction) is considered.

[0032] [Formula 2]

[0033] dE / dx = (q / ε r 0) (p - n + N 1 / 8 )D - N A )

[0034] Here, q is an elementary charge (1.062 x 10 15 [C]), ε0is a dielectric constant of vacuum (8.854 x 10 -14 [F / cm]), ε r is a relative dielectric constant of a substance. In the case of silicon, ε r = 11.9. p is a hole concentration, n is an electron concentration, and N A is an acceptor concentration. In the case of a single-sided abrupt junction, only an n-type layer is considered, and thus it is assumed that there is no acceptor (N A = 0). Also, if a depletion layer in which there are no holes and electrons (n = p = 0) is assumed, by integrating mathematical formula 2 with respect to depth x, mathematical formula 3 is obtained.

[0035] [Formula 3]

[0036] E = (q / ε r ε0)∫N D dx

[0037] The position of a pn junction is assumed to be the origin 0, and the position of the end of a depletion layer at a position opposite the pn junction in an n-type layer is assumed to be x0. Also, if the depletion layer as a whole from 0 to x0 is integrated, E of mathematical formula 3 becomes a maximum value of an electric field intensity distribution. If this is assumed to be E m , E m is expressed by mathematical formula 4.

[0038] [Formula 4]

[0039]

[0040] If the maximum value Em of the electric field intensity distribution is assumed to reach a critical electric field intensity E C , mathematical formula 4 is expressed by mathematical formula 5.

[0041] [Formula 5]

[0042]

[0043] Both sides of mathematical formula 5 are constants. The right side of mathematical formula 5 is a range in which complete depletion occurs in an n-type layer, and is called a critical integration concentration n C . From this, the following mathematical formula 6 is obtained. Mathematical formula 6 shows a correspondence between the critical integration concentration n C and the critical electric field intensity E C . In this way, the critical integration concentration n C becomes a value corresponding to the critical electric field intensity E Ccorresponding value. If the value in the present case is substituted, the critical integrated concentration n C is represented as n C = 6.52E06 x E C .

[0044]

Formula 6

[0045] E c (ε r ε0 / q) = n c

[0046] Figure 4 is a graph in which the donor concentration is integrated from the surface toward the back surface of the semiconductor substrate. The critical integrated concentration is smaller than or equal to the position of the drift layer 2 and the first buffer layer 7, and is larger than or equal to the position of at least the peak concentration of the second buffer layer 8. In this way, by providing the position larger than or equal to the critical integrated concentration to the second buffer layer 8, the depletion layer extends to the position of the second buffer layer 8, and thus the withstand voltage can be improved and the leakage current can be reduced.

[0047] Figure 5 is a graph showing the concentration dependency of the second buffer layer with respect to the leakage current of the diode. By making the impurity concentration of the second buffer layer 8 high, the leakage current can be reduced. It is preferable that the impurity concentration of the second buffer layer 8 be larger than or equal to 2E16 cm -3 , and more preferably larger than or equal to 4E16 cm -3 .

[0048] Figure 6 is a simulation result showing the peak depth dependency of the second buffer layer with respect to the withstand voltage BV. The depth from the back surface of the peak concentration of the second buffer layer 8 is referred to as the peak depth. By making the peak depth shallow, the depletion layer sufficiently extends in the thickness direction, and thus the withstand voltage BV can be improved. It is preferable that the peak depth of the second buffer layer 8 be smaller than or equal to 2 μm.

[0049] The impurity concentration becomes a minimum value at the boundary of the first buffer layer 7 and the second buffer layer 8. It is preferable that the minimum value be larger than or equal to the impurity concentration of the drift layer 2. In this way, by making the donor concentration of the first buffer layer 7 and the second buffer layer 8 high, the effect of blocking the depletion layer can be improved, and the surge voltage at the time of recovery can be suppressed.

[0050] In the case where the donor concentration of the first buffer layer 7 is reduced, defects are easily generated in the region from the peak position of the first buffer layer 7 toward the back surface. In contrast, by gently reducing the donor concentration of the first buffer layer 7 toward the back surface, defects in this region become difficult to generate, and the withstand voltage can be improved. Specifically, it is preferable that the donor concentration from the peak position of the first buffer layer 7 toward the back surface up to 0.3Xb be greater than or equal to 10% of the peak concentration of the first buffer layer 7.

[0051] Further, it is preferable that the impurity concentration of the drift layer 2 fall within the range of 3E13 to 3E14 cm -3 , and the peak position of the first buffer layer 7 exist at 15 to 25 μm. Alternatively, it is preferable that the impurity concentration of the drift layer 2 fall within the range of 1E12 to 3E13 cm -3 , and the peak position of the first buffer layer 7 exist at 20 to 30 μm. By thus setting, even if the impurity concentration of the first buffer layer 7 is reduced, defects are difficult to generate, and the depletion layer can be gently prevented.

[0052] Next, the method of forming the diffusion layer on the back surface side of the semiconductor device according to the present embodiment will be described. First, the cathode layer 5 is formed by implanting impurities into the back surface of the semiconductor substrate 1. Next, the first buffer layer 7 is formed by implanting protons between the drift layer 2 and the cathode layer 5. Next, the second buffer layer 8 is formed by implanting impurities between the first buffer layer 7 and the cathode layer 5. Next, the cathode layer 5 and the second buffer layer 8 are activated using the heat of a laser. Next, the first buffer layer 7 is doped by furnace annealing.

[0053] Here, the protons are activated in the range of approximately 350 to 500°C, and if the temperature becomes higher, anneal out occurs, and the donors disappear. However, the speed of activation at low temperatures of 350°C is slow, and the anneal processing time becomes long, which is not suitable for mass production. Further, the speed of activation at high temperatures of 500°C is fast, and therefore, it is difficult to control the fluctuations within the wafer surface and between batches. Therefore, the temperature of the furnace annealing is set to fall within the range of 400 to 450°C.

[0054] Further, crystal defects are generated in the region where the protons pass through, that is, the back surface side. This crystal defect induces doping at the time of annealing. Therefore, the impurity concentration of the first buffer layer 7 becomes a distribution that is gentle on the back surface side and steep on the surface side, such as Xb > 5Xa. However, if the processing time of the furnace annealing is made longer, the diffusion range becomes large, and in order to diffuse to a large range with a gentle gradient on the back surface side, annealing of greater than or equal to 2 hours is required.

[0055] Furthermore, if donor formation is not advanced towards the back side of the first buffer layer 7, defect regions will be generated. Conversely, the lower the impurity concentration of the semiconductor substrate 1 and the shorter the range of the implanted protons, the less likely defect regions will be generated. Specifically, by using an impurity concentration of 3E13 to 3E14 cm⁻¹ in the semiconductor substrate 1... -3 Under the condition that the proton range is set to 15-25 μm, and the impurity concentration of semiconductor substrate 1 is 1E12-3E13 cm⁻¹ -3 In this case, the range of the protons is set to 20-30 μm, thus obtaining a concentration distribution of Xb > 5Xa.

[0056] Figure 7 This diagram shows the impurity concentration distribution of the first buffer layer of a 1200V diode at each activation annealing temperature. The activation annealing temperatures of the first buffer layer 7 are 340°C, 370°C, and 400°C. The annealing time is 120 minutes. At lower activation annealing temperatures, leakage current increases due to the formation of defective regions on the back side. Therefore, the minimum impurity concentration at the boundary between the first buffer layer 7 and the second buffer layer 8 needs to be greater than or equal to the impurity concentration of the drift layer 2. By setting the activation annealing temperature of the first buffer layer 7 to be greater than or equal to 400°C, the formation of defective regions on the back side is suppressed.

[0057] By shortening the annealing time, productivity can also be improved. Figure 8 This diagram shows the impurity concentration distribution of the first buffer layer of a 1200V diode at each activation annealing temperature. The activation annealing temperatures of the first buffer layer 7 are 400°C, 410°C, and 430°C. The annealing time is 60 minutes. At low activation annealing temperatures, leakage current increases due to the formation of defective regions on the back side. By setting the activation annealing temperature of the first buffer layer 7 to be greater than or equal to 410°C, the formation of defective regions on the back side is suppressed. Therefore, the minimum impurity concentration at the boundary between the first buffer layer 7 and the second buffer layer 8 needs to be greater than or equal to the impurity concentration of the drift layer 2.

[0058] Figure 9 This is a cross-sectional view showing a modified example 1 of the semiconductor device according to the embodiment. The semiconductor device is a diode with a voltage rating of 4500V. On the back side of the semiconductor substrate 1, an n-type cathode layer 5 and a back p-type layer 9 are arranged alternately in a laterally aligned manner. The impurity concentration of the drift layer 2 is approximately 1E13cm³. -3 .

[0059] Figure 10 It means Figure 9The graph shows the measurement results of the surge voltage Vka during recovery of the diode, which is dependent on the depth of the first buffer layer. If the first buffer layer 7 is shallow, the hole injection efficiency from the back p-type layer 9 decreases. Therefore, the electric field strength on the back side increases, and the surge voltage during recovery becomes higher. However, if the first buffer layer 7 is too deep, it causes a decrease in breakdown voltage and the formation of defect regions. Therefore, it is preferable that the depth of the first buffer layer 7 is 10 to 30 μm, more preferably 20 to 30 μm, which reduces the surge voltage during recovery.

[0060] Figure 11 It means Figure 9 The graph shows the concentration dependence of the first buffer layer on the surge voltage during diode recovery. If the impurity concentration of the first buffer layer 7 is high, the hole injection efficiency from the back p-type layer 9 decreases. Therefore, the electric field strength on the back side increases, and the surge voltage during recovery becomes higher. Therefore, it is preferable that the peak concentration of the first buffer layer 7 is less than or equal to 1E15cm⁻¹. -3 However, when the impurity concentration in the first buffer layer 7 is too low, the effect of the first buffer layer 7 in preventing the depletion layer becomes smaller. Therefore, a concentration of 1E14cm is more preferable. -3 ~1E15cm -3 The range.

[0061] Figure 12 This is a cross-sectional view showing a modified example 2 of the semiconductor device according to the embodiment. The semiconductor device is an insulated gate bipolar transistor (IGBT). Figure 12 This is a cross-sectional view of the IGBT unit. A p-type base layer 10 is disposed on the surface side of the semiconductor substrate 1. An n-type base layer is disposed on the surface side of the base layer 10. + Type 11 emitter layer and p + Type contact layer 12. To incorporate n + A trench 13 is formed through the emitter layer 11 and the base layer 10. A gate electrode 15 is disposed inside the trench 13, separated by an insulating film 14. An emitter electrode 16 is disposed on the surface of the semiconductor substrate 1. A p-type collector layer 17 and a collector electrode 18 are disposed on the back side of the semiconductor substrate 1. The structures of the first buffer layer 7 and the second buffer layer 8 are similar to... Figure 1 The diodes are the same, and their functions and effects are also the same. However, they can suppress surge voltage during cutoff rather than surge voltage during recovery. Furthermore, an n-type diode can be disposed below the base layer 10 of the p-type diode. + The type layer can also be a reverse-conducting IGBT with IGBT region and diode region.

[0062] Explanation of the label

[0063] 1 semiconductor substrate, 2 drift layer, 3 anode layer (1st diffusion layer), 5 cathode layer (2nd diffusion layer), 7 1st buffer layer, 8 2nd buffer layer, 9 back p-type layer (p-type layer), 10 base layer (1st diffusion layer), 17 collector layer (2nd diffusion layer).

Claims

1. A semiconductor device, characterized by comprising: Having: a semiconductor substrate having a surface, a back surface on the opposite side of the surface, and a drift layer of a first conductivity type between the surface and the back surface; a first diffusion layer of a second conductivity type provided between the drift layer and the surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductivity type provided between the drift layer and the second diffusion layer, implanted with protons, and having a higher concentration than the drift layer; and a second buffer layer of the first conductivity type between the first buffer layer and the second diffusion layer, having a higher concentration than the drift layer, the peak concentration of the second buffer layer is higher than the peak concentration of the first buffer layer, the impurity concentration of the first buffer layer gradually decreases from the peak position toward the back surface, the length from the peak position of the first buffer layer to the boundary between the drift layer and the first buffer layer is set as Xa, the length from the peak position to the boundary between the first buffer layer and the second buffer layer is set as Xb, Xb > 5Xa.

2. The semiconductor device according to claim 1, wherein the second diffusion layer has a p-type layer, the peak position of the first buffer layer is present in a range of 10 to 30 μm in depth from the back surface.

3. The semiconductor device according to claim 1, wherein the second diffusion layer has a p-type layer, 4. The semiconductor device according to claim 2, wherein the peak concentration of the first buffer layer is less than or equal to 1E15 cm -3 . the second diffusion layer has a p-type layer, 5. The semiconductor device according to any one of claims 1 to 4, wherein the peak concentration of the first buffer layer is less than or equal to 1E15 cm -3 . when the donor impurity concentration is integrated from the surface toward the back surface, the drift layer and the first buffer layer are less than or equal to a critical integrated concentration, and the second buffer layer is greater than or equal to the critical integrated concentration at least at the position of the peak concentration.

6. The semiconductor device according to any one of claims 1 to 4, wherein 7. The semiconductor device according to any one of claims 1 to 4, wherein The impurity concentration of the second buffer layer is greater than or equal to 2E16 cm -3 . the depth of the peak concentration of the second buffer layer from the back surface is less than or equal to 2 μm.

8. The semiconductor device according to any one of claims 1 to 4, wherein the minimum value of the impurity concentration of the first buffer layer and the second buffer layer is greater than or equal to the impurity concentration of the drift layer.

9. The semiconductor device according to any one of claims 1 to 4, wherein the donor concentration of the first buffer layer from the peak position toward the back surface to 0.3Xb is greater than or equal to 10% of the peak concentration of the first buffer layer.

10. The semiconductor device according to any one of claims 1 to 4, wherein the peak position of the first buffer layer is present in 15 to 25 μm. The impurity concentration of the drift layer falls in the range of 3E13 to 3E14 cm -3 -3.

11. The semiconductor device according to any one of claims 1 to 4, wherein the peak position of the first buffer layer is present in 20 to 30 μm. The impurity concentration of the drift layer falls in the range of 1E12~3E13 cm -3 -2. ​ 12. A method of manufacturing a semiconductor device according to any one of claims 1 to 11, the method of manufacturing characterized by comprising the steps of: forming the second diffusion layer by implanting impurities into the back surface of the semiconductor substrate; forming the first buffer layer by implanting protons between the drift layer and the second diffusion layer; forming the second buffer layer by implanting impurities between the first buffer layer and the second diffusion layer; activating the second diffusion layer and the second buffer layer using heat of a laser; and dopantizing the first buffer layer by furnace annealing, the temperature of the furnace annealing is in the range of 400 to 450°C, and the processing time is greater than or equal to 2 hours.

13. A method of manufacturing a semiconductor device according to any one of claims 1 to 11, the method of manufacturing characterized by comprising the steps of: forming the second diffusion layer by implanting impurities into the back surface of the semiconductor substrate; forming the first buffer layer by implanting protons between the drift layer and the second diffusion layer; forming the second buffer layer by implanting impurities between the first buffer layer and the second diffusion layer; activating the second diffusion layer and the second buffer layer using heat of a laser; and dopantizing the first buffer layer by furnace annealing, the temperature of the furnace annealing is in the range of 410 to 450°C, and the processing time is greater than or equal to 1 hour.

14. The method of manufacturing a semiconductor device according to claim 12 or 13, characterized in that, In the case where the impurity concentration of the semiconductor substrate is 3E13 to 3E14 cm -3 -3, the range of the proton is set to 15 to 25 μm, and in the case where the impurity concentration of the semiconductor substrate is 1E12 to 3E13 cm -3 -3, the range of the proton is set to 20 to 30 μm.

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