A high-speed field effect transistor and a method of fabricating the same

Abstract

The application provides a high-speed field effect transistor and a preparation method thereof. The high-speed field effect transistor comprises a substrate, a gate unit, a source unit and a drain unit connected to both sides of the gate unit, and the gate unit comprises an intrinsic GaAs layer, an intrinsic AlGaAs layer and an N+AlGaAs layer sequentially arranged on both ends of the intrinsic GaAs layer, a gate metal layer arranged on the upper end of the N+AlGaAs layer, a P region arranged in the middle of the intrinsic GaAs layer, the lower end of the P region being in contact with the substrate, the upper end of the P region being sequentially covered with an oxide layer and polycrystalline silicon, and both sides of the polycrystalline silicon and the oxide layer being in contact with the intrinsic AlGaAs layer. The application forms a heterojunction structure composed of AlGaAs and GaAs between the gate, the source and the drain, the structure can form a thin-layer N-type conductive channel, thereby eliminating the influence of impurity scattering; GaAs has higher electron mobility than Si, so that most carriers also move faster than in Si, in addition, GaAs also has the characteristics of reducing parasitic capacitance and signal loss, thereby effectively improving the output power and frequency.

Description

TECHNICAL FIELD

[0001] The application relates to a high-speed field effect transistor and a preparation method thereof. BACKGROUND

[0002] The existing field effect transistor is generally silicon-based, and the carriers in the channel are affected by lattice scattering, impurity scattering and surface scattering during transportation, so that the mobility is reduced and the cutoff frequency is limited, and the existing field effect transistor has the defects of low speed, high energy loss and the like. In the existing HEMT device, the high-mobility carriers have the defects of low concentration, small current and weak load capacity, and even a multilayer structure can solve the problem of low carrier concentration, but the structure is complex and the process is too complicated.

[0003] GaAs has higher electron mobility than Si, so a kind of multi-channel laminated insulated side gate fin structure AlGaAs / GaAs high electron mobility transistor disclosed in CN111430459A utilizes a multi-layer AlGaAs / GaAs heterojunction to form a laminated N wire channel, and since an AlGaAs layer and a GaAs layer need to be grown for each channel, the process is complex and is not conducive to production. SUMMARY

[0004] To solve the above technical problems, the application provides a high-speed field effect transistor and a preparation method thereof.

[0005] The application is implemented through the following technical solutions.

[0006] The application provides a high-speed field effect transistor and a preparation method thereof, which comprises a substrate, a gate unit provided on the substrate, and a source unit and a drain unit connected to the two sides of the gate unit, respectively, the gate unit comprises an intrinsic GaAs layer, the upper ends of the intrinsic GaAs layer are not covered with an intrinsic AlGaAs layer and an N+AlGaAs layer in sequence, the upper end of the N+AlGaAs layer is provided with a gate metal layer, the middle part of the intrinsic GaAs layer is provided with a P region, the lower end of the P region is in contact with the substrate, the upper end of the P region is covered with an oxide layer and polycrystalline silicon in sequence, the two sides of the polycrystalline silicon and the oxide layer are in contact with the intrinsic AlGaAs layer, and the two sides of the intrinsic GaAs layer are connected with the source unit and the drain unit, respectively.

[0007] The gate unit is n, and when n>1, the n gate units are connected in sequence.

[0008] The source unit and the drain unit each comprise an N+GaAs layer, the N+GaAs layer is connected with the intrinsic GaAs layer, and the upper end of the N+GaAs layer is provided with a drain metal layer and a source metal, respectively.

[0009] A preparation method of a high-speed field effect transistor, the method comprises the following steps:

[0010] S1, making a substrate, growing an intrinsic GaAs layer on the substrate by LPE;

[0011] S2, growing a field oxide layer on the intrinsic GaAs layer by thermal oxidation;

[0012] S3, performing photoetching on the middle and both ends of the oxide layer respectively to photoetch a P+ region window and an N+ region window;

[0013] S4, performing P ion implantation and N ion implantation respectively in the P region window and the N region window and then performing annealing to form a P region and an N+ GaAs layer respectively;

[0014] S5, epitaxially growing an intrinsic AlGaAs layer and an N+ AlGaAs layer;

[0015] S6, photoetching the AlGaAs layer and the N+ AlGaAs layer on the upper end of the P region;

[0016] S7, depositing silicon oxide in the photoetched region by PECVD;

[0017] S8, photoetching the silicon oxide in the region other than the P region to form an oxide layer;

[0018] S9, depositing polysilicon on the oxide layer by LPCVD;

[0019] S10, photoetching the polysilicon in the region other than the oxide layer to form a polysilicon layer;

[0020] S11, photoetching the AlGaAs layer and the N+ AlGaAs layer on the N+ GaAs layer to form an N+ AlGaAs layer and an intrinsic AlGaAs layer;

[0021] S12, performing front metal tungsten sputtering on the N+ AlGaAs layer and the N+ GaAs layer, and then performing metal tungsten photoetching and alloying to form a gate metal layer, a drain metal layer and a source metal respectively;

[0022] S13, depositing silicon nitride on the surface of the die, and then photoetching the passivation layer on the upper end of the gate metal layer, the drain metal layer and the source metal.

[0023] The substrate is a GaAs semi-insulating single crystal wafer with an electrical resistivity ρ>10 7 Ω·cm.

[0024] The growth temperature of the oxide layer in S2 is 1050℃, and the method is to perform dry oxygen oxidation for 180-210 min and then perform wet oxygen oxidation for 10-20 min.

[0025] In S4,

[0026] The boron dosage of the B ion implantation is 3e14-5e14 cm-2 energy 30-40KeV, injection angle 6-7°, and annealing after completion.

[0027] P ion implantation, phosphorus dose 2e15-4e15cm -2 energy 70-80KeV, injection angle 6-7°, and annealing after completion.

[0028] The thickness of the N+ AlGaAs layer and the intrinsic AlGaAs layer in the S11 is 0.1-0.2μm and

[0029] The thickness of the oxidized layer and the polysilicon is and

[0030] The thickness of the passivation layer is

[0031] The beneficial effects of the present application are that a heterojunction structure composed of AlGaAs and GaAs is formed between the gate, the source and the drain, which can form a thin N-type conductive channel, and the electrons in the channel are far away from the ionized impurities, thus eliminating the influence of impurity scattering.

[0032] A series structure is formed by multiple gate units, and multiple N-type conductive channels are formed, which not only reduces the complexity of the process, but also further improves the electron mobility. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a schematic diagram of the basic unit structure of the present application;

[0034] Figure 2 is a schematic diagram of the chip structure of the present application;

[0035] In the figure: 1-gate metal layer, 2-N+ AlGaAs layer, 3-intrinsic AlGaAs layer, 4-polysilicon, 5-oxidized layer, 6-drain metal layer, 7-source metal, 8-N+ GaAs layer, 9-P region, 10-intrinsic GaAs layer, 11-substrate. DETAILED DESCRIPTION

[0036] The technical solutions of the present application are further described below, but the scope of protection is not limited to the description.

[0037] A high-speed field-effect transistor and its fabrication method are disclosed, comprising a substrate 11; a gate unit, a source unit, and a drain unit are disposed on the substrate 11, the gate unit comprising an intrinsic GaAs layer 10, an intrinsic AlGaAs layer 3 and an N+AlGaAs layer 2 are sequentially covered at both ends of the intrinsic GaAs layer 10, a gate metal layer 1 is disposed at the upper end of the N+AlGaAs layer 2, a P-region 9 is disposed in the middle of the intrinsic GaAs layer 10, the lower end of the P-region 9 is in contact with the substrate 11, an oxide layer 5 and a polysilicon layer 4 are sequentially covered at the upper end of the P-region 9, the polysilicon layer 4 and the oxide layer 5 are in contact with the intrinsic AlGaAs layer 3 on both sides, and the two sides of the intrinsic GaAs layer 10 are respectively connected to the drain of the source unit and the drain of the drain unit.

[0038] There are n gate units, and when n>1, the n gate units are connected in series.

[0039] Both the source and drain units include an N+GaAs layer 8, which is connected to the intrinsic GaAs layer 10. A drain metal layer 6 and a source metal layer 7 are respectively disposed on the upper end of the N+GaAs layer 8.

[0040] like Figure 2 As shown, the gate, drain, and source cells constitute the basic MOSFET structure. A heterojunction structure composed of AlGaAs and GaAs exists between the gate and source, and also between the gate and drain. When the gate voltage exceeds the threshold voltage, a thin N-type conductive channel is formed on the surface of the P-region below the gate through inversion. The thickness of the inversion channel is controlled by adjusting the gate voltage. Simultaneously, when a forward voltage is applied to the Schottky contact metal, the AlGaAs and GaAs heterojunction controlled by it forms a high-electron-mobility N-type conductive channel, i.e., 2-DEG, on the surface of the undoped GaAs buffer layer. Electrons in this channel are not only far from ionized impurities, eliminating the influence of impurity scattering, but also have their recombination prevented by the intrinsic AlGaAs spacer layer, further improving electron mobility. If a drain-source voltage is applied, a drain-source current with high electron mobility and low noise is output. When the Schottky metal voltage is reverse-biased, the high-mobility electrons in the GaAs buffer layer are depleted, and the current is pinched off.

[0041] Compared to silicon-based field-effect transistors, which weaken the scattering effect of impurities in the conductive channel and improve electron mobility, GaAs has a higher electron mobility than Si, so majority carriers move faster than in silicon. In addition, GaAs also has the characteristics of reducing parasitic capacitance and signal loss, thereby effectively improving output power and frequency. Compared to ordinary HEMT devices, the device of this invention will have increased current, enhanced load capacity, simplified structure, and is easier to implement in the process.

[0042] A method for preparing a high-speed field effect transistor, the method comprising:

[0043] S1, making a substrate 11, and growing an intrinsic GaAs layer 10 on the substrate 11 by LPE;

[0044] S2, growing a field oxide layer on the intrinsic GaAs layer 10 by thermal oxidation;

[0045] S3, performing photoetching on the middle and both ends of the field oxide layer respectively to photoetch a P+ region window and an N+ region window;

[0046] S4, performing P ion implantation and N implantation in the P region window and the N region window respectively, and then performing annealing to form a P region 9 and an N+ GaAs layer 8 respectively;

[0047] S5, epitaxially growing an intrinsic AlGaAs layer and an N+ AlGaAs layer;

[0048] S6, photoetching the AlGaAs layer and the N+ AlGaAs layer on the upper end of the P region 9;

[0049] S7, depositing silicon oxide in the photoetched region by PECVD;

[0050] S8, photoetching the silicon oxide in the region other than the P region 9 to form a field oxide layer 5;

[0051] S9, depositing polysilicon on the field oxide layer 5 by LPCVD;

[0052] S10, photoetching the polysilicon in the region other than the field oxide layer 5 to form a polysilicon layer 4;

[0053] S11, photoetching the AlGaAs layer and the N+ AlGaAs layer on the N+ GaAs layer 8 to form an N+ AlGaAs layer 2 and an intrinsic AlGaAs layer 3;

[0054] S12, performing front metal tungsten sputtering on the N+ AlGaAs layer 2 and the N+ GaAs layer 8, and then performing metal tungsten photoetching and alloying to form a gate metal layer 1, a drain metal layer 6 and a source metal 7 respectively;

[0055] S13, depositing silicon nitride on the surface of the die, and then photoetching the passivation layer on the upper end of the gate metal layer 1, the drain metal layer 6 and the source metal 7.

[0056] The substrate is a GaAs semi-insulating single crystal wafer with an electrical resistivity ρ>10 7 Ω·cm.

[0057] The growth temperature of the field oxide layer in S2 is 1050℃, and the method comprises dry oxygen oxidation for 180-210 min and wet oxygen oxidation for 10-20 min.

[0058] The S4 is,

[0059] The boron dose of B ion implantation is 3e14-5e14 cm -2 , the energy is 30-40 KeV, the implantation angle is 6-7°, and annealing is performed after completion.

[0060] P ion implantation, the phosphorus dose is 2e15-4e15 cm -2 , the energy is 70-80 KeV, the implantation angle is 6-7°, and annealing is performed after completion.

[0061] The thickness of the N+ AlGaAs layer 2 and the intrinsic AlGaAs layer 3 in the S11 is 0.1-0.2 μm and

[0062] The thickness of the oxidized layer 5 and the polysilicon 4 is and

[0063] The thickness of the passivation layer is

[0064] 1. A GaAs semi-insulating single crystal wafer with a resistivity of 110 Ω·cm is prepared, and a GaAs epitaxial layer is grown by LPE, and the width of the epitaxial layer is about 1 um.

[0065] 2. A field oxide layer is grown on the surface, the growth temperature is 1050°C, the growth time is 250 min, and the oxidation process adopts a method combining dry oxygen oxidation and wet oxygen oxidation, the dry oxygen time is 210 min, and the wet oxygen is 20 min.

[0066] 3. Silicon oxidation photolithography, etching and stripping are performed in the existing manner to form P and N+ implantation windows in sequence.

[0067] 4. B ion implantation is performed, the boron dose is 5e14 cm -2 , the energy is 40 KeV, the implantation angle is 7°, N ion implantation is then performed, the phosphorus dose is 4e15 cm -2 , the energy is 80 KeV, the implantation angle is 7, and annealing treatment is performed to activate the impurity ions.

[0068] 5. The wafer surface is cleaned in the existing manner, and HF and stripping liquid are used to remove the oxide layer and photoresist during the cleaning.

[0069] 6. A 0.2 um intrinsic AlGaAs layer and N+ type AlGaAs layer are grown by molecular beam epitaxy.

[0070] 7. AlGaAs layer photolithography, etching and stripping are performed in the existing manner to form a silicon oxide deposition window, and the gate length is about 0.2-0.25 um.

[0071] 8. Silicon oxide is deposited by PECVD, thickness is about 1000A

[0072] 9. Silicon oxide layer is photolithographed and etched by existing method, then LPCVD is used to deposit Polysilicon forms gate region.

[0073] 10. Polysilicon layer is photolithographed by existing method, then annealing is performed.

[0074] 12. AlGaAs layer is photolithographed, etched and removed by existing method, forming drain and source ohmic contact window.

[0075] 13. Front side tungsten metal film is deposited by magnetron sputtering, thickness is 2um, tungsten metal is etched according to existing technology, forming front side drain and source electrode and Schottky contact electrode, then metal alloying is performed, alloying temperature and time are 400℃ and 30min respectively.

[0076] 14. Silicon nitride film is deposited by PECVD, film thickness is

[0077] 15. Silicon nitride is photolithographed, etched and removed by existing process, forming passivation layer.

[0078] Product parameters after fabrication are:

[0079]

Claims

1. A high speed field effect transistor comprising a substrate (11), characterised in that: The substrate (11) is provided with a gate unit and a source unit and a drain unit respectively connected to both sides of the gate unit. The gate unit includes an intrinsic GaAs layer (10). The intrinsic GaAs layer (10) is covered with an intrinsic AlGaAs layer (3) and an N+AlGaAs layer (2) in sequence at both ends. A gate metal layer (1) is provided at the upper end of the N+AlGaAs layer (2). A P region (9) is provided in the middle of the intrinsic GaAs layer (10). The lower end of the P region (9) is in contact with the substrate (11). An oxide layer (5) and a polysilicon layer (4) are covered at the upper end of the P region (9). The polysilicon layer (4) and the oxide layer (5) are in contact with the intrinsic AlGaAs layer (3) on both sides. The intrinsic GaAs layer (10) is connected to the drain of the source unit and the drain of the drain unit on both sides.

2. The high speed field effect transistor of claim 1, wherein: There are n gate units, and when n>1, the n gate units are connected in series.

3. The high-speed field-effect transistor as described in claim 1, characterized in that: Both the source unit and the drain unit include an N+GaAs layer (8), which is connected to the intrinsic GaAs layer (10). The upper end of the N+GaAs layer (8) is provided with a drain metal layer (6) and a source metal layer (7).

4. A method for fabricating a high-speed field-effect transistor, the method comprising: S1. Fabricate a substrate (11) and grow an intrinsic GaAs layer (10) on the substrate (11) using LPE. S2, a field oxide layer is grown on the intrinsic GaAs layer (10) by thermal oxidation; S3. Photolithography is performed on the middle and both ends of the oxide layer to create P+ and N+ region windows; S4. P-ion implantation and N-ion implantation are performed in the P-region window and N-region window respectively, followed by annealing to form P-region (9) and N+GaAs layer (8) respectively. S5. Epitaxial growth of intrinsic AlGaAs and N+AlGaAs layers; S6. Photolithographically remove the AlGaAs layer and N+AlGaAs layer at the top of P region (9); S7. Silicon oxide is deposited in the photolithography area using PECVD; S8. Photolithography removes the silicon oxide layer (5) from the region outside P region (9); S9. Polycrystalline silicon is deposited on the oxide layer (5) using LPCVD. S10. Photolithography removes the polysilicon outside the oxide layer (5) to form polysilicon (4); S11. Photolithography removes the AlGaAs layer (N+AlGaAs) on the N+GaAs layer (8) to form the N+AlGaAs layer (2) and the intrinsic AlGaAs layer (3); S12. Front-side tungsten sputtering is performed on N+AlGaAs layer (2) and N+GaAs layer (8), followed by tungsten photolithography and alloying to form gate metal layer (1), drain metal layer (6) and source metal layer (7), respectively. S13. Deposit silicon nitride on the die surface, and then remove the passivation layer at the top of the gate metal layer (1), drain metal layer (6), and source metal layer (7) by photolithography.

5. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: The substrate is a GaAs semi-insulating single crystal wafer with a resistivity p > 10 7 Ω-cm.

6. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: The growth temperature of the oxide layer in S2 is 1050℃, and the method is to use dry oxygen oxidation for 180-210 min followed by wet oxygen oxidation for 10-20 min.

7. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: In S4, The boron dose of B ion implantation is 3e14-5e14 cm -2 , the energy is 30-40 KeV, the implantation angle is 6-7°, and annealing is performed after completion. P ion implantation, phosphorous dose of 2e15-4e15 cm -2 70-80 KeV, implantation angle of 6-7°, and annealing after completion.

8. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: The thicknesses of the N+AlGaAs layer (2) and the intrinsic AlGaAs layer (3) in S11 are 0.1-0.2 μm and 0.2 μm, respectively.

9. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: The thicknesses of the oxide layer (5) and the polysilicon (4) are respectively and 10. The method for fabricating a high-speed field-effect transistor as described in claim 4, characterized in that: The passivation layer thickness is

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