Semiconductor memory device

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and a method of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a double-gate transistor and a memory cell. The memory cell is adjacent to the double-gate transistor, wherein the memory cell and the double-gate transistor share a common electrode.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor memory devices and methods of forming the same. Background Art

[0002] Semiconductor memory devices can generally be classified into volatile memory devices and non-volatile memory (NVM) devices. Resistive random access memory (RRAM) devices are a type of non-volatile memory (NVM) device for advanced computing systems, such as for in-memory processing (PIM) applications and machine learning (ML) applications using binary neural network (BNN)-based techniques. RRAM devices are suitable for such applications because they can provide a high-density architecture with high parallel programming speed and low power consumption.

[0003] However, memory devices may pose various challenges, such as sensitivity to process variations and high latency in programming speed. There is a need for high-density memory device arrays to improve the accuracy of ML algorithms that occupy valuable space on semiconductor chips.

[0004] Therefore, it is desirable to provide memory devices and methods of forming the same with improved device performance and a smaller footprint to overcome or at least mitigate the above disadvantages. Summary of the Invention

[0005] To achieve the above and other aspects of the present disclosure, semiconductor memory devices and methods of forming the same are provided.

[0006] According to one aspect of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device includes a double-gate transistor and a memory cell adjacent to the double-gate transistor. The memory cell and the double-gate transistor share a common electrode.

[0007] According to another aspect of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device includes a double-gate transistor and a memory cell adjacent to the double-gate transistor. The memory cell further includes a first memory electrode, a switching layer coupled to the first memory electrode, and a second memory electrode coupled to the switching layer. The first memory electrode is a drain electrode of the double-gate transistor.

[0008] According to another aspect of the present disclosure, a method of forming a semiconductor memory device is provided. The method includes forming a double-gate transistor and forming a memory element adjacent to the double-gate transistor. The double-gate transistor is formed by forming a gate electrode stack having a first gate electrode and a second gate electrode located above the first gate electrode. The memory element is formed by forming a first memory electrode and a second memory electrode adjacent to the double-gate transistor. The memory element is formed to be coupled to the double-gate transistor through the first memory electrode of the memory element. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be better understood by reading the following detailed description in conjunction with the accompanying drawings:

[0010] Figure 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 1 A to Figure 1 C are enlarged views corresponding to respective regions of the semiconductor memory device in Figure 1 according to an embodiment of the present disclosure.

[0012] Figures 2A to 2D is a cross-sectional view showing a method of forming the semiconductor memory device in Figure 1 according to an embodiment of the present disclosure.

[0013] Figure 3 is a cross-sectional view of a semiconductor memory device according to an alternative embodiment of the present disclosure.

[0014] Figure 4 is a cross-sectional view of a semiconductor memory device according to an alternative embodiment of the present disclosure.

[0015] Figure 5 is a cross-sectional view of a semiconductor memory device according to an alternative embodiment of the present disclosure.

[0016] Figure 6 is a cross-sectional view of a semiconductor memory device according to an alternative embodiment of the present disclosure.

[0017] For simplicity and clarity of illustration, the drawings illustrate general construction manners and may omit specific descriptions and details of well-known features and technologies to avoid unnecessarily obscuring the discussion of the described embodiments of the device.

[0018] Additionally, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the embodiments of the device. The same reference numerals in different drawings represent the same elements, while similar reference numerals may but do not necessarily represent similar elements. Detailed Description of the Embodiments

[0019] The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor memory devices and methods of forming the same. The semiconductor memory device improves device performance with a smaller footprint.

[0020] A resistive random access memory (RRAM) element typically includes a pair of memory electrodes and a switching layer interposed between the pair of memory electrodes. The switching layer of the RRAM element is typically insulating.

[0021] The RRAM element operates by switching between states based on the resistance of the switching layer. For example, when a sufficiently high voltage difference is applied between the two memory electrodes, a dielectric breakdown event may occur and one or more conducting filaments may be formed within the switching layer. As one or more conducting filaments are formed, the switching layer becomes conductive. By applying a sufficiently low voltage difference between the two memory electrodes to break the one or more conducting filaments, the switching layer can return to an insulating state.

[0022] When the switching layer is insulating, the switching layer has a relatively high resistance and the RRAM element can be referred to as being in a high resistance state (HRS). When the switching layer is conductive, the switching layer has a relatively low resistance and the RRAM element can be referred to as being in a low resistance state (LRS). To set the RRAM element, the RRAM element is switched from the HRS to the LRS. To reset the RRAM element, the RRAM element is switched from the LRS to the HRS.

[0023] Various embodiments of the present disclosure will now be described in detail in conjunction with the accompanying drawings. It should be noted that the same and corresponding elements are denoted by the same reference numerals. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limiting of the present disclosure.

[0024] Figure 1 is a cross-sectional view of a semiconductor memory device 100 according to an embodiment of the present disclosure. Figure 1 A, Figure 1 B and Figure 1C is an enlarged view corresponding to respective regions of the memory device 100 depicted by the dashed lines. The memory device 100 may be disposed in a memory primitive region of a semiconductor device, and the memory device 100 may be part of a plurality of memory devices arranged in an array configuration of rows and columns in the memory primitive region. For clarity, only one memory device is shown. The memory device 100 may include a transistor 102 and an RRAM primitive 104 adjacent to the transistor 102.

[0025] The RRAM primitive 104 may be coupled to the transistor 102. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0026] The transistor 102 may be a double-gate transistor including a gate electrode stack having a first gate electrode 106 and a second gate electrode 108 located above the first gate electrode 106. In one embodiment of the present disclosure, the first and second gate electrodes 106, 108 may include a conductive material such as, but not limited to, tantalum, hafnium, copper, silver, cobalt, tungsten, combinations thereof, or other conductive materials known to those skilled in the art. In another embodiment of the present disclosure, the first and second gate electrodes 106, 108 may include a bilayer stack of a conductive material such as, but not limited to, titanium / titanium nitride, etc. In yet another embodiment of the present disclosure, the thickness of the first and second gate electrodes 106, 108 may be in the range of 5 to 30 nm. It should be understood that the first and second gate electrodes 106, 108 may not have to be formed of the same conductive material or have the same thickness, although Figure 1 they are shown as being formed of the same conductive material and having the same thickness.

[0027] The transistor 102 may further include a first gate dielectric layer 110 and a second gate dielectric layer 112. The first and second gate dielectric layers 110, 112 may be disposed between the first and second gate electrodes 106, 108 such that the first gate dielectric layer 110 covers above the first gate electrode 106 and the second gate dielectric layer 112 pads below the second gate electrode 108. The second gate dielectric layer 112 may also be conformal with the lower surface of the second gate electrode 108. In one embodiment of the present disclosure, the first and second gate dielectric layers 110, 112 may include a dielectric material such as, but not limited to, tantalum oxide, hafnium oxide, aluminum oxide, silicon oxide, combinations thereof, or other dielectric materials known to those skilled in the art. In another embodiment of the present disclosure, the thickness of the first and second gate dielectric layers 110, 112 may be in the range of 2 to 10 nm. It should be understood that the first and second gate dielectric layers 110, 112 may not necessarily be formed of the same dielectric material or have the same thickness, although Figure 1 it is shown that they are formed of the same dielectric material and have the same thickness.

[0028] The transistor 102 may further include a channel layer 114 between the first and second gate dielectric layers 110, 112. The channel layer 114 may conformally cover above the first gate dielectric layer 110. In one embodiment of the present disclosure, the channel layer 114 may include an oxide semiconductor material such as, but not limited to, zinc oxide, cadmium oxide, indium oxide, indium gallium zinc oxide (IGZO), combinations thereof, or other oxide semiconductor materials known to those skilled in the art. In another embodiment of the present disclosure, the channel layer 114 may include amorphous silicon. In yet another embodiment of the present invention, the thickness of the channel layer 114 may be in the range of 3 to 20 nm.

[0029] The transistor 102 may include a source electrode 116 and a drain electrode 118. The source electrode 116 may be disposed adjacent to a first side of the gate electrode stack, and the drain electrode 118 may be disposed adjacent to a second side of the gate electrode stack, where the gate electrode stack includes the first and second gate electrodes 106, 108, and the second side is laterally opposite to the first side. The source and drain electrodes 116, 118 may also be disposed above a portion of the channel layer 114.

[0030] In one embodiment of the present disclosure, the source and drain electrodes 116, 118 may have lower surfaces that are substantially coplanar with the lowermost surface of the first gate dielectric layer 110. In another embodiment of the present disclosure, the source and drain electrodes 116, 118 may comprise a conductive material such as, but not limited to, ruthenium, platinum, titanium nitride, tantalum nitride, combinations thereof, or other conductive materials known to those skilled in the art. In another embodiment of the present disclosure, the thickness of the source and drain electrodes 116, 118 may be in the range of 5 to 10 nm. It should be understood that the source and drain electrodes 116, 118 need not be formed of the same conductive material or have the same thickness, although Figure 1 it is shown that they are formed of the same conductive material and have the same thickness.

[0031] The RRAM element 104 may be adjacent to the transistor 102; in particular, the RRAM element 104 may be arranged on the second side of the gate electrode stack such that the drain electrode 118 of the transistor 102 is a common electrode shared with the RRAM element 104. In one embodiment of the present disclosure, the drain electrode 118 of the transistor 102 is the first memory electrode 118 of the RRAM element 104. Thus, the drain electrode 118 of the transistor 102 and the first memory electrode 118 of the RRAM element 104 refer to the same feature and are denoted by the same reference numeral 118. Thus, in the present disclosure, the terms "drain electrode" and "first memory electrode" may be used interchangeably. For example, the term "drain electrode" is used when referring to the transistor, while the term "first memory electrode" is used when referring to the RRAM element. The first memory electrode may also be referred to as the bottom memory electrode.

[0032] The RRAM element 104 may further include a second memory electrode 120 and a switching layer 122. The second memory electrode 120 and the switching layer 122 may cover at least a portion of the first memory electrode 118. As Figure 1 shown, the switching layer 122 may include a first portion located on and in contact with the upper surface portion of the first memory electrode 118 and a second portion located on and in contact with the sidewall portion of the first memory electrode 118. In one embodiment of the present disclosure, the lowermost surface of the switching layer 122 is located below the upper surface of the first memory electrode 118. In another embodiment of the present disclosure, the switching layer 122 may have an uppermost surface that is substantially coplanar with the uppermost surface of the second gate dielectric layer 112. In yet another embodiment of the present disclosure, the switching layer 122 may include a substantially sharp corner. For example, the angle between the first portion and the second portion may be in the range of about 85 degrees to 95 degrees.

[0033] The second memory electrode 120 may conformally cover the switching layer 122. The second memory electrode 120 may also be referred to as the top memory electrode. In one embodiment of the present disclosure, the second memory electrode 120 may have a top surface that is substantially coplanar with the top surface of the second gate electrode 108. In another embodiment of the present disclosure, the second memory electrode 120 may include a conductive material such as, but not limited to, tantalum, hafnium, copper, silver, cobalt, tungsten, combinations thereof, or other conductive materials known to those skilled in the art. In another embodiment of the present disclosure, the second memory electrode 120 may include a bilayer stack of conductive materials such as, but not limited to, titanium / titanium nitride, etc. In yet another embodiment of the present disclosure, the thickness of the second memory electrode 120 may be in the range of 5 to 30 nm.

[0034] It should be understood that, for ease of manufacturing, the second memory electrode 120 may include the same conductive material as the second gate electrode 108 of the transistor 102. However, it should be understood that the second memory electrode 120 and the second gate electrode 108 may not necessarily be formed of the same conductive material or have the same thickness, although Figure 1 it is shown that they are formed of the same conductive material and have the same thickness.

[0035] In one embodiment of the present disclosure, the switching layer 122 may include a dielectric material such as, but not limited to, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, silicon oxide, combinations thereof, or other dielectric materials known to those skilled in the art. The switching layer 122 may be configured to have a certain thickness such that a relatively low voltage may be sufficient to switch the resistance of the switching layer 122. The voltage required for the operation of the RRAM element 104 may further vary with the technology node and the type of memory device being fabricated. In one embodiment of the present disclosure, the thickness of the switching layer 122 may be in the range of 2 to 10 nm.

[0036] It should be understood that, for ease of manufacturing, the switching layer 122 may include the same dielectric material as the second gate dielectric layer 112 of the transistor 102. However, it should be understood that the switching layer 122 and the second gate dielectric layer 112 may not necessarily be formed of the same dielectric material or have the same thickness, although Figure 1 it is shown that they are formed of the same dielectric material and have the same thickness.

[0037] The transistor 102 may be an access transistor for driving the RRAM element 104 and may be disposed in the back-end-of-line (BEOL) region of the semiconductor device. The transistor 102 in the BEOL region can shorten the wiring to the RRAM element 104, thereby advantageously reducing the delay in the programming speed of the memory device 100.

[0038] Figure 1A shows the filament formation region in the switching layer 122 of the semiconductor memory device 100 according to an embodiment of the present disclosure. The RRAM element 104 can be set by implementing the second memory electrode 120 at a voltage level higher than that of the first memory electrode 118 to switch the state of the switching layer 122 from the HRS state to the LRS state. For example, a sufficiently high voltage can be applied to the second memory electrode 120. An electric field can be generated in the region where the switching layer 122 contacts the first memory electrode 118, and one or more conductive paths formed by one or more conductive filaments 124 can be formed in the switching layer 122.

[0039] The RRAM element 104 can be reset by implementing the first memory electrode 118 at a voltage level higher than that of the second memory electrode 120 to disconnect one or more conductive filaments 124 in the switching layer 122, that is, to switch the state of the switching layer 122 from the LRS state to the HRS state (non-conductive). For example, a sufficiently high voltage can be applied to the source electrode 116, the first gate electrode 106, and / or the second gate electrode 108 to bias the voltage level of the drain electrode 118 to be higher than that of the second memory electrode 120. In another example, a negative voltage can be applied to the second memory electrode 120 such that the second memory electrode 120 is at a voltage level lower than that of the first memory electrode 118.

[0040] As Figure 1 shown in A, the conductive filaments 124 can be formed in the junctions / corners between the first and second portions of the switching layer 122 that contact the first memory electrode 118. Since the electric field formed around the junctions / corners of the first memory electrode 118 is stronger than that in the non-corner regions, the conductive filaments 124 can be substantially confined to the junctions / corners in the switching layer 122. Minimizing the variability of the positions where the conductive filaments 124 are formed is beneficial because the confinement reduces the randomness of the conductive filaments 124, thereby reducing the variability of the switching layer 122 in the HRS state. An uncontrolled distribution of the conductive filaments 124 can lead to undesirable process variations, such as high device-to-device variability and cycle-to-cycle variability.

[0041] Figure 1 B and Figure 1 C respectively show the drain electrode 118 spaced apart from the second gate dielectric layer 112 by a distance D1 and the source electrode 116 spaced apart from the second gate dielectric layer 112 by a distance D2 according to an embodiment of the present disclosure. It should be understood that the separation distances D1 and D2 do not have to be the same, although Figure 1 they are shown as being the same.

[0042] The second dielectric layer 112 and the switching layer 122 are dielectric layers that predominantly have similar material properties. When setting the RRAM element 104, one or more conductive paths may undesirably form in the second dielectric layer 112. By forming source and drain electrodes 116, 118 that are separated from the second gate dielectric layer 112, the likelihood of forming a conductive path in the second gate dielectric layer 112 is advantageously minimized.

[0043] Figures 2A to 2D is a cross-sectional view showing a method of forming Figure 1 the semiconductor memory device 100 in accordance with an embodiment of the present disclosure. Certain structures, for example, can be conventionally fabricated using known processes and techniques, and various aspects of the present disclosure can be implemented using the specifically disclosed processes and methods.

[0044] As used herein, "deposition technique" refers to the process of applying a material over another material (or substrate). Exemplary techniques for deposition include, but are not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or atomic layer deposition (ALD).

[0045] In addition, "patterning technique" includes depositing a material or photoresist as needed when forming the described patterns, structures, or openings, patterning, exposing, developing, etching, cleaning, and / or removing the material or photoresist. Exemplary examples of techniques for patterning include, but are not limited to, wet etching lithography processes, dry etching lithography processes, or direct patterning processes. These techniques can use mask sets and mask layers with dopants of the desired conductive type.

[0046] Figure 2A A memory device 100 is shown in accordance with an embodiment of the present disclosure, including a substrate 202 and a first dielectric layer 204 located over the substrate 202. The memory device 100 may further include a first region 206 defined to form a transistor and a second region 208 defined to form an RRAM element.

[0047] A conductive material can be deposited over the first dielectric layer 204 in the first and second regions 206, 208 using a deposition technique. The conductive material can be patterned in the first region 206 using a patterning technique to form a first gate electrode 106.

[0048] A dielectric material layer and an oxide semiconductor material layer can be sequentially deposited over the first gate electrode 106 and the first dielectric layer 204 using various deposition techniques. In one embodiment of the present disclosure, the dielectric material layer and the oxide semiconductor material layer can be deposited using an ALD process to conformally deposit them on the first gate electrode 106 and the first dielectric layer 204. The dielectric material layer and the oxide semiconductor material layer can be patterned using various patterning techniques to form the first gate dielectric layer 110 and the channel layer 114.

[0049] The first gate dielectric layer 110 and the channel layer 114 can cover over the first gate electrode 106 and can extend away from the first gate electrode 106 such that the first gate dielectric layer 110 can contact the upper surface of the first dielectric layer 204. The first gate dielectric layer 110 and the channel layer 114 can be confined within the first region 206 of the memory device 100 and can not extend into the second region 208.

[0050] Figure 2B A memory device 100 in accordance with an embodiment of the present disclosure after forming the source electrode 116 and the drain electrode 118 is shown. A conductive material can be deposited over the upper surfaces of the channel layer 114 and the first dielectric layer 204 using a deposition technique. The conductive material can be patterned using a patterning technique to form the source electrode 116 adjacent to the first side of the first gate electrode 106 and the drain electrode 118 adjacent to the second side of the first gate electrode 106; the second side is laterally opposite to the first side. The drain electrode 118 can extend into the second region 208 of the memory device 100.

[0051] It should be understood that the source and drain electrodes 116, 118 are discrete electrodes, and a portion of the upper surface of the channel layer 114 can be exposed after forming the source and drain electrodes 116, 118. The portion of the channel layer 114 exposed between the source and drain electrodes 116, 118 has a width W1.

[0052] In one embodiment of the present disclosure, the source and drain electrodes 116, 118 can have substantially coplanar upper surfaces. In another embodiment of the present disclosure, the source and drain electrodes 116, 118 can have upper surfaces that are higher than the upper surface of the channel layer 114. In another embodiment of the present disclosure, the source and drain electrodes 116, 118 can partially overlap the upper surface of the channel layer 114. In yet another embodiment of the present disclosure, the source and drain electrodes 116, 118 can partially overlap the uppermost surface of the channel layer 114.

[0053] Figure 2CFIG. 100 shows a memory device 100 after forming a second dielectric layer 210, a first opening 212 and a second opening 214 in the second dielectric layer 210 according to an embodiment of the present disclosure. The second dielectric layer 210 may be deposited over first and second regions 206, 208 of the memory device 100; particularly over the first dielectric layer 204, source and drain electrodes 116, 118, and channel layer 114. The second dielectric layer 210 may be deposited using a deposition technique. The first and second openings 212, 214 may be formed using a patterning technique.

[0054] The first opening 212 may be formed in the second dielectric layer 210 at the first region 206 of the memory device 100 and over the first gate electrode 106 between the source and drain electrodes 116, 118. The first opening 212 has a width W2 and exposes a portion of the uppermost surface of the channel layer 114 between the source and drain electrodes 116, 118. In one embodiment of the present disclosure, the width W2 is narrower than the width W1 such that a portion of the second dielectric layer 210 remains in contact with the channel layer 114 adjacent to the source and drain electrodes 116, 118.

[0055] The second opening 214 may be formed in the second dielectric layer 210 in the second region 208 of the memory device 100. The second opening 214 may partially expose the drain electrode 118; particularly the upper surface portion and sidewall portion of the drain electrode 118. In one embodiment of the present disclosure, the second opening 214 has a first region 214a with a width of W3 and a second region 214b with a width of W4; W4 is narrower than W3.

[0056] Figure 2D FIG. 100 shows a memory device 100 after forming a transistor 102 in the first region 206 and an RRAM element 104 in the second region 208 according to an embodiment of the present disclosure. A dielectric material may be deposited over the second dielectric layer 210 and within the first and second openings 212, 214. In one embodiment of the present disclosure, the dielectric material may be conformally deposited using a deposition technique (e.g., ALD process). A conductive material may be deposited over the dielectric material.

[0057] The dielectric material and the conductive material may be patterned using a patterning technique. The patterned dielectric material forms a second gate dielectric layer 112 of the transistor 102 and a switching layer 122 of the RRAM element 104. The patterned conductive layer forms a second gate electrode 108 of the transistor 102 and a second memory electrode 120 of the RRAM element 104.

[0058] It should be understood that for ease of manufacturing, the second gate dielectric layer 112, the switching layer 122, the second gate electrode 108, and the second memory electrode 120 can be patterned simultaneously. However, it should be understood that without departing from the spirit or scope of the present invention, the second gate dielectric layer 112, the switching layer 122, the second gate electrode 108, and the second memory electrode 120 can be formed separately.

[0059] The second gate dielectric layer 112 can line the first opening 212 and can extend above the upper surface of the second dielectric layer 210 in the first region 206 of the memory device 100. The second gate electrode 108 can cover the second gate dielectric layer 112 and can have sidewalls that are substantially coplanar with the sidewalls of the second gate dielectric layer 112. The second gate electrode 108 can completely fill or can incompletely fill the first opening 212 in the second dielectric layer 210.

[0060] The switching layer 122 can line the second opening 214 and can extend above the upper surface of the second dielectric layer 210 in the second region 208 of the memory device 100. The second memory electrode 120 can cover the switching layer 122 and can have sidewalls that are substantially coplanar with the sidewalls of the switching layer 122. The second memory electrode 120 can completely fill or can incompletely fill the second opening 214 in the second dielectric layer 210.

[0061] A third dielectric layer 216 can be deposited over the transistor 102 and the RRAM element 104 using deposition techniques. The first, second, and third dielectric layers 204, 210, 216 can be collectively referred to as an interlayer dielectric (ILD) layer 218. The ILD layer 218 can include a dielectric material suitable for at least electrically isolating the memory device 100 from adjacent conductive structures. In one embodiment of the present disclosure, the dielectric material can include, but is not limited to, silicon dioxide, tetraethyl orthosilicate (TEOS), or other dielectric materials known to those skilled in the art.

[0062] Figure 3 is a cross-sectional view of a semiconductor memory device 300 according to an alternative embodiment of the present disclosure. The memory device 300 is similar to Figure 1 the memory device 100 therein, so common features are labeled with the same reference numerals and need not be discussed. As Figure 3 shown, instead of source and drain electrodes 116, 118 separated from the second gate dielectric layer 112, the memory device 300 can have source and drain electrodes 316 and 318 that contact the second gate dielectric layer 112. It should be understood that the formation of an undesired conduction path in the second gate dielectric layer 112 can be minimized by optimizing the electrical operating conditions of the memory device 300.

[0063] Figure 4 is a cross-sectional view of a semiconductor memory device 400 according to an alternative embodiment of the present disclosure. The memory device 400 is similar to Figure 1 the memory device 100 in Figure 4 and thus common features are labeled with the same reference numerals and need not be discussed. As

[0064] Figure 5 shown, instead of the switching layer 122 having a first portion on the upper surface of the first memory electrode 118 and a second portion on the sidewall of the first memory electrode 118, the switching layer 422 of the RRAM element 404 may cover only the upper surface of the first memory electrode 118. Figure 1 and thus common features are labeled with the same reference numerals and need not be discussed. As Figure 5 shown, the RRAM element 504 may be shared between the first transistor 102 and the second transistor 502. The RRAM element 504 may include a switching layer 522 that is located on and in contact with the upper surface portion and the sidewall portion of the first memory electrode 118 (or the drain electrode 118 of the first transistor 102) and the upper surface portion and the sidewall portion of the first memory electrode 518 (or the drain electrode 518 of the second transistor 502). The switching layer 522 may have two substantially pointed corners that provide two filament formation regions, each filament formation region leading to each of the transistors 102, 502. By forming two memory devices with two transistors 102, 502 having a shared RRAM element 504, the configuration of the memory device 500 advantageously increases the device density of the memory device 500.

[0065] Figure 6 is a cross-sectional view of a semiconductor memory device 600 according to an alternative embodiment of the present disclosure. The memory device 600 is similar to Figure 5 the memory device 500 in Figure 6 and thus common features are labeled with the same reference numerals and need not be discussed. As

[0066] As presented in the above disclosure, a semiconductor memory device with improved device performance and a smaller footprint, and a method of forming the same are proposed. The memory device may include a double-gate transistor and an RRAM element. The double-gate transistor may include a gate electrode stack having a first gate electrode and a second gate electrode located above the first gate electrode, and may further include source and drain electrodes located on laterally opposite sides of the gate electrode stack.

[0067] The double-gate transistor provides a larger drive current, thereby at least doubling the access time of the memory device compared to a typical single-gate transistor. Due to providing a larger drive current, the overall size of the double-gate transistor can be advantageously reduced to provide a substantially similar drive current to set the RRAM element, thus saving valuable space on the semiconductor chip.

[0068] The RRAM element may be coupled to the double-gate transistor such that the drain electrode of the double-gate transistor also serves as the bottom electrode of the RRAM element. The RRAM element further includes a top electrode located above the bottom electrode and a switching layer interposed between the top electrode and the bottom electrode.

[0069] The switching layer may cover the upper surface and sidewall portions of the bottom electrode (or the drain electrode of the double-gate transistor), such that a filament formation region can be formed to form a substantially confined conductive filament when the RRAM element is set. The substantially confined conductive filament region advantageously reduces the variability of the switching layer in the HRS state and provides improved device-to-device and cycle-to-cycle control.

[0070] The semiconductor memory device may be fabricated in the BEOL region of the semiconductor device to achieve shorter wiring to the RRAM element, thereby further advantageously reducing the delay in the programming speed of the memory device. The semiconductor memory device may be compatible with a complementary metal oxide semiconductor (CMOS) process.

[0071] The semiconductor memory device disclosed in the present disclosure may be configured by a memory array having a cross configuration, a three-dimensional (3D) configuration, a combination thereof, or any other configuration known to those skilled in the art, thereby achieving a high-density architecture with a high parallel programming speed and low power consumption. For example, the 3D configuration may be achieved by separately repeating Figure 1 and Figures 3 to 6 the memory devices 100, 300, 400, 500, and 600 or combinations thereof in

[0072] The terms "top", "bottom", "above", "below", etc. (if any) in the specification and claims are for descriptive purposes and not necessarily for describing permanent relative positions. It should be understood that the terms so used are interchangeable under appropriate circumstances so that embodiments of the devices described herein, for example, can operate in orientations different from those shown or otherwise described herein.

[0073] In addition, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0074] Similarly, if a method is described herein as including a series of steps, the order of such steps presented herein is not necessarily the only order in which the steps can be performed, specific steps of the steps may be omitted and / or additional specific steps not described herein may be added to the method. In addition, the terms "comprising", "including", "having" and any variations thereof are intended to cover non-exclusive inclusion such that a process, method, article or device comprising a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article or device. The occurrence of the phrase "in an embodiment" herein does not necessarily all refer to the same embodiment.

[0075] In addition, unless otherwise specified, all numbers representing quantities, ratios, numerical characteristics of materials, reaction conditions, etc. used in the specification and claims should be understood to be modified by the term "about" in all cases.

[0076] Although several exemplary embodiments have been given in the above detailed description of the device, it should be understood that there are many variations. It should also be understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size or configuration of the device in any way. Instead, the above detailed description will provide a convenient guide for those skilled in the art to implement the exemplary embodiments of the device, and it will be understood that various changes can be made to the functions and arrangements of the elements described in the exemplary embodiments and the manufacturing methods without departing from the scope of the present disclosure stated in the appended claims.

Claims

1. A memory device, comprising: A double-gate transistor, the double-gate transistor comprising: A gate electrode stack, which includes a first gate electrode and a second gate electrode located above the first gate electrode; A first gate dielectric layer located above the first gate electrode, the first gate dielectric layer having a lowermost surface; A second gate dielectric layer between the first gate dielectric layer and the second gate electrode; A source electrode; and A drain electrode, wherein the source electrode and the drain electrode are adjacent to the gate electrode stack on opposite lateral sides of the gate electrode stack, and include lower surfaces that are substantially coplanar with the lowermost surface of the first gate dielectric layer; and A memory element adjacent to the double-gate transistor, wherein the memory element and the double-gate transistor share a common electrode.

2. The memory device according to claim 1, wherein the drain electrode is the common electrode shared with the memory element.

3. The memory device according to claim 1, wherein the second gate dielectric layer is conformal with the lower surface of the second gate electrode.

4. The memory device according to claim 1, wherein the double-gate transistor further includes a channel layer between the first gate dielectric layer and the second gate dielectric layer, and the channel layer is conformal with the upper surface of the first gate dielectric layer.

5. The memory device according to claim 4, wherein the source electrode and the drain electrode cover a portion of the channel layer and are separated from the second gate dielectric layer.

6. The memory device according to claim 1, wherein the memory element includes: A first memory electrode, wherein the first memory electrode is the common electrode shared with the double-gate transistor; A second memory electrode located above the first memory electrode; And A switching layer between the first memory electrode and the second memory electrode, wherein the switching layer is conformal with the lower surface of the second memory electrode.

7. The memory device according to claim 6, wherein a portion of the switching layer is in partial contact with the upper surface of the first memory electrode.

8. The memory device according to claim 6, wherein a portion of the switching layer is in partial contact with the sidewall of the first memory electrode.

9. The memory device according to claim 1, wherein the memory device is a resistive random access memory device.

10. A memory device, comprising: A double-gate transistor, the double-gate transistor comprising: A first gate electrode; A first gate dielectric layer located above the first gate electrode, the first gate dielectric layer having a lowermost surface; A channel layer located above the first gate electrode; A second gate dielectric layer located above the channel layer, the second gate dielectric layer having an uppermost surface; and A second gate electrode located above the second gate dielectric layer, wherein the first gate electrode and the second gate electrode form a gate electrode stack; A source electrode adjacent to a first side of the gate electrode stack; and A drain electrode adjacent to a second side of the gate electrode stack, the second side being laterally opposite to the first side, wherein the source electrode and the drain electrode have lower surfaces substantially coplanar with the lowermost surface of the first gate dielectric layer; and A memory element adjacent to the double-gate transistor, the memory element comprising: A first memory electrode; A switching layer coupled to the first memory electrode, wherein the switching layer has an uppermost surface substantially coplanar with the uppermost surface of the second gate dielectric layer; and A second memory electrode coupled to the switching layer, wherein the first memory electrode is the drain electrode of the double-gate transistor.

11. The memory device according to claim 10, wherein the second gate electrode has an uppermost surface substantially coplanar with the uppermost surface of the second memory electrode.

12. The memory device according to claim 10, wherein the switching layer of the memory element has a lowermost surface located below the upper surface of the first memory electrode.

13. A method of forming a memory device, comprising: Forming a first gate electrode; Forming a second gate electrode above the first gate electrode, wherein the first gate electrode and the second gate electrode form a gate electrode stack; Forming a first gate dielectric layer above the first gate electrode, the first gate dielectric layer having a lowermost surface; Forming a second gate dielectric layer between the first gate dielectric layer and the second gate electrode; Forming a source electrode; And Forming a drain electrode, wherein the source electrode and the drain electrode are adjacent to the gate electrode stack on laterally opposite sides of the gate electrode stack and include lower surfaces substantially coplanar with the lowermost surface of the first gate dielectric layer, wherein the gate electrode stack, the first gate dielectric layer, the second gate dielectric layer, the source electrode and the drain electrode form a double-gate transistor; And Forming a memory element adjacent to the double-gate transistor, the memory element having a first memory electrode and a second memory electrode above the first memory electrode, wherein the first memory electrode is a common electrode shared with the double-gate transistor.

14. The method according to claim 13, wherein the drain electrode is the common electrode.

15. The method according to claim 13, wherein the switching layer of the memory element is formed simultaneously with the second gate dielectric layer, and the switching layer has an uppermost surface substantially coplanar with the uppermost surface of the second gate dielectric layer.

16. The method according to claim 15, wherein forming the switching layer includes forming a first portion of the switching layer on an upper surface portion of the first memory electrode and a second portion on a sidewall portion of the first memory electrode.

17. The method according to claim 13, wherein the second memory electrode is formed simultaneously with the second gate electrode, wherein the second memory electrode has an uppermost surface substantially coplanar with the uppermost surface of the second gate electrode.

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