Multi-threshold logic power device and preparation method thereof

Abstract

The present invention provides a multi-threshold logic power device and a preparation method thereof. Through the patterned design of a contact mask, a contact structure array having the same common trench gate structure can be formed, and the edges of the second conductive type contact parts of the contact structures in the contact structure array can have different lateral spacings from the edges of the channels, so that a multi-threshold logic state can be realized, and thus the power device can have a multi-threshold logic state to store information through an external circuit. The present invention can prepare a multi-threshold logic power device having different threshold voltages and the ability to store information without adding any additional process steps, and the preparation process is simple, the cost is low, and the application range is wide. The number of threshold voltages can be flexibly designed to store multi-bit digital information or analog information in the power device. Power MOSFETs and IGBTs with built-in multi-threshold voltages can be used in large current applications and have the ability to store information.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology and relates to a multi-threshold logic power device and a preparation method thereof. Background Art

[0002] Multiple-valued logic (MVL) has more than two possible thresholds to facilitate logic calculations. Its main applications are divided into two categories: the first category is to use multi-valued logic to effectively solve binary problems; the second category is to use more than two discrete-level signals (multi-bit systems) to design electronic circuits, such as multi-valued memories, arithmetic circuits, field-programmable gate arrays (FPGAs), etc.

[0003] Among them, MVL circuits have been implemented in bipolar technologies such as integrated interconnect logic (IIL), emitter coupled logic (ECL), metal oxide semiconductor (MOS) and charge coupled device (CCD). The manufactured MVL devices include multi-level transistors (MOSFET, FINFET), multi-threshold memories (Flash, DRAM, NAND, RRAM), single electron transistors (SET), carbon nanotube transistors (CNTFET), etc.

[0004] In the prior art, see Figure 1 and Figure 2 ,in Figure 2 Indicated Figure 1 The circuit connection diagram of the multi-threshold logic transistor in FIG. The structure of the multi-threshold logic transistor is actually composed of multiple transistors sharing the same gate. The multi-threshold logic transistor includes a shared gate Gate and three threshold voltages Vt0, Vt1 and Vt2. The multi-threshold logic transistor can process four levels of logic signals (or 2 bits), namely 00, 01, 10 and 11.

[0005] However, although multi-threshold logic transistors are more efficient and faster than binary logic transistors, the process of forming transistors with multiple Vt in existing multi-threshold logic transistors is complex and costly. In addition, currently, multi-threshold logic transistors with "built-in" multi-level or multi-Vt are mainly used in multi-level logic and storage to achieve more efficient data calculation and high-density storage, but there are few reports on the application of "built-in" multi-level transistors in the field of power devices.

[0006] Therefore, it is necessary to provide a multi-threshold logic power device with the ability to store information and a preparation method thereof. Summary of the invention

[0007] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a multi-threshold logic power device with information storage capability and a preparation method, so as to solve the problems of complex preparation process, high cost and narrow application field of multi-threshold logic devices in the prior art.

[0008] To achieve the above-mentioned purpose and other related purposes, the present invention provides a multi-threshold logic power device capable of storing information, the multi-threshold logic power device comprising:

[0009] a first conductivity type epitaxial layer;

[0010] A second conductivity type well region, wherein the second conductivity type well region is located in the first conductivity type epitaxial layer;

[0011] a first conductivity type source region, the first conductivity type source region being located in the second conductivity type well region;

[0012] A trench gate structure, the trench gate structure comprising a gate dielectric layer and a gate conductive layer, the trench gate structure being located in the first conductive type epitaxial layer and penetrating the first conductive type source region and the second conductive type well region;

[0013] A contact structure, wherein the contact structure penetrates the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the contact structure constitutes a contact structure array, the contact structure array has the same common trench gate structure, and in the contact structure array, the edge of the second conductive type contact portion and the edge of the channel have different lateral spacings.

[0014] Optionally, in the contact structure array, the second conductive type contact portions have different doping concentrations.

[0015] Optionally, in the contact structure array, the doping concentration of the second conductive type contact portion decreases as the lateral spacing increases.

[0016] Optionally, the contact structure includes a second conductivity type contact portion located in the second conductivity type well region and a metal contact portion penetrating the first conductivity type source region and contacting the second conductivity type contact portion.

[0017] Optionally, the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure includes one or a combination of a rectangle and a square.

[0018] Optionally, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.

[0019] Optionally, the multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.

[0020] The present invention also provides a method for preparing a multi-threshold logic power device having the ability to store information, comprising the following steps:

[0021] A semiconductor substrate is provided, the semiconductor substrate comprising a first conductive type epitaxial layer, a second conductive type well region, a first conductive type source region and a trench gate structure; wherein the second conductive type well region is located in the first conductive type epitaxial layer, the first conductive type source region is located in the second conductive type well region, the trench gate structure comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is located in the first conductive type epitaxial layer and penetrates the first conductive type source region and the second conductive type well region;

[0022] A contact mask is formed on the semiconductor substrate, and a contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure penetrates the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the formed contact structures constitute a contact structure array, the contact structure array has the same common trench gate structure, and in the contact structure array, the edge of the second conductive type contact portion and the edge of the channel have different lateral spacings.

[0023] Optionally, in the contact structure array, a plurality of second conductive type contact portions formed have different doping concentrations; in the contact structure array, a doping concentration of the second conductive type contact portions formed decreases as the lateral spacing increases.

[0024] Optionally, the step of forming the contact structure includes:

[0025] Etching the first conductive type source region through a contact mask to form a contact groove penetrating the first conductive type source region;

[0026] Implanting second conductivity type impurities into the second conductivity type well region through the contact mask to form a second conductivity type contact portion;

[0027] A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion.

[0028] Optionally, the first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type; the prepared multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET, so as to store digital information in the threshold of the multi-threshold logic power device.

[0029] Optionally, the step of preparing the semiconductor substrate comprises:

[0030] forming a first conductivity type epitaxial layer;

[0031] forming a trench gate structure in the first conductivity type epitaxial layer, wherein the trench gate structure comprises a gate dielectric layer and a gate conductive layer;

[0032] Forming a second conductivity type well region in the first conductivity type epitaxial layer between the trench gate structures through a well region mask;

[0033] A first conductive type source region is formed in the second conductive type well region through a source region mask.

[0034] As described above, the multi-threshold logic power device with information storage capability and the preparation method of the present invention have the following beneficial effects:

[0035] When preparing the contact structure, a contact structure array having the same common trench gate structure can be formed through the patterned design of the contact mask, and the edges of the second conductive type contact portions of the contact structures in the contact structure array can have different lateral spacings from the edges of the channels, thereby realizing multi-threshold logic states, and thereby realizing a power device having multi-threshold logic states to store information through an external circuit; the present invention can prepare a multi-threshold logic power device having different threshold voltages Vt and the ability to store information without adding any additional process steps, and the preparation process is simple, the cost is low, and the application range is wide; the number of threshold voltages Vt can be flexibly designed to store multi-bit digital information or analog information in the power device; power MOSFETs and IGBTs with built-in multi-threshold voltages Vt can be used in high current applications and have the ability to store information. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Shown is a schematic structural diagram of a multi-threshold logic transistor in the prior art.

[0037] Figure 2 Display as Figure 1 Schematic diagram of the circuit connection of the multi-threshold logic transistor in .

[0038] Figure 3 Shown is a schematic diagram of the process flow for preparing a multi-threshold logic power device in an embodiment of the present invention.

[0039] Figure 4 Shown is a schematic diagram of the structure of a multi-threshold logic power device in an embodiment of the present invention.

[0040] Figure 5 Shown is a partial top view structural schematic diagram of a multi-threshold logic power device in an embodiment of the present invention.

[0041] Figure 6 It is a schematic diagram of an enlarged structure of the lateral distance between the second conductive type contact portion and the edge of the channel in an embodiment of the present invention.

[0042] Figure 7 Shown is a circuit connection schematic diagram of a multi-threshold logic power device in an embodiment of the present invention.

[0043] Figure 8 It is a schematic diagram showing the simulation relationship between the threshold voltage Vt and the lateral spacing in an embodiment of the present invention.

[0044] Component number description

[0045] 101 first conductive type substrate

[0046] 102 first conductivity type epitaxial layer

[0047] 103 Trench Gate Structure

[0048] 1031 Gate dielectric layer

[0049] 1032 gate conductive layer

[0050] 104 second conductivity type well region

[0051] 105 first conductivity type source region

[0052] 106 second conductive type contact portion

[0053] 107 Channel

[0054] 108 interlayer dielectric layer

[0055] 1091 Source Metal Layer

[0056] 1092 Gate Metal Layer

[0057] 1093 Drain Metal Layer

[0058] A Contact structure array

[0059] D Horizontal spacing DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0062] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0063] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0064] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] like Figure 3As shown, the present embodiment provides a method for preparing a multi-threshold logic power device, wherein, when preparing the contact structure, a contact structure array having the same common trench gate structure can be formed through the patterning design of the contact mask, and the edges of the second conductive type contact portions of the contact structures in the contact structure array can have different lateral spacings from the edges of the channels, thereby realizing multi-threshold logic states, thereby realizing a power device having multi-threshold logic states to store information through an external circuit; the present invention can prepare a multi-threshold logic power device having different threshold voltages Vt and the ability to store information without adding any additional process steps, and the preparation process is simple, the cost is low, and the application range is wide; the number of threshold voltages Vt can be flexibly designed and can be used to store multi-bit digital information or analog information; power MOSFETs and IGBTs with built-in multi-threshold voltages Vt can be used in high current situations and have the ability to store information.

[0066] As an example, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.

[0067] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is not limited to this. In another embodiment, the first conductivity type may also be p-type and the second conductivity type may be n-type, without excessive restriction here.

[0068] As an example, the prepared multi-threshold logic power device may include a multi-threshold logic MOSFET or a multi-threshold logic IGBT, etc., wherein the multi-threshold logic MOSFET may include a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET, etc., to store digital information in the threshold of the multi-threshold logic power device.

[0069] Specifically, the specific type and structure of the multi-threshold logic power device can be prepared by preparing the relevant functional layers according to the needs, and no excessive restrictions are made here. Figure 4 , a multi-threshold logic VDMOSFET is taken as an example for further description, but the type of the multi-threshold logic power device is not limited thereto.

[0070] The structure and preparation method of the multi-threshold logic power device of this embodiment are further explained below in conjunction with the accompanying drawings.

[0071] First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a first conductive type epitaxial layer 102, a second conductive type well region 104, a first conductive type source region 105 and a trench gate structure 103; wherein the second conductive type well region 104 is located in the first conductive type epitaxial layer 102, the first conductive type source region 105 is located in the second conductive type well region 104, the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032, the trench gate structure 103 is located in the first conductive type epitaxial layer 102, and penetrates the first conductive type source region 105 and the second conductive type well region 104, thereby forming a vertical double channel 107, which can be understood Figure 4 Only one device unit of the multi-threshold logic power device is illustrated. In actual applications, the multi-threshold logic power device may include a plurality of identical or different device units that are repeatedly arranged.

[0072] As an example, the steps of preparing the semiconductor substrate include:

[0073] Providing a first conductive type substrate 101;

[0074] forming a first conductivity type epitaxial layer 102 on the first conductivity type substrate 101;

[0075] forming a trench gate structure 103 in the first conductivity type epitaxial layer 102 , wherein the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032 ;

[0076] Forming a second conductivity type well region 104 in the first conductivity type epitaxial layer 102 between the trench gate structures 103 through a well region mask;

[0077] A first conductivity type source region 105 is formed in the second conductivity type well region 104 through a source region mask.

[0078] The above steps and structures for forming the semiconductor substrate can be flexibly changed according to specific needs and are not limited thereto.

[0079] Specifically, first, the first conductive type substrate 101 is provided. The material of the first conductive type substrate 101 can be doped semiconductor materials such as silicon (Si), silicon germanium (SiGe), gallium nitride (GaN) or silicon carbide (SiC), and the specific type is not overly limited here.

[0080] Next, the first conductivity type epitaxial layer 102 is formed on the first conductivity type substrate 101 by epitaxial (epi) growth.

[0081] Next, the trench gate structure 103 is formed in the first conductivity type epitaxial layer 102 . The trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032 .

[0082] In this embodiment, the trench gate structure 103 can reduce the unit area of ​​the power device, and the steps of preparing the trench gate structure 103 may include:

[0083] Etching the first conductivity type epitaxial layer 102 to form a gate trench;

[0084] Using a thermal oxygen growth process, a gate dielectric layer 1031 is grown on the surface of the gate trench to cover the bottom and sidewalls of the gate trench;

[0085] Polysilicon is deposited in the gate trench to form the gate conductive layer 1032 .

[0086] The method for preparing the trench gate structure 103 is not limited thereto, and a split gate structure may be selected as required. The specific preparation process and structure are not limited here.

[0087] Then, if Figure 4 and Figure 5 , preparing the contact structure, comprising the following steps:

[0088] A contact mask is formed on the semiconductor substrate, and the contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure penetrates the first conductive type source region 105 to contact the second conductive type well region 104, and the contact structure includes a second conductive type contact portion 106; wherein the formed contact structure constitutes a contact structure array A, the contact structure array A has the same common trench gate structure 103, and in the contact structure array A, the edge of the second conductive type contact portion 106 and the edge of the channel 107 have different lateral spacings D.

[0089] Specifically, a mask material layer may be deposited on the surface of the semiconductor substrate, wherein the deposition method may include chemical vapor deposition, and the mask material layer may be a silicon dioxide layer, but is not limited thereto.

[0090] Next, a graphic photoresist layer defining the contact structure can be formed on the surface of the mask material layer through a photolithography process, and the mask material layer can be dry-etched using the photoresist layer as an etching mask through a dry etching process to form a contact mask having the contact structure pattern.

[0091] Next, second conductivity type impurities are implanted into the first conductivity type source region 105 through the patterned contact mask to form the contact structure in contact with the second conductivity type well region 104 .

[0092] In this embodiment, the contact structure is formed by injecting second conductivity type impurities into the first conductivity type source region 105 to short the first conductivity type source region 105, so that the contact structure formed is directly the second conductivity type contact portion 106, but the type and structure of the contact structure are not limited thereto, for example, the contact structure may also adopt a trench contact structure, wherein the step of forming the trench contact structure may include:

[0093] Etching the first conductive type source region 105 through the contact mask to form a contact groove penetrating the first conductive type source region 105;

[0094] Implanting second conductivity type impurities into the second conductivity type well region 104 through the contact mask to form a second conductivity type contact portion 106;

[0095] A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion 106 .

[0096] The trench contact structure can be used to form a second conductive type contact portion 106 located in the second conductive type well region 104 and a metal contact portion, such as metal W, that penetrates the first conductive type source region 105 and contacts the second conductive type contact portion 106, so as to further reduce the on-resistance and reduce the area of ​​the traditional planar contact structure. No excessive restrictions are imposed on the specific selection of the contact structure.

[0097] In this embodiment, a plurality of contact structure arrays A can be formed by patterning the contact mask. Figure 5 As shown, in the contact structure array A, the plurality of contact structures have the same common trench gate structure 103, and the edges of the contact structures and the edges of the channels 107 have different lateral spacings D, which can realize multi-threshold logic states, such as Figure 6As shown, the power device can be realized to have multiple threshold logic states to store information through an external circuit. This embodiment can prepare the multi-threshold logic power device with different threshold voltages Vt and the ability to store information without adding any additional process steps. The preparation process is simple, the cost is low, and the application range is wide; and the number of the threshold voltages Vt can be flexibly designed to store multi-bit digital information or analog information in the power device; the power MOSFET and IGBT with built-in multiple threshold voltages Vt can be used in large current applications and have the ability to store information.

[0098] As an example, in the contact structure array A, the plurality of second conductive type contact portions 106 formed may have different doping concentrations.

[0099] Specifically, through different doping concentrations, the effect of forming a multi-threshold voltage Vt can be further enhanced. The specific doping amount is not limited here. The type of doping element of the second conductive type contact portion 106 may include B, but is not limited to this. It can also be a doping element with an opposite conductive type such as P, As, Sb, etc., which can be selected according to the type of conductive type and requirements.

[0100] As an example, in the contact structure array A, the doping concentration of the second conductive type contact portion 106 formed decreases as the lateral spacing D increases, so as to further enhance the effect of forming a multi-threshold voltage Vt as needed, but is not limited to this. For example, the doping concentration of the second conductive type contact portion 106 may also increase or change randomly as the lateral spacing D increases.

[0101] As an example, in the contact structure array A, the distribution of the second conductive type contact portions 106 may be discrete, that is, randomly distributed as required, but is not limited thereto.

[0102] As an example, the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure 103 includes one or a combination of a rectangle and a square; the size, morphology, etc. of the contact structure and the trench gate structure 103 are not excessively restricted here and can be selected as needed.

[0103] As an example, the lateral spacing D between the edge of the second conductive type contact portion 106 and the edge of the channel 107 in the contact structure may range from 0 μm to 3 μm, but is not limited thereto and may be set as required.

[0104] As an example, the steps of forming an interlayer dielectric layer 108, a source metal layer 1091, a gate metal layer 1092 and a drain metal layer 1093 may also be included to form the multi-threshold logic VDMOSFET. The order of the steps of forming the multi-threshold logic VDMOSFET may be selected according to specific needs and is not overly limited here.

[0105] As an example, the method further includes forming a first conductivity type buffer layer on the lower surface of the first conductivity type epitaxial layer 102 .

[0106] Specifically, the doping concentration of the first conductive type buffer layer can be between the doping concentrations of the first conductive type substrate 101 and the first conductive type epitaxial layer 102, so as to prevent the impurity atoms of the first conductive type substrate 101 from diffusing into the first conductive type epitaxial layer 102 during the high-temperature process in the multi-threshold logic VDMOSFET through the first conductive type buffer layer, thereby avoiding the increase in the doping concentration of the first conductive type epitaxial layer 102 and causing a decrease in the breakdown voltage, and the first conductive type substrate 101 can be used to solve the problem of tail current when the device is turned off.

[0107] This embodiment also provides a method for preparing a multi-threshold logic IGBT. Figure 4 The main difference between the preparation of the multi-threshold logic VDMOSFET in the embodiment is that a step of preparing an additional second conductive type injection layer is added between the drain metal layer 1093 and the first conductive type epitaxial layer 102. Specifically, the first conductive type substrate 101 can be removed by CMP, and the second conductive type impurities can be injected to form the second conductive type injection layer, but it is not limited thereto.

[0108] See also Figure 7 , which illustrates a circuit connection diagram of the multi-threshold logic power device. In this embodiment, the multi-threshold logic power device is tested through simulation. The results are shown in the following table and Figure 8 .

[0109]

[0110] It should be noted that, in the above table, a negative value represents the value of the lateral spacing D set when the second conductive type contact portion 106 approaches the channel 107 from the reference position, and a positive value represents the value of the lateral spacing D set when the second conductive type contact portion 106 is away from the reference position from the channel 107. Figure 6 From the above table and Figure 8 It can be seen that when the lateral distance D is smaller, the threshold voltage Vt is higher.

[0111] like Figure 4 The present embodiment also provides a multi-threshold logic power device with the ability to store information. The multi-threshold logic power device can be prepared using the above method, but is not limited to this. The preparation, material, etc. of the multi-threshold logic power device can be set as needed, and no excessive restrictions are made here. The multi-threshold logic power device described in the present embodiment is directly prepared using the above preparation method, so the material, preparation process, etc. of the multi-threshold logic power device are not described here.

[0112] Specifically, the multi-threshold logic power device includes a first conductivity type epitaxial layer 102 , a second conductivity type well region 104 , a first conductivity type source region 105 , a trench gate structure 103 and a contact structure. In which, the second conductive type well region 104 is located in the first conductive type epitaxial layer 102, the first conductive type source region 105 is located in the second conductive type well region 104, the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032, the trench gate structure 103 is located in the first conductive type epitaxial layer 102, and passes through the first conductive type source region 105 and the second conductive type well region 104, the contact structure passes through the first conductive type source region 105 to contact the second conductive type well region 104, and the contact structure includes a second conductive type contact portion 106; wherein the contact structure formed constitutes a contact structure array A, the contact structure array A has the same common trench gate structure 103, and there are different lateral spacings D between the edge of the second conductive type contact portion 106 and the edge of the channel 107 in the contact structure array A.

[0113] As an example, in the contact structure array A, the second conductive type contact portions 106 have different doping concentrations.

[0114] Specifically, through different doping concentrations, the effect of forming a multi-threshold voltage Vt can be further enhanced. The specific doping amount is not limited here. The type of doping element of the second conductive type contact portion 106 may include B, but is not limited to this. It can also be a doping element with an opposite conductive type such as P, As, Sb, etc., which can be selected according to the type of conductive type and requirements.

[0115] As an example, in the contact structure array A, the doping concentration of the second conductive type contact portion 106 decreases as the lateral spacing D increases, so as to further enhance the effect of forming a multi-threshold voltage Vt as needed, but is not limited to this. For example, the doping concentration of the second conductive type contact portion 106 may also increase or change randomly as the lateral spacing D increases.

[0116] As an example, in the contact structure array A, the distribution of the second conductive type contact portions 106 may be discrete, that is, randomly distributed as required, but is not limited thereto.

[0117] As an example, the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure 103 includes one or a combination of a rectangle and a square; the size, morphology, etc. of the contact structure and the trench gate structure 103 are not excessively restricted here and can be selected as needed.

[0118] As an example, the contact structure includes a second conductive type contact portion 106 located in the second conductive type well region 104 and a metal contact portion penetrating the first conductive type source region 105 and contacting the second conductive type contact portion 106 to provide a trench contact structure, but is not limited thereto.

[0119] As an example, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.

[0120] As an example, the multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.

[0121] In summary, the multi-threshold logic power device with information storage capability and the preparation method of the present invention, when preparing the contact structure, can form a contact structure array with the same common trench gate structure through the patterned design of the contact mask, and can make the edge of the second conductive type contact portion of the contact structure in the contact structure array have different lateral spacings from the channel edge, so as to realize multi-threshold logic states, so that the power device can have multi-threshold logic states to store information through an external circuit; the present invention can prepare multi-threshold logic power devices with different threshold voltages Vt and information storage capabilities without adding any additional process steps, and the preparation process is simple, the cost is low, and the application range is wide; the number of threshold voltages Vt can be flexibly designed to store multi-bit digital information or analog information in the power device; power MOSFET and IGBT with built-in multi-threshold voltages Vt can be used in large current occasions and have the ability to store information.

[0122] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A multi-threshold logic power device, characterized in that, the multi-threshold logic power device comprises: a first-conductivity-type epitaxial layer; a second-conductivity-type well region, which is located within the first-conductivity-type epitaxial layer; a first-conductivity-type source region, which is located within the second-conductivity-type well region; a trench gate structure, which comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is located within the first-conductivity-type epitaxial layer and penetrates through the first-conductivity-type source region and the second-conductivity-type well region; a contact structure, the contact structure penetrates through the first-conductivity-type source region to contact with the second-conductivity-type well region, and the contact structure comprises a second-conductivity-type contact portion; wherein, the contact structure forms a contact structure array, the contact structure array has the same common trench gate structure, and there are different lateral spacings between the edge of the second-conductivity-type contact portion and the channel edge in the contact structure array; in the contact structure array, the doping concentration of the second-conductivity-type contact portion decreases as the lateral spacing increases.

2. The multi-threshold logic power device according to claim 1, characterized in that: the contact structure comprises a second-conductivity-type contact portion located within the second-conductivity-type well region and a metal contact portion that penetrates through the first-conductivity-type source region and contacts with the second-conductivity-type contact portion.

3. The multi-threshold logic power device according to claim 1, characterized in that: the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure includes one or a combination of a rectangle and a square.

4. The multi-threshold logic power device according to claim 1, characterized in that: the first-conductivity-type is n-type and the second-conductivity-type is p-type; or the first-conductivity-type is p-type and the second-conductivity-type is n-type.

5. The multi-threshold logic power device according to claim 1, characterized in that: the multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein, the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold value of the multi-threshold logic power device.

6. A preparation method of a multi-threshold logic power device, characterized in that, comprises the following steps: providing a semiconductor substrate, the semiconductor substrate includes a first-conductivity-type epitaxial layer, a second-conductivity-type well region, a first-conductivity-type source region and a trench gate structure; wherein, the second-conductivity-type well region is located within the first-conductivity-type epitaxial layer, the first-conductivity-type source region is located within the second-conductivity-type well region, the trench gate structure comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is located within the first-conductivity-type epitaxial layer and penetrates through the first-conductivity-type source region and the second-conductivity-type well region; A contact mask is formed on the semiconductor substrate, and a contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure penetrates the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the formed contact structures constitute a contact structure array, the contact structure array has the same common trench gate structure, and in the contact structure array, the edge of the second conductive type contact portion and the edge of the channel have different lateral spacings; in the contact structure array, the doping concentration of the formed second conductive type contact portion decreases as the lateral spacing increases.

7. The preparation method according to claim 6, It is characterized in that The steps of forming the contact structure include: Etching the first conductive type source region through a contact mask to form a contact groove penetrating the first conductive type source region; Implanting second conductivity type impurities into the second conductivity type well region through the contact mask to form a second conductivity type contact portion; A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion.

8. The preparation method according to claim 6, Features: The first conductivity type is n-type and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type; the prepared multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET, so as to store digital information in the threshold of the multi-threshold logic power device.

9. The preparation method according to claim 6, It is characterized in that The steps of preparing the semiconductor substrate include: forming a first conductivity type epitaxial layer; forming a trench gate structure in the first conductivity type epitaxial layer, wherein the trench gate structure comprises a gate dielectric layer and a gate conductive layer; Forming a second conductivity type well region in the first conductivity type epitaxial layer between the trench gate structures through a well region mask; A first conductive type source region is formed in the second conductive type well region through a source region mask.

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