Non-volatile memory device

Abstract

A non-volatile memory device can include a substrate, a first floating gate, a second floating gate, a third floating gate, and a fourth floating gate. The substrate can include an active region. The first through fourth floating gates can be formed on the substrate. The first through fourth floating gates can be arranged radially to partially overlap the active region. The first floating gate and the third floating gate can face each other along a first direction. The first floating gate and the third floating gate can have asymmetric planar shapes. The first floating gate and the second floating gate can face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate can have asymmetric planar shapes. The third floating gate and the fourth floating gate can face each other along the second direction. The third floating gate and the fourth floating gate can have asymmetric planar shapes. The fourth floating gate and the second floating gate can face each other along the first direction. The fourth floating gate and the second floating gate can have asymmetric planar shapes.

Description

Technical Field

[0001] The technology and implementation methods disclosed in this patent document generally relate to a semiconductor device. Background Technology

[0002] The growing trend of using mobile devices to access information anytime, anywhere has increased the demand for highly integrated semiconductor devices. System-on-a-Chip (SoC) is a technology that integrates multiple computer components into a single semiconductor device. SoC technology makes it possible to manufacture both memory and non-memory components on a single chip.

[0003] Embedded memory is a hot topic in many industries. Embedded memory is on-chip memory integrated into a System-on-a-Chip (SoC), enabling the logic circuitry on the SoC to perform its intended functions. An example of embedded memory is electrically erasable programmable read-only memory (EEPROM). EEPROM, similar to read-only memory (ROM), retains data without power and can be erased and reprogrammed by applying a high voltage. Summary of the Invention

[0004] The disclosed technology relates to a non-volatile memory device with improved reliability.

[0005] In an exemplary embodiment of this disclosure, a non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate, and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be arranged radially to partially overlap with the active region. The first and third floating gates may face each other in a first direction. The first and third floating gates may have an asymmetrical planar shape. The first and second floating gates may face each other in a second direction substantially perpendicular to the first direction. The first and second floating gates may have an asymmetrical planar shape. The third and fourth floating gates may face each other in the second direction. The third and fourth floating gates may have an asymmetrical planar shape. The fourth and second floating gates may face each other in the first direction. The fourth and second floating gates may have an asymmetrical planar shape.

[0006] In an exemplary embodiment of this disclosure, a non-volatile memory device may include a first well region and a second well region, a device isolation layer, a first select gate and a second select gate, and a first floating gate and a second floating gate. The first well region and the second well region may be formed on a substrate. The first well region and the second well region may have complementary conductivity types. The first well region and the second well region may be arranged parallel to each other along a first direction. A device isolation region may be formed on the substrate to define a first active region in the first well region and a second active region in the second well region. The first select gate and the second select gate may be formed on the substrate. The first select gate and the second select gate may overlap with the first active region. The first select gate and the second select gate may be arranged parallel to each other along a second direction substantially perpendicular to the first direction. The first select gate and the second select gate may have a linear shape extending in the first direction. The first floating gate and the second floating gate may be arranged adjacent to the first select gate and the second select gate, respectively. The first floating gate and the second floating gate may overlap with the first active region and the second active region, respectively. The first floating gate and the second floating gate may face each other along the second direction. The first floating gate and the second floating gate may have an asymmetrical planar shape.

[0007] In an example embodiment, the non-volatile memory device may further include a third well region, a third active region, and a third floating gate and a fourth floating gate. The third well region may have a conductivity type substantially the same as that of the first well region. The third active region may be defined in the third well region by a device isolation layer. The third active region may overlap with the first select gate and the second select gate. The third floating gate and the fourth floating gate may be arranged adjacent to the first select gate and the second select gate, respectively. The third floating gate and the fourth floating gate may face each other along a second direction. The third floating gate and the fourth floating gate may have an asymmetrical planar shape along the second direction. The first floating gate and the third floating gate may have an asymmetrical planar shape along a first direction. The second floating gate and the fourth floating gate may have an asymmetrical planar shape along the first direction.

[0008] Based on some embodiments of the disclosed technology, the multiple floating gates overlapping the active region can have an asymmetrical planar shape to prevent uneven interconnection ratios relative to the individual floating gates. Therefore, the non-volatile memory device can have a uniform threshold voltage, sufficient read margin, and improved operational reliability.

[0009] In addition, the gap between the gate and the active region, as well as the gap between the floating gate, can be wide enough to further improve operational reliability. Attached Figure Description

[0010] Figure 1These are examples of unit cells of non-volatile memory devices based on some implementations of the disclosed technology.

[0011] Figure 2A and Figure 2B These are examples of unit cells of a non-volatile memory device based on some implementations of the disclosed technology.

[0012] Figure 3 These are examples of cell arrays of non-volatile memory devices based on some implementations of the disclosed technology.

[0013] Figure 4A It is along Figure 3 The cross-sectional view taken by line A-A' in the diagram.

[0014] Figure 4B It is along Figure 3 The cross-sectional view taken by line B-B' in the diagram. Detailed Implementation

[0015] Features of the technology disclosed in this patent document are described with reference to the accompanying drawings, using examples of image sensing devices. Although some embodiments of the disclosed technology will be discussed, the disclosed technology can be implemented in various ways beyond the details of the examples described herein.

[0016] The disclosed technology can be implemented in some embodiments to provide a non-volatile memory device as an embedded memory, which can be used as an analog trimming device in a SoC device including digital and analog circuits or as internal memory for storing instructions and data used by the SoC device.

[0017] In some implementations, the first conductivity type and the second conductivity type can be N-type and P-type, respectively, or vice versa. That is, non-volatile memory devices based on some example embodiments of the disclosed technology may include N-type channels or P-type channels. In one example, the first conductivity type and the second conductivity type are P-type and N-type, respectively, and the non-volatile memory device has an N-type channel.

[0018] In some implementations, the first and second directions can be substantially perpendicular to each other. For example, in XY coordinates, the first direction D1 can be the X direction, and the second direction D2 can be the Y direction.

[0019] Figure 1 These are examples of unit cells of non-volatile memory devices based on some implementations of the disclosed technology. For illustrative purposes, Figure 1 This shows two unit cells that share a first active region and a second active region. Figure 2A and Figure 2BThese are examples of unit cells of a non-volatile memory device based on some implementations of the disclosed technology.

[0020] In some implementations, a non-volatile memory device may include multiple unit cells. (See reference...) Figure 1 , Figure 2A and Figure 2B Each unit cell may include a first well region PW having a first conductivity type and a second well region NW adjacent to the first well region PW having a second conductivity type. The first well region PW and the second well region NW may be formed in a substrate. In some implementations, two or more unit cells may share the first well region PW and the second well region NW. The first well region PW and the second well region NW may have a linear shape extending in a second direction D2. The first well region PW and the second well region NW may be parallel to each other along a first direction D1. In one implementation, the first well region PW and the second well region NW may be spaced apart from each other in the first direction D1. In another implementation, the first well region PW may be in direct contact with the second well region NW in the first direction D1.

[0021] Each of the first well region PW and the second well region NW may include a first active region AC1 and a second active region AC2 defined by an isolation layer (not shown) in a substrate (not shown). Each unit cell may share the first active region AC1 and the second active region AC2. The first active region AC1 can be used for programming and reading operations. The second active region AC2 can be used for programming and erasing operations. The first active region AC1 may extend in a second direction D2. The second active region AC2 may extend in a first direction D1.

[0022] The first unit cell may include a first selection gate SG1 and a first floating gate FG1. The first selection gate SG1 and the first floating gate FG1 may extend in a first direction D1. The first selection gate SG1 may be spaced apart from the first floating gate FG1 in a second direction D2. The first selection gate SG1 may be disposed adjacent to the first floating gate FG1. The first unit cell and a second unit cell adjacent to the first unit cell may share a first active region AC1 and a second active region AC2. The second unit cell may include a second selection gate SG2 and a second floating gate FG2. The second selection gate SG2 and the second floating gate FG2 may extend in the first direction D1. The second selection gate SG2 may be spaced apart from the second floating gate FG2 in the second direction D2. The second selection gate SG2 may be disposed adjacent to the second floating gate FG2.

[0023] The first floating gate FG1 and the second floating gate FG2 may include a first region 101 and a second region 102. The first region 101 may extend in a first direction D1. The first region 101 of the first floating gate FG1 and the second floating gate FG2 may each include sidewalls facing the first select gate SG1 and the second select gate SG2. The second region 102 may extend from a portion of the first region 101 along a second direction D2. The second region 102 may overlap with a second active region AC2. In some implementations, the first floating gate FG1 and the second floating gate FG2 may have different shapes depending on the location where the second region 102 contacts the first region 101. For example, the second region 102 of the first floating gate FG1 may be connected to an end of the first region 101 of the first floating gate FG1. In some implementations, the first floating gate FG1 may have a vertical linear structure and a protruding horizontal linear structure at the end of the vertical linear structure. In one example, the first floating gate FG1 may have an "L" shape. In contrast, the second region 102 of the second floating gate FG2 may be connected to the portion of the first region 101 of the second floating gate FG2 other than the end of the first region 101. In some implementations, the second floating gate FG2 may have a vertical linear structure with a protruding horizontal linear structure. In one example, the cross-section of the second floating gate FG2 may have a crooked or "T" shape.

[0024] The first select gate SG1 and the second select gate SG2 may overlap with the first active region AC1. The first select gate SG1 and the second select gate SG2 may be used as word lines (WL). The first select gate SG1 and the second select gate SG2 may be used to prevent over-erasure conditions during erase operations. The first floating gate FG1 and the second floating gate FG2 may be used to store logic information. The first floating gate FG1 and the second floating gate FG2 may overlap with the first active region AC1 and the second active region AC2. Since the second active region AC2 may be used as an active control gate ACG, the first floating gate FG1 and the second floating gate FG2 may overlap with the second active region AC2. That is, the second active region AC2 may be used as a control gate to control the first floating gate FG1 and the second floating gate FG2, as well as the first select gate SG1 and the second select gate SG2.

[0025] Therefore, the first floating gate FG1 and the second floating gate FG2 can be electrically enabled in response to a bias voltage applied to the first select gate SG1 and the second select gate SG2 and / or a bias voltage applied to the second active region AC2. That is, the first floating gate FG1 and the second floating gate FG2 can be connected in response to a bias voltage applied to the first select gate SG1 and the second select gate SG2 and / or a bias voltage applied to the second active region AC2. The first floating gate FG1 and the second floating gate FG2, and the first select gate SG1 and the second select gate SG2, can be connected to each other via capacitance at both ends of the surfaces of the first floating gate FG1 and the second floating gate FG2 and the first select gate SG1 and the second select gate SG2 facing each other. That is, the first floating gate FG1 and the second floating gate FG2 can be enabled by the assembly of the first capacitor C1 in response to a bias voltage applied to the first select gate SG1 and the second select gate SG2. Furthermore, the first floating gate FG1 and the second floating gate FG2, along with the second active region AC2, can be connected via a capacitance vertically generated in the overlapping region between the first floating gate FG1 and the second floating gate FG2 and the second active region AC2. That is, the first floating gate FG1 and the second floating gate FG2 can be enabled by the components of the second capacitor C2 in response to a bias voltage applied to the second active region AC2. Since the first floating gate FG1 and the second floating gate FG2 can be connected via the first select gate SG1 and the second select gate SG2 and / or the second active region AC2, the connection ratio can vary depending on the operating mode. As a result, interference can be suppressed, and operational reliability improved.

[0026] exist Figure 2A and Figure 2B In the figures, reference numeral C3 indicates a third capacitor C3 comprising a substrate, a gate insulating layer, and a first floating gate FG1 and a second floating gate FG2. Although not depicted in the figures, each unit cell may include an insulating structure formed in the gap or space between the opposing first select gate SG1 and second select gate SG2 and the sidewalls of the first floating gate FG1 and second floating gate FG2. The insulating structure may include spacers formed on the respective sidewalls of the first select gate SG1 and second select gate SG2 and the first floating gate FG1 and second floating gate FG2. These spacers may serve as the dielectric layer of the first capacitor C1.

[0027] Furthermore, in each unit cell, the bit line BL can be electrically connected to the first active region AC1 adjacent to the first floating gate FG1 and the second floating gate FG2. The source lines SL1 and SL2 can be electrically connected to the first active region AC1 adjacent to the first select gate SG1 and the second select gate SG2. The enable control line ACL can be electrically connected to the second active region AC2.

[0028] The following will refer to Figure 2A and Figure 2B Discuss the programming, erasing, and reading operations of unit cells.

[0029] Programming operations for a single cell can utilize channel hot electrons (CHE). For example, a programming operation may include applying a positive pump voltage to the select gate SG and a second active region AC2 (used as an active control gate ACG), and applying a programming voltage and a ground voltage to the bit line BL and source line SL, respectively. The positive pump voltage may be higher than the programming voltage. For example, approximately 6V may be applied to the select gate SG and the active control gate ACG, and approximately 4.5V may be applied to the bit line BL. The pump voltage may be obtained by using, for example, a charge pump to increase the voltage from the supply voltage.

[0030] The erase operation for a single cell can utilize Fowler-Nordheim tunneling. For example, the erase operation may include applying a negative pump voltage to the select gate SG, a positive pump voltage to the active control gate ACG, and applying a ground voltage to the bit line BL and the source line SL. The absolute value of the pump voltage may be higher than the absolute value of the negative pump voltage. For example, approximately -6V may be applied to the select gate SG, and approximately 9V may be applied to the active control gate ACG.

[0031] A read operation of a single cell may include applying a power supply voltage to the select gate SG, applying a read voltage to the bit line BL, and applying a ground voltage to the active control gate ACG and the source line SL. The read voltage may be higher than the ground voltage and lower than the power supply voltage. For example, the power supply voltage may be approximately -3V and the read voltage may be approximately 1V.

[0032] The following can be referred to Figure 3 A non-volatile memory device with an example implementation is shown in detail.

[0033] Figure 3 These are examples of cell arrays of non-volatile memory devices based on some implementations of the disclosed technology. Figure 4A It is along Figure 3 A cross-sectional view taken from line A-A' in the diagram. Figure 4B It is along Figure 3 The cross-sectional view taken by line B-B' in the diagram.

[0034] Reference Figure 1 , Figure 3 , Figure 4A and Figure 4BA non-volatile memory device implemented based on some embodiments of the disclosed technology may include a cell array 11. The cell array 11 may include a plurality of subarrays 11-1 and 11-2 arranged in a matrix array by rows and columns. Each of the subarrays 11-1 and 11-2 may include first unit cells 10-1 to fourth unit cells 10-4. Since the subarrays 11-1 and 11-2 may be arranged in a matrix array, adjacent subarrays 11-1 and 11-2 may be symmetrical about a first direction D1 and a second direction D2.

[0035] Each of the subarrays 11-1 and 11-2 may include a second well region NW, a first well region PW1, and a third well region PW2. The second well region NW may be formed in a substrate Sub. The second well region NW may have a second conductivity type. The first well region PW1 may be located above the second well region NW. The first well region PW1 may have a first conductivity type. The third well region PW2 may be located below the second well region NW. The third well region PW2 may have a first conductivity type. The first well region PW1, the second well region NW, and the third well region PW2 can be formed by implanting ions into the substrate Sub. The first well region PW1 and the third well region PW2 can be formed by implanting P-type impurities such as boron (B) into the substrate Sub. The second well region NW can be formed by implanting N-type impurities such as phosphorus (P), arsenic (As), etc. The first well region PW1, the second well region NW, and the third well region PW2 may have a linear planar shape extending in a second direction D2. In one implementation, the first well region PW1, the second well region NW, and the third well region PW2 may be spaced apart from each other in the first direction D1, and are not limited to a specific structure. In another implementation, the second well region NW may be in direct contact with both the first well region PW1 and the third well region PW2.

[0036] The substrate Sub may include a semiconductor substrate. The semiconductor substrate Sub may include monocrystalline silicon. For example, the substrate Sub may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate including a support substrate, an insulating layer and a monocrystalline silicon layer stacked sequentially, etc.

[0037] Each of the first well region PW1 and the third well region PW2 may include a first active region AC1 defined by the isolation layer 103 in the substrate Sub. The first active region AC1 can be used for programming operations and reading operations. The first active region AC1 may have a linear planar shape extending in a second direction D2. As an example, Figure 3A first active region AC1 is shown in each of the first well region PW1 and the third well region PW2. In another implementation, each of the first well region PW1 and the third well region PW2 may include more than one first active region AC1. For example, each of the first well region PW1 and the third well region PW2 may include two first active regions AC1 spaced apart from each other in a first direction D1.

[0038] The second well region NW may include a second active region AC2 defined by isolation layer 103. The second active region AC2 can be used for programming and erasing operations. That is, the second active region AC2 can be used as an active control gate ACG. Therefore, the connection ratio can vary depending on the operating mode, thereby suppressing interference and improving operational reliability. The second active region AC2 may extend in the first direction D1. The second active region AC2 extending in the first direction D1 can prevent or reduce interference and punch-through effects between the first select gate SG1 and the second select gate SG2 and the second active region AC2. Here, punch-through effects may include undesirable electrical connections between the first select gate SG1 and the second select gate SG2 and the second active region AC2.

[0039] The isolation layer 103 can be formed using a shallow trench isolation (STI) process. The isolation layer 103 may include an insulating material. The isolation layer 103 may have a depth measured from the top surface of the substrate Sub. In one implementation, the depths of the first well region PW1, the second well region NW, and the third well region PW2 may be deeper than the depth of the isolation layer 103. In another implementation, the depth of the isolation layer 103 may be substantially equal to or greater than the depths of the first well region PW1, the second well region NW, and the third well region PW2.

[0040] Each of subarrays 11-1 and 11-2 may include a first select gate SG1 and a second select gate SG2 formed at the substrate Sub. The first select gate SG1 may be used as a word line for the first unit cell 10-1 and the third unit cell 10-3. The second select gate SG2 may be used as a word line for the second unit cell 10-2 and the fourth unit cell 10-4. Each of the first select gate SG1 and the second select gate SG2 may be used to prevent over-erasure during an erase operation. The first select gate SG1 and the second select gate SG2 may be spaced apart from each other in the second direction D2. Furthermore, the first select gate SG1 and the second select gate SG2 may be parallel to each other. The gap (g1) between the second active region AC2 and the first select gate SG1 may be the same as or similar to the gap (g2) between the second active region AC2 and the second select gate SG2. The gaps (g1 and g2) are wide enough to effectively prevent interference and punch-through effects between the second active region AC2 and the first select gate SG1 and the second select gate SG2.

[0041] Each of subarrays 11-1 and 11-2 may include a first floating gate FG1, a second floating gate FG2, a third floating gate FG3, and a fourth floating gate FG4 configured to be connected to the second active region AC2. In some implementations, the first floating gate FG1 to the fourth floating gate FG4 are arranged in the longitudinal direction of the second active region AC2. In some implementations, the first floating gate FG1 and the third floating gate FG3 are arranged on one side of the second active region AC2 (extending in the longitudinal direction of the second active region AC2), and the second floating gate FG2 and the fourth floating gate FG4 are arranged on the other side of the second active region AC2 (extending in the longitudinal direction of the second active region AC2). Each of the first floating gate FG1 to the fourth floating gate FG4 includes a branch configured to extend toward the second active region AC2. The branches of the first floating gate FG1 to the fourth floating gate FG4 are connected to the second active region AC2 and spaced apart from each other. In one example, the branch may include a second region 102 of a first floating gate FG1 and a fourth floating gate FG4. In some implementations, the first to fourth floating gates FG1, FG2, FG3, and FG4 may be configured to partially overlap with the second active region AC2. The first to fourth floating gates FG1, FG2, FG3, and FG4 may correspond to the first to fourth unit cells 10-1, 10-2, 10-3, and 10-4, respectively. The first to fourth floating gates FG1, FG2, FG3, and FG4 may store charges corresponding to one or more bits of information. The first to fourth floating gates FG1, FG2, FG3, and FG4 may overlap with the first active region AC1 and the second active region AC2. The first floating gate FG1 and the third floating gate FG3 may be arranged adjacent to the first select gate SG1 and may be spaced apart from the first select gate SG1 by a gap 110. The second floating gate FG2 and the fourth floating gate FG4 may be arranged adjacent to the second select gate SG2 and may be spaced apart from the second select gate SG2 by a gap 110. The gap 110 may be filled by an insulating structure 112. The insulating structure 112 may include spacers formed on the sidewalls of each of the select gates SG1 and SG2 and the floating gates FG1 to FG4.

[0042] The second regions 102 of the first floating gate FG1 and the fourth floating gate FG4 can be connected to one end or the other end of the first region 101 of the first floating gate FG1 and the fourth floating gate FG4, such that the first floating gate FG1 and the fourth floating gate FG4 can have an "L" shape. In contrast, the second regions 102 of the second floating gate FG2 and the third floating gate FG3 can be connected to one end or the other end of the first region 101 of the second floating gate FG2 and the third floating gate FG3, such that the horizontal cross-section of each of the second floating gate FG2 and the third floating gate FG3 can have a vertical linear structure with a protruding horizontal linear structure. In one example, the cross-sections of the second floating gate FG2 and the third floating gate FG3 can have a crutch shape or a "T" shape. Therefore, the first floating gate FG1 and the third floating gate FG3 facing each other in the first direction D1 can have an asymmetrical shape. Furthermore, as... Figure 3 As shown in the plan view above, the first floating gate FG1 and the second floating gate FG2, which face each other in the second direction D2, may have asymmetrical shapes. The third floating gate FG3 and the fourth floating gate FG4, which face each other in the second direction D2, may also have asymmetrical shapes. The fourth floating gate FG4 and the second floating gate FG2, which face each other in the first direction D1, may also have asymmetrical shapes. These shapes of the floating gates FG1, FG2, FG3, and FG4 prevent interference between the floating gates FG1, FG2, FG3, and FG4 and provide uniform capacitance for the second capacitor C2 in each of the unit cells 10-1 to 10-4 to prevent or reduce differences in the connection ratios relative to the floating gates FG1 to FG4. Therefore, each of the unit cells 10-1 to 10-4 may include floating gates FG1 to FG4 that are asymmetrical to each other and have branches spaced apart from each other to improve threshold voltage uniformity. As a result, the reliability of the read operation can be improved.

[0043] In some implementations, each of the first floating gate FG1 to the fourth floating gate FG4 may include a first region 101 and a second region 102. The first region 101 may have a structure extending in a first direction D1. The second region 102 may protrude from or extend from the first region 101 in a second direction D2. The first region 101 may partially overlap with a first active region AC1. The second region 102 may partially overlap with a second active region AC2. To make... Figure 2A and Figure 2B The first capacitor C1 has a sufficiently high capacitance, and the length of the first region 101 can be longer than the length of the second region 102. Furthermore, in order to... Figure 2A and Figure 2BThe second capacitor C2 of each of the unit cells 10-1 to 10-4 has a uniform capacitance, and the second region 102 can be configured to intersect with the second active region AC2. In one example, the second region 102 can be configured to intersect the isolation layer 103 and the second active region AC2 along the second direction D2. Therefore, the second active region AC2 and the first floating gate FG1 to the fourth floating gate FG4 can have substantially the same overlap area.

[0044] The second regions 102 of the first floating gate FG1 to the fourth floating gate FG4 may be spaced apart from each other in the first direction D1. The second regions 102 may be located in the central portion of the second active region AC2. The second regions 102 of the second floating gate FG2 and the third floating gate FG3 may be located at one edge and the other edge of the second active region AC2, respectively. The gap S between the second active region AC2 and the first floating gate FG1 to the fourth floating gate FG4 may be the same or similar.

[0045] The first active region AC1 in each subarray may include a first junction region 104 formed between a first floating gate FG1 and a second floating gate FG2, and between a third floating gate FG3 and a fourth floating gate FG4. Furthermore, the first active region AC1 may include a second junction region 106 and a third junction region 108. The second junction region 106 may be formed in the first active region AC1 adjacent to the first select gate SG1 and the second select gate SG2. The third junction region 108 may be formed below the insulating structure 112 in the gap 110. The first junction region 104, the second junction region 106, and the third junction region 108 may include impurity regions formed by implanting a second conductivity type impurity into the first active region AC1. The first junction region 104 and the second junction region 106 may have an LDD structure. The third junction region 108 may be used to electrically connect a sensing channel to the first active region AC1 via a select gate and a floating gate. The first junction region 104 may be connected to the bit line BL. The portions of the first junction region 104 between the first floating gate FG1 and the second floating gate FG2, and the portions of the first junction region 104 between the third floating gate FG3 and the fourth floating gate FG4, can be connected to different bit lines BL. The second junction region 106 can be connected to the source line SL. The portions of the second junction region 106 adjacent to the first select gate SG1 and the portions of the second junction region 106 adjacent to the second select gate SG2 can be electrically connected to different source lines SL.

[0046] The second active region AC2 in each of subarrays 11-1 and 11-2 may be electrically connected to the enable control line ACL parallel to the bit line BL. Although not depicted in the figures, the second active region AC2 may also include an impurity region to reduce the contact resistance between the enable control line ACL and the second active region AC2. The impurity region may be formed by implanting an impurity of a second conductivity type. The doping concentration of this impurity region may be higher than the doping concentration of the impurity region in the second well region NW.

[0047] In some embodiments of the disclosed technology, the plurality of floating gates FG1 to FG4 overlapping with the second active region AC2 may have an asymmetrical shape to prevent or reduce differences in the connection ratios of the floating gates FG1 to FG4. Therefore, the non-volatile memory device can have a uniform threshold voltage, thereby improving the reliability of read operations.

[0048] In addition, the gaps (g1, g2) between the gates SG1 and SG2 and the second active region AC2, as well as the gap (S) between the floating gates FG1 to FG4, can be wide enough to further improve operational reliability.

[0049] The technical features disclosed in this patent document can be implemented in various configurations or methods, and the disclosed embodiments are merely examples of specific implementations. Variations and enhancements can be made to the disclosed embodiments and other embodiments based on the content disclosed and / or shown in this patent document.

[0050] Cross-reference to related applications

[0051] This patent document claims priority and benefit to Korean Patent Application No. 10-2020-0187100, filed on December 30, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: A substrate, the substrate including an active region; as well as A first floating gate, a second floating gate, a third floating gate, and a fourth floating gate are formed on the substrate and arranged to partially overlap with the active region. The first floating gate and the third floating gate are arranged along a first direction on one side of the active region and are asymmetrical about the center of the active region, while the second floating gate and the fourth floating gate are arranged along the first direction on the other side of the active region and are asymmetrical about the center of the active region. The first floating gate and the second floating gate are arranged to face each other in a second direction perpendicular to the first direction, and the first floating gate and the second floating gate are asymmetrical. The third floating gate and the fourth floating gate are also arranged to face each other in the second direction, and the third floating gate and the fourth floating gate are asymmetrical. Wherein, the portions of the first floating gate to the fourth floating gate that overlap with the active region are spaced apart from each other at equal intervals, and The active region is used as an active control gate.

2. The memory device according to claim 1, wherein, The third floating gate and the fourth floating gate, which face each other in the second direction, are asymmetrical about an axis passing through the center of the active region in the first direction, and the fourth floating gate and the second floating gate, which face each other in the first direction, are asymmetrical about an axis passing through the center of the active region in the second direction.

3. The memory device according to claim 1, wherein, The active region extends in the first direction, the first floating gate and the fourth floating gate are spaced apart from each other, and the second floating gate and the third floating gate overlap with one edge portion and another edge portion of the active region, respectively. The first floating gate overlaps with the portion of the active region between the one edge and the center of the active region, and the fourth floating gate overlaps with another portion of the active region between the other edge and the center of the active region.

4. The memory device according to claim 1, wherein, The first floating gate and the fourth floating gate have an L-shape, and the horizontal cross-section of each of the second floating gate and the third floating gate has a vertical linear structure with a protruding horizontal linear structure.

5. The memory device according to claim 1, wherein, Each of the first floating gate to the fourth floating gate includes a first region and a second region, the first region having a linear shape extending in the first direction and the second region having a linear shape extending from the first region in the second direction.

6. The memory device according to claim 5, wherein, The length of each first region in each of the first floating gate to the fourth floating gate is longer than the length of each second region in each of the first floating gate to the fourth floating gate.

7. The memory device according to claim 5, wherein, The second region intersects with and partially overlaps with the active region, and the overlap area between the active region and the first floating gate to the fourth floating gate is equal to each other.

8. A memory device comprising: substrate; A first well region and a second well region are formed in the substrate and have different conductivity types. The first well region and the second well region are arranged parallel to each other along a first direction. An isolation layer is formed in the substrate to define a first active region and a second active region in each of the first well region and the second well region; A first selection gate and a second selection gate are formed on the substrate and overlap with the first active region. The first selection gate and the second selection gate are arranged parallel to each other along a second direction perpendicular to the first direction, and the first selection gate and the second selection gate have a linear shape extending in the first direction. as well as A first floating gate and a second floating gate are arranged adjacent to a first selection gate and a second selection gate, respectively. The first floating gate and the second floating gate overlap with a first active region and a second active region, and the first floating gate and the second floating gate face each other in the second direction. In this configuration, the first floating gate and the second floating gate face each other and are asymmetrical in the second direction. Wherein, the portions of the first floating gate and the second floating gate that overlap with the second active region are spaced apart from each other at equal intervals, and The second active region serves as an active control gate. During programming and erasing operations, a positive pump voltage is applied to the second active region, and the positive pump voltage during the erasure operation is higher than the positive pump voltage during the programming operation.

9. The memory device according to claim 8, wherein, The first select gate and the first floating gate, as well as the second select gate and the second floating gate, have sidewalls facing each other in the second direction, and an insulating structure is formed between the sidewalls.

10. The memory device according to claim 8, wherein, The second active region extends in the first direction, and the distance between the first select gate and the second active region in the second direction is the same as the distance between the second select gate and the second active region in the second direction.

11. The memory device according to claim 8, wherein, The first floating gate has an L-shaped cross-section, and the second floating gate has a vertical linear structure with a protruding horizontal linear structure in its cross-section.

12. The memory device according to claim 8, wherein, Each of the first floating gate and the second floating gate includes a first region and a second region, the first region having a linear shape extending in the first direction and the second region having a linear shape extending from the first region in the second direction.

13. The memory device according to claim 12, wherein, The length of the first region is longer than the length of the second region, and the second region intersects with and partially overlaps with the second active region.

14. The memory device of claim 8, further comprising: A third well region is formed on the substrate, and the conductivity type of the third well region is the same as that of the first well region. A third active region, the third active region being defined in the third well region by the isolation layer, the third active region overlapping with the first selected gate and the second selected gate; as well as A third floating gate and a fourth floating gate are arranged to be adjacent to the first selection gate and the second selection gate, respectively. The third floating gate and the fourth floating gate overlap with the third active region and the second active region, and the third floating gate and the fourth floating gate face each other in the second direction. The third floating gate and the fourth floating gate face each other and are asymmetrical in the second direction.

15. The memory device according to claim 14, wherein, The first floating gate and the third floating gate face each other and are asymmetrical in the first direction.

16. The memory device according to claim 14, wherein, The second floating gate and the fourth floating gate face each other and are asymmetrical in the first direction.

17. The memory device according to claim 14, wherein, The overlap area between the second active region and the first floating gate to the fourth floating gate in the first direction is equal to that of each other.

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