Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a source-drain layer in the fins on both sides of the gate structure; forming a first sidewall on the sidewall of the gate structure, the first sidewall also being located on part of the sidewall and top surface of the source-drain layer; forming a first protective layer on the surface of the source-drain layer on the first region, and a mask layer located on the first protective layer, the first protective layer having a first doping ion, so that the first doping ion is doped into the top surface of the source-drain layer on the first region; using the mask layer as a mask, injecting a second doping ion into the top surface of the source-drain layer on the second region. The first sidewall can prevent the first doping ion or the second doping ion from entering the channel from the loose connection between the gate structure and the source-drain layer, and prevent the first doping ion or the second doping ion from affecting the doping ion concentration in the channel, thereby improving the performance of the formed device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the fin field effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, the gate size of fin field effect transistors is also constantly decreasing. At this time, the distribution width of boron and phosphorus doped ions becomes an important factor affecting the short channel effect (SCE) of fin field effect transistors. At the same time, the diffusion of boron and phosphorus doped ions caused by transient enhanced diffusion (TED) not only affects the short channel effect, but also affects the transistor channel mobility, junction capacitance, and leakage performance.

[0004] The performance of the semiconductor structure formed by the existing fin field effect transistor needs to be improved urgently. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, the base including a first region and a second region, the substrate also including a fin and an isolation structure located on the base, the isolation structure also located on the side wall of the fin, and the top surface of the isolation structure is lower than the top surface of the fin; forming a gate structure spanning the fin, the gate structure being located on part of the top surface and part of the side wall surface of the fin; forming a source-drain layer in the fin on both sides of the gate structure; forming a first side wall on the side wall of the gate structure, the first side wall being also located on part of the side wall and top surface of the source-drain layer; forming a first protective layer on the surface of the source-drain layer in the first region, and a mask layer located on the first protective layer, the first protective layer having a first doping ion, so that the first doping ion is doped into the top surface of the source-drain layer in the first region; using the mask layer as a mask, injecting a second doping ion into the top surface of the source-drain layer in the second region.

[0007] Optionally, the process of implanting second doping ions into the top surface of the source / drain layer on the second region includes an ion implantation process.

[0008] Optionally, the parameters of the ion implantation process include: the energy range of N-type ions is 3keV to 25keV, the dose range is 2.0E15 atom / cm 3 Up to 1.5E16 atom / cm 3 ; The energy range of P-type ions is 0.5keV to 10keV, and the dose range is 3.0E15 atom / cm 3 Up to 2.0E16 atom / cm 3 .

[0009] Optionally, the first doping ion is N-type, and the material of the first protective layer includes phosphosilicate glass; the first doping ion is P-type, and the material of the first protective layer includes borophosphosilicate glass.

[0010] Optionally, the process for forming the first protective layer includes a chemical vapor deposition process.

[0011] Optionally, before forming the first sidewall spacer, the method further includes forming a first dielectric layer on the isolation structure, wherein the first dielectric layer covers the sidewall surface of the source / drain layer.

[0012] Optionally, a material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0013] Optionally, the method for forming the first protective layer includes: forming a first protective material layer on the surface of the first dielectric layer, the surface of the source and drain layer, the side walls and the top surface of the gate structure; forming a mask layer on the surface of the first protective material layer, the mask layer exposing the surface of the first protective material layer on the second region; etching the first protective material layer using the mask layer as a mask until the surface of the first dielectric layer, the surface of the source and drain layer, the side walls and the top surface of the gate structure on the second region are exposed.

[0014] Optionally, after injecting the second doping ions, it also includes: removing the mask layer; after removing the mask layer, forming a second dielectric layer on the substrate, the second dielectric layer is also located on the surface of the first protective layer, the surface of the source and drain layer, and the sidewall and surface of the gate structure.

[0015] Optionally, a material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0016] Optionally, the material of the first spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0017] Optionally, the gate structure includes: a gate layer; a second sidewall spacer located on a sidewall of the gate layer; and a second protective layer located on a top of the gate layer.

[0018] Optionally, the material of the gate layer includes polysilicon.

[0019] Optionally, the method for forming the source and drain layers includes: forming a first opening in the fins on both sides of the gate structure on the first region; forming a first epitaxial layer in the first opening, and injecting third doping ions into the first epitaxial layer to form a source and drain layer on the first region; forming a second opening in the fins on both sides of the gate structure on the second region; forming a second epitaxial layer in the second opening, and injecting fourth doping ions into the second epitaxial layer to form a source and drain layer on the second region.

[0020] Optionally, the third doping ions include N-type or P-type ions, and the third doping ions have the same conductivity type as the first doping ions; the fourth doping ions include N-type or P-type ions, and the fourth doping ions have the same conductivity type as the second doping ions.

[0021] Optionally, the first doping ions include N-type or P-type ions; the second doping ions include N-type or P-type ions, and the conductivity type of the second doping ions is different from the conductivity type of the first doping ions.

[0022] Optionally, the material of the mask layer includes photoresist.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first sidewall is formed on the sidewall of the gate structure, and the first sidewall can prevent the first doping ion or the second doping ion from entering the channel from the loose connection between the gate structure and the source and drain layer, and avoid the influence of the first doping ion or the second doping ion on the doping ion concentration in the channel, thereby improving the stability of the threshold voltage and other performances of the formed device, and suppressing the short channel effect and other problems. A first protective layer is formed on the surface of the source and drain layer on the first region, and a mask layer is formed on the first protective layer, and the first protective layer has a first doping ion, so that the first doping ion is doped into the top surface of the source and drain layer on the first region to reduce the contact resistance between the surface of the source and drain layer on the first region and the conductive plug on the first region formed subsequently; the second doping ion is injected into the top surface of the source and drain layer on the second region using the mask layer as a mask, which can reduce the contact resistance between the second doping ion and the conductive plug on the surface of the source and drain layer on the second region formed subsequently, and the mask layer is also used to block the influence of the second doping ion on the source and drain layer on the first region.

[0025] Furthermore, the process of doping the top surface of the source and drain layer with the first doping ion is completed before the second dielectric layer is formed. Compared with the method of forming a through hole in the interlayer dielectric layer to expose the top surface of the source and drain layer after the interlayer dielectric layer is formed, the method avoids the situation where the ion implantation process affects the interlayer dielectric layer exposed by the side wall of the through hole, thereby improving the performance of the device.

[0026] Furthermore, before forming the first sidewall, a first dielectric layer is formed on the isolation structure, and the first dielectric layer covers the sidewall surface of the source / drain layer. Since the first dielectric layer covers the sidewall surface of the source / drain layer, the sidewall of the source / drain layer is avoided from being exposed, and the first doping ions or the second doping ions are prevented from being incorporated into the source / drain layer through the sidewall of the source / drain layer, thereby reducing the influence of the first doping ions on the doping ion concentration in the channel, thereby improving the stability of the performance of the formed device such as the threshold voltage, suppressing the short channel effect and other problems, and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 3 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0028] Figures 4 to 11 It is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0030] As described in the background art, the performance of a semiconductor structure formed by using the existing FinFET technology needs to be improved. Now, a semiconductor structure is described and analyzed.

[0031] Figures 1 to 3 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0032] Please refer to Figure 1 and Figure 2 , Figure 1 It is a top view. Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the XY direction, providing a substrate, the substrate comprising a base 100, a fin 101 and an isolation structure 102 located on the base 100, the isolation structure 102 also being located on the sidewall of the fin 101, and the top surface of the isolation structure being lower than the top surface of the fin 101; forming a gate structure 103 across the fin 101, the gate structure 103 being located on a portion of the top surface and a portion of the sidewall surface of the fin 101, the gate structure 103 comprising a gate layer 104, a sidewall 105 located on the sidewall of the gate layer 104, and a protective layer 106 located on the top of the gate layer 104; and forming a source / drain layer 107 in the fin 101 on both sides of the gate structure 103.

[0033] Please refer to Figure 3 , Figure 3 View direction is the same as Figure 2 , ions 108 are implanted into the surface of the source and drain regions 107 .

[0034] The above method is used in the process of forming a FinFET device, and ions 108 are implanted into the surface of the source and drain region 107. The ions 108 include N-type or P-type conductive ions, which are used to reduce the contact resistance between the surface of the source and drain region 107 and the conductive plug subsequently formed on the surface of the source and drain region 107. However, since the FinFET device is a three-dimensional structure, the source and drain layer 107 protrudes from the substrate 100. During the process of implanting the ions 108, the ions 108 will inevitably pass through the sidewall A (such as Figure 1 and Figure 2As shown, the ions 108 are implanted into the source / drain layer 107. Since the ions 108 are N-type or P-type conductive ions, the lateral diffusion of the ions 108 in the source / drain layer 107 will eventually cause a change in the doping ion concentration in the channel between the source / drain layers 107 and below the gate layer 104, thereby affecting the performance of the subsequently formed device, such as the threshold voltage, resulting in a short channel effect, etc., thereby reducing the reliability of the device performance.

[0035] In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, a first sidewall is formed on the sidewall of the gate structure, and the first sidewall can prevent the first doping ion or the second doping ion from entering the channel from the loose connection between the gate structure and the source and drain layer, and avoid the influence of the first doping ion or the second doping ion on the doping ion concentration in the channel, thereby improving the stability of the threshold voltage and other performances of the formed device, and suppressing the short channel effect and other problems. A first protective layer is formed on the surface of the source and drain layer on the first region, and a mask layer is located on the first protective layer, and the first protective layer has a first doping ion, so that the first doping ion is doped into the top surface of the source and drain layer on the first region, so as to reduce the contact resistance between the surface of the source and drain layer on the first region and the conductive plug on the first region formed subsequently; the second doping ion is injected into the top surface of the source and drain layer on the second region with the mask layer as a mask, so as to reduce the contact resistance between the second doping ion and the conductive plug on the surface of the source and drain layer on the second region formed subsequently, and the mask layer is also used to block the influence of the second doping ion on the source and drain layer on the first region.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 11 It is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 4 and Figure 5 , Figure 4 It is a top view. Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure along the XY direction provides a substrate, wherein the substrate includes a base 200, the base 200 includes a first region I and a second region II, the substrate also includes a fin 201 and an isolation structure 202 located on the base 200, the isolation structure 202 is also located on the side wall of the fin 201, and the top surface of the isolation structure 202 is lower than the top surface of the fin 201.

[0039] The material of the substrate 200 includes silicon. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate may also be a silicon-on-insulator (SOI) structure or a germanium-on-insulator structure.

[0040] The material of the fin 201 includes silicon. In this embodiment, the material of the fin 201 is silicon. In other embodiments, the material of the fin 201 can also be a semiconductor material such as single crystal germanium, silicon germanium, gallium arsenide, etc.

[0041] The material of the isolation structure 202 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride. In this embodiment, the material of the isolation structure 202 is silicon oxide. The isolation structure 202 is used for electrical insulation between different devices.

[0042] The first region I and the second region II are used to form devices of different conductivity types. In this embodiment, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0043] Please refer to Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 The schematic diagram of the cross-sectional structure along the XY direction shows a gate structure 203 across the fin 201 , wherein the gate structure 203 is located on a portion of the top surface and a portion of the sidewall surface of the fin 201 ; a source-drain layer 207 is formed in the fin 201 on both sides of the gate structure 203 .

[0044] In this embodiment, the gate structure 203 includes: a gate layer 204 ; a second spacer 205 located on the sidewall of the gate layer 204 ; and a second protection layer 206 located on the top of the gate layer 204 .

[0045] The material of the gate layer 204 includes silicon. In this embodiment, the material of the gate layer 204 is polysilicon. In other embodiments, the material of the gate layer 204 can be amorphous silicon, silicon carbide, etc.

[0046] The material of the second sidewall spacer 205 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the second sidewall spacer 205 is silicon nitride.

[0047] The material of the second protective layer 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the second protective layer 206 is silicon oxide.

[0048] The method for forming the source-drain layer 207 includes: forming a first opening (not shown in the figure) in the fin 201 on both sides of the gate structure 203 on the first region I; forming a first epitaxial layer (not shown in the figure) in the first opening, and implanting a third doping ion into the first epitaxial layer to form the source-drain layer 207 on the first region I; forming a second opening (not shown in the figure) in the fin 201 on both sides of the gate structure 203 on the second region II; forming a second epitaxial layer (not shown in the figure) in the second opening, and implanting a fourth doping ion into the second epitaxial layer to form the source-drain layer 207 on the second region II. In this embodiment, the material of the first epitaxial layer is silicon carbide; the material of the second epitaxial layer is silicon germanium.

[0049] The third doping ion includes an N-type or P-type ion, and the third doping ion has the same conductivity type as the first doping ion; the fourth doping ion includes an N-type or P-type ion, and the fourth doping ion has the same conductivity type as the second doping ion. In this embodiment, the third doping ion is an N-type ion; the fourth doping ion is a P-type ion.

[0050] Please refer to Figure 8 and Fig. 9 , Figure 8 It is a top view. Fig. 9 yes Figure 8 The schematic cross-sectional structure diagram along the XY direction shows that a first sidewall 209 is formed on the sidewall of the gate structure 203 , and the first sidewall 209 is also located on a portion of the sidewall and top surface of the source / drain layer 207 .

[0051] The material of the first sidewall 209 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. The first sidewall 209 is used to block the first doping ions from entering the channel through the weak adhesion between the source and drain layer 207 and the gate structure 203, avoiding the influence of the first doping ions on the doping ion concentration in the channel, thereby improving the stability of the performance of the formed device such as the threshold voltage, and suppressing the short channel effect and other problems.

[0052] In this embodiment, before forming the first sidewall spacer 209 , a first dielectric layer 208 is further formed on the isolation structure 202 , and the first dielectric layer 208 covers the sidewall surface of the source / drain layer 207 .

[0053] The material of the first dielectric layer 208 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the first dielectric layer 208 is silicon oxide.

[0054] The formation process of the first dielectric layer 208 includes a chemical vapor deposition process. In this embodiment, the formation process of the first dielectric layer 208 is a fluid chemical vapor deposition process, which has good material filling ability and is conducive to forming a first dielectric layer 208 with low defects.

[0055] Subsequently, a first protective layer is formed on the surface of the source / drain layer 207 on the first region I, and a mask layer is located on the first protective layer, wherein the first protective layer has first doping ions so that the first doping ions are doped into the top surface of the source / drain layer on the first region; using the mask layer as a mask, second doping ions are injected into the top surface of the source / drain layer on the second region II.

[0056] The channel of the device is formed between the source and drain layers 207 and below the gate layer 204. Since the first dielectric layer 208 covers the sidewall surface of the source and drain layer 207, the sidewall of the source and drain layer 207 is avoided from being exposed, and the first doping ions or the second doping ions are prevented from being doped into the source and drain layer 207 through the sidewall of the source and drain layer 207, thereby reducing the influence of the first doping ions or the second doping ions on the doping ion concentration in the channel, thereby improving the stability of the performance such as the threshold voltage of the formed device, suppressing the problems such as the short channel effect, and improving the performance of the device.

[0057] Please refer to Fig.10 , Fig.10 The viewing direction is the same as Fig. 9 A first protective layer 210 is formed on the surface of the source / drain layer 207 on the first region I, and a mask layer 211 is located on the first protective layer 210, wherein the first protective layer 210 has first doping ions so that the first doping ions are doped into the top surface of the source / drain layer 207 on the first region I.

[0058] In this embodiment, the first protection layer 210 is also located on the surface of the first dielectric layer 208 on the first region I, the sidewall and top surface of the gate structure 203, so that the first doping ions are doped into the top surface of the source / drain layer 207 on the first region I.

[0059] The method for forming the first protective layer 210 includes: forming a first protective material layer (not shown in the figure) on the surface of the first dielectric layer 208, the surface of the source and drain layer 207, and the side walls and top surface of the gate structure 203; patterning the first protective material layer, removing the first protective material layer on the second region II, so that the surface of the first dielectric layer 208, the surface of the source and drain layer 207, and the side walls and top surface of the gate structure 203 on the second region II are exposed.

[0060] The method for patterning the first protective material layer includes: forming a mask layer 211 on the surface of the first protective material layer, the mask layer 211 exposing the surface of the first protective material layer on the second region II; etching the first protective material layer using the mask layer 211 as a mask until the surface of the first dielectric layer 208, the surface of the source and drain layer 207, and the side walls and top surface of the gate structure 203 on the second region II are exposed.

[0061] The material of the mask layer 211 includes photoresist.

[0062] In this embodiment, the first region I is used to form an N-type device, so the material of the first protective layer 210 is phosphosilicate glass. In other embodiments, the material of the first protective layer 210 can be phosphosilicate glass.

[0063] In this embodiment, after forming the first protective layer 210 and before injecting the second doping ions, the first protective layer 210 is further subjected to thermal annealing. In other embodiments, the thermal annealing can be performed in other process steps after forming the first protective layer 210. The phosphorus (or boron) ions in the phosphosilicate glass (or borophosphosilicate glass) will diffuse to the top surface of the source-drain layer 207 through the thermal annealing, thereby reducing the resistivity of the source-drain layer 207 on the first region I, and further reducing the contact resistance between the source-drain layer 207 on the first region I and the conductive plug subsequently formed on the surface of the source-drain layer 207 on the first region I.

[0064] Please continue to refer to Fig.10 , using the mask layer 211 as a mask, second doping ions are implanted into the top surface of the source / drain layer 207 on the second region II.

[0065] The second doping ions include N-type or P-type ions, and the conductivity type of the second doping ions is different from the conductivity type of the first doping ions. In this embodiment, the second region is used to form a P-type device, so the second doping ions are P-type ions.

[0066] The process of implanting the second doping ions into the top surface of the source / drain layer 207 on the second region II includes an ion implantation process.

[0067] The second doping ions are N-type ions or P-type ions.

[0068] The process parameters of the ion implantation process include: the energy range of N-type ions is 3keV to 25keV, and the dose range is 2.0E15 atom / cm 3 Up to 1.5E16 atom / cm 3 ; The energy range of P-type ions is 0.5keV to 10keV, and the dose range is 3.0E15 atom / cm3 Up to 2.0E16 atom / cm 3 .

[0069] Second doping ions are implanted into the top surface of the source / drain layer 207 on the second region II to reduce the contact resistance between the source / drain layer 207 on the second region II and a conductive plug subsequently formed on the surface of the source / drain layer 207 on the second region II.

[0070] The mask layer 211 is also used to protect the devices on the first region I from being affected by the second doping ion implantation.

[0071] Please refer to Fig.11 , Fig.11 The viewing direction is the same as Fig.10 After the second doping ions are injected, the mask layer 211 is removed; after the mask layer 211 is removed, a second dielectric layer 212 is formed on the substrate 200, and the second dielectric layer 212 is also located on the surface of the first protective layer 210, the surface of the source and drain layer 207, and the side wall and surface of the gate structure 205.

[0072] The material of the second dielectric layer 212 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the second dielectric layer 212 is silicon oxide.

[0073] The second dielectric layer 211 and the first dielectric layer 208 are used as interlayer dielectric layers to isolate metal interconnects and devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve parasitic field effect transistors formed by metal crossing different regions.

[0074] The process of doping the top surface of the source-drain layer 207 with the first doping ion is completed before forming the second dielectric layer. Compared with the method of forming a through hole in the interlayer dielectric layer to expose the top surface of the source-drain layer after the interlayer dielectric layer is formed, the method of injecting doping ions into the surface of the source-drain layer after the through hole is formed avoids the situation where the ion implantation process affects the interlayer dielectric layer exposed by the side wall of the through hole, thereby improving the performance of the device.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, the base comprising a first region and a second region, the substrate further comprising a fin and an isolation structure located on the base, the isolation structure also being located on a sidewall of the fin, and a top surface of the isolation structure being lower than a top surface of the fin; forming a gate structure across the fin, the gate structure being located on a portion of a top surface and a portion of a sidewall surface of the fin; forming source and drain layers in the fins on both sides of the gate structure; Forming a first sidewall spacer on the sidewall of the gate structure, wherein the first sidewall spacer is also located on a portion of the sidewall and top surface of the source / drain layer; forming a first protective layer on the surface of the source-drain layer on the first region, and a mask layer on the first protective layer, wherein the first protective layer has first doping ions, so that the first doping ions are doped into the top surface of the source-drain layer on the first region; Using the mask layer as a mask, second doping ions are implanted into the top surface of the source / drain layer on the second region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process of implanting second doping ions into the top surface of the source / drain layer on the second region includes an ion implantation process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the ion implantation process include: the energy range of N-type ions is 3keV to 25keV, and the dose range is 2.0E15 atom / cm 3 Up to 1.5E16 atom / cm 3 ; The energy range of P-type ions is 0.5keV to 10keV, and the dose range is 3.0E15 atom / cm 3 Up to 2.0E16 atom / cm 3 .

4. The method for forming a semiconductor structure according to claim 1, wherein: include: The first doping ion is N-type, and the material of the first protective layer includes phosphosilicate glass; The first doping ion is of P type, and the material of the first protective layer includes borophosphosilicate glass.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the first protective layer includes a chemical vapor deposition process.

6. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first sidewall spacer, the method further includes forming a first dielectric layer on the isolation structure, wherein the first dielectric layer covers the sidewall surface of the source / drain layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first protective layer includes: forming a first protective material layer on the surface of the first dielectric layer, the surface of the source and drain layer, the side walls and the top surface of the gate structure; forming a mask layer on the surface of the first protective material layer, the mask layer exposing the surface of the first protective material layer on the second area; etching the first protective material layer using the mask layer as a mask until the surface of the first dielectric layer, the surface of the source and drain layer, the side walls and the top surface of the gate structure on the second area are exposed.

9. The method for forming a semiconductor structure according to claim 1, wherein: After injecting the second doping ions, it also includes: removing the mask layer; after removing the mask layer, forming a second dielectric layer on the substrate, the second dielectric layer is also located on the surface of the first protective layer, the surface of the source and drain layer, and the sidewall and surface of the gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

12. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes: a gate layer; a second spacer located on the sidewall of the gate layer; and a second protection layer located on the top of the gate layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the gate layer includes polysilicon.

14. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the source and drain layers includes: forming a first opening in the fins on both sides of the gate structure on the first region; forming a first epitaxial layer in the first opening, and injecting third doping ions into the first epitaxial layer to form a source and drain layer on the first region; forming a second opening in the fins on both sides of the gate structure on the second region; forming a second epitaxial layer in the second opening, and injecting fourth doping ions into the second epitaxial layer to form a source and drain layer on the second region.

15. The method for forming a semiconductor structure according to claim 14, wherein: The third doping ions include N-type or P-type ions, and the third doping ions have the same conductivity type as the first doping ions; the fourth doping ions include N-type or P-type ions, and the fourth doping ions have the same conductivity type as the second doping ions.

16. The method for forming a semiconductor structure according to claim 1, wherein: The first doping ions include N-type or P-type ions; the second doping ions include N-type or P-type ions, and the conductivity type of the second doping ions is different from the conductivity type of the first doping ions.

17. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask layer includes photoresist.

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