Semi-sgt mosfet device and method of manufacturing

Abstract

The application discloses a kind of semi-SGT MOSFET devices, comprising: first epitaxial layer and second epitaxial layer with first conductive type doping are formed on semiconductor substrate;Semi-SGT MOSFET device is divided into active region and terminal area;First epitaxial layer is divided into first area in active region and second area in the terminal area, and the doping concentration of first area and second area is independently set;The doping concentration of second epitaxial layer is higher than the doping concentration of first area, and the doping concentration of second area is lower than the doping concentration of first area, so that second area can be completely depleted when the device is reverse biased, to improve the withstand voltage value of terminal area.The application also discloses a kind of semi-SGT MOSFET device manufacturing method.The application can improve the breakdown voltage of terminal area while not affecting the performance of device unit in active region.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly to a kind of semi shielded gate trench (Shield Gate Trench, SGT) MOSFET device;The present application also relates to a kind of manufacturing method of semi SGT MOSFET device. BACKGROUND

[0002] Compared with traditional trench type (Trench) MOSFET, SGT MOSFET inserts longitudinal source field plate, i.e. source polysilicon in drift region. Source field plate and drift region are laterally depleted, so that the doping concentration of drift region can be greatly increased without reducing breakdown voltage, thereby reducing specific on-resistance and obtaining more excellent performance. There are two very common structures of SGT MOSFET, which are introduced as follows:

[0003] As shown in Figure 1 , it is a device unit structure schematic diagram of the existing first SGT MOSFET device. The existing first SGT MOSFET device is an up-down structure SGT MOSFET. Taking N-type device as an example, the gate structure of the existing first SGT MOSFET device is formed in the gate trench 101.

[0004] The gate trench 101 is formed in the first epitaxial layer 2 of N type. The first epitaxial layer 2 is formed on the N-type heavily doped semiconductor substrate 1. The semiconductor substrate 1 is usually in wafer structure.

[0005] Generally, the semiconductor substrate 1 is a heavily doped structure and is thinned on the back as a drain region. In order to reduce the semiconductor substrate 1 back diffusion, the semiconductor substrate 1 usually selects arsenic (Arsenic) doped substrate. However, because the lowest resistivity that can be achieved by phosphorus (Phosphorus) doped substrate in current process is lower than that of Arsenic doped substrate. Therefore, in the case of high substrate resistance ratio, such as low-voltage devices below 40V, Phosphorus doped substrate is also often used. The thinner the semiconductor substrate 1, the better the heat dissipation of the device, and the more significant the reduction of substrate resistance.

[0006] Figure 1 The gate structure is an up-down structure gate structure, and the source polysilicon 4 is formed at the bottom of the gate trench 101, and the source polysilicon 4 and the gate trench 101 are isolated by the shielding dielectric layer 3. The shielding dielectric layer 3 needs to withstand the breakdown voltage of the device, so the higher the breakdown voltage required by the device, the thicker the thickness of the shielding dielectric layer 3.

[0007] A polysilicon gate 6 is formed on top of the gate trench 101, and a gate dielectric layer, such as a gate oxide layer 5, is isolated between the polysilicon gate 6 and the gate trench 101. An inter-silicon oxide layer is isolated between the polysilicon gate 6 and the source polysilicon 4.

[0008] A P-type doped channel region 7 is formed in the surface region of the first epitaxial layer 2. The junction depth of the channel region 7 is less than or equal to the depth of the first side surface of the polysilicon gate 6. The surface of the channel region 7 covered by the first side surface of the polysilicon gate 6 is used to form the channel.

[0009] The first epitaxial layer 2 below the channel region 7 forms the drift region. The biggest difference between SGT MOSFET and traditional Trench MOSFET is that vertical source polysilicon 4 is inserted laterally into the drift region.

[0010] An N-type heavily doped source region 8 is formed on the surface of the channel region 7.

[0011] The N-type heavily doped drain region is composed of the thinned semiconductor substrate 1 or is composed of the thinned semiconductor substrate 1 superimposed with the N-type heavily doped back ion implantation region.

[0012] It also includes: an interlayer film 11, a contact hole (CT) 9 passing through the interlayer film 11, the bottom of the contact hole 9 corresponding to the top of the source region 8 also passing through the source region 8 to achieve simultaneous contact with the source region 8 and the channel region 7; the source and gate are patterned by the front metal layer 10, the source is connected to the source region 8 and the channel region 7 through the contact hole 9 corresponding to the bottom; the source polysilicon 4 is also connected to the source through the contact hole 9 corresponding to the top; the gate is connected to the polysilicon gate 6 through the contact hole corresponding to the bottom.

[0013] like Figure 2 The diagram shown is a schematic of the design structure of the second type of existing SGT MOSFET device. This second type of SGT MOSFET device is a left-right structure SGT MOSFET device; and Figure 1 The difference between the existing first type of SGT MOSFET device shown is that the existing second type of SGT MOSFET device has the following characteristics:

[0014] The polysilicon gate 6a adopts a left-right structure. This left-right structured polysilicon gate 6a is formed after the source polysilicon 4 and the shielding dielectric layer 3 are formed, the shielding dielectric layer 3 is etched back, and then the gate dielectric layer 5a and the polysilicon gate 6a are filled in the area where the shielding dielectric layer 3 is removed.

[0015] As can be seen from the above, the biggest difference between the first and second types of existing SGT MOSFET devices is:

[0016] The position between polysilicon gate and source polysilicon, Figure 1 The polysilicon gate 6 in the up-down structure is located directly above the source polysilicon 4. Figure 2 The polysilicon gate 6a in the left-right structure is located on both sides of the source polysilicon 4.

[0017] The advantages and disadvantages of the two structures are as follows:

[0018] The process implementation of the up-down structure is more complex, because the source polysilicon 4 is covered by the polysilicon gate 6 directly above, so that the source polysilicon 4 cannot be directly connected with the contact via, and an additional photomask and process step are needed.

[0019] The process implementation of the left-right structure is simple, and no particularly complex process step is needed. All structures such as the polysilicon gate 6a and the source polysilicon are on the surface of the chip, i.e. the surface of the first epitaxial layer 2, and can be directly connected. However, compared with the up-down structure, the contact area of the polysilicon gate and the source polysilicon is larger in the left-right structure, so that the input capacitance is also larger.

[0020] In order to provide higher output power, in addition to the need to increase the output current, it is necessary to make the on-resistance of the MOSFET as low as possible, and it is also necessary to increase the output voltage, which requires increasing the breakdown voltage of the MOSFET.

[0021] The SGT MOSFET has a lower specific on-resistance compared with the Trench MOSFET, so that a lower resistance can be achieved, and the SGT MOSFET is increasingly replacing the Trench MOSFET in more and more occasions.

[0022] However, the SGT MOSFET has a problem, if the breakdown voltage of the device is higher, it requires:

[0023] 1. The depth of the gate trench 101 is deeper, and the length of the source field plate, i.e. the source polysilicon 4, is longer.

[0024] 2. The thickness of the shielding dielectric layer 3 is thicker; usually the shielding dielectric layer 3 is composed of an oxide layer.

[0025] This brings great difficulty to the process implementation. Moreover, even if the process can be implemented, stress problems will also be caused. The stress problem will also cause the alignment accuracy to be poor, and the most important alignment is the alignment accuracy of the CT, which will increase the threshold fluctuation.

[0026] In order to reduce the cost of the device, the power device is currently being transferred from 8 inches to 12 inches to reduce the production cost of the device. The stress problem is more serious in 12 inches than in 8 inches. 8 inches to 12 inches refers to the diameter of the wafer on which the device is formed.

[0027] More importantly, in current SGT MOSFETs, the source field plate voltage is a fixed potential of 0V, while the drift region voltage gradually increases from near the source voltage to the drain voltage. The voltage difference between them gradually increases. This leads to a gradual weakening of the depletion capability of the drift region. This results in a non-uniform distribution of the electric field intensity within the bulk, causing the trench depth to be non-linear with breakdown voltage. This necessitates a deeper gate trench 101 required for high-voltage devices, further exacerbating stress problems.

[0028] Therefore, SGT MOSFETs with a breakdown voltage above 150V are typically half-SGT MOSFETs. A half-SGT can be considered as an SGT + Trench MOSFET. For example... Figure 3 The diagram shown is a schematic of the device cell structure of an existing half-SGT MOSFET device. Figure 3 This shows a typical 250V SGT implementation, which is a half-SGT implementation. Figure 3 The existing half-SGT MOSFET shown and Figure 2 The difference between the existing SGT MOSFET shown is that it will... Figure 3 The 250V breakdown voltage is withstandn in two parts:

[0029] 1. The epitaxial layer 2a has a relatively low doping concentration and is used to achieve a 100V withstand voltage. The principle is similar to that of a conventional trench MOSFET such as VDMOS, where the drain voltage vertically depletes the epitaxial layer 2a to achieve the withstand voltage. A typical condition for achieving a 100V withstand voltage is that the thickness of the drift region corresponding to the epitaxial layer 2a is between 8μm and 10μm, and the corresponding resistivity is between 2.0Ω*cm and 3.5Ω*cm.

[0030] 2. The epitaxial layer 2b has a relatively high doping concentration and is used to implement a 150V SGT MOSFET. The depletion of the epitaxial layer 2b is mainly achieved through the lateral depletion of the source polysilicon 4. Due to the high doping concentration of the epitaxial layer 2b, the longitudinal depletion of the drain voltage is relatively small or negligible. A typical process condition is a drift region thickness of 7μm to 11μm, corresponding to a resistivity between 0.3Ω*cm and 0.6Ω*cm.

[0031] The shielding dielectric layer 33 is usually selected to be silicon dioxide, and the corresponding thickness is between 0.8 μm and 1.2 μm. In the case described here, the doping concentration of the drift region is uniform. As described above, the voltage difference between the source polysilicon 3 and the drift region gradually increases with the longitudinal depth. In order to make the distribution of the electric field strength in the body of the SGT part closer to the ideal, the doping concentration of the epitaxial layer 2b part can be changed, a two-layer or multi-layer doping concentration drift region can be used, or a gradual doping can be used.

[0032] Note that in the structure shown in Figure 3 , in order to achieve better voltage resistance, the gate trench 101 needs to pass through the epitaxial layer 2b and reach the epitaxial layer 2a. Otherwise, the voltage resistance of the VDMOS part will not reach the expected value.

[0033] There is a very big difference in the distribution of the electric field strength in the body between the half SGT and the full SGT at the time of breakdown.

[0034] As shown in Figure 4A , the electric field strength distribution in the body at the time of breakdown of the device unit structure of the existing second SGT MOSFET device with a corresponding breakdown voltage of 150 V is shown in Figure 2 . Figure 2 The simulation of a half cell, i.e. a half device unit structure, is shown in Figure 4B , the electric field strength distribution in the body at the time of breakdown of the device unit structure of the existing half SGT MOSFET device with a corresponding breakdown voltage of 250 V is shown in Figure 3 . By comparing Figure 4A and Figure 4B , it can be seen that:

[0035] Figure 4B The simulation diagram before the bottom surface of the gate trench 101 of Figure 4A is the same as the upper part of the electric field strength simulation diagram of the 250 V SGT.

[0036] Figure 4B The only difference between Figure 4A and Figure 4B is that the epitaxial layer 2a is added to the 250 V SGT, and the epitaxial layer 2a is a relatively light area, which will be depleted and thus also withstand voltage. This makes Figure 4A and have a very big difference in the distribution of the electric field strength:

[0037] In the structure of the 150 V SGT, the edge of the corresponding depletion region marked 102 basically stops at the bottom of the gate trench 101 and does not extend. This is because, Figure 2The first epitaxial layer 2 in the middle has a high doping concentration. Without the help of the lateral depletion of the source polysilicon 4, the vertical depletion of the drain voltage alone cannot achieve the depletion of the first epitaxial layer 2 at the bottom of the gate trench 101.

[0038] For the 250V SGT structure, the depletion region corresponding to mark 103 extends significantly downwards from the bottom of the gate trench 101. This extension is the reason for the increased breakdown voltage (BV).

[0039] For traditional SGT structures such as Figure 2 The existing second type of SGT MOSFET device shown here, because the depletion region stops at the bottom of the gate trench 101 and does not widen downwards, can therefore adopt the simple termination structure illustrated. Figure 5 The diagram shown is a schematic representation of the active region and termination region of an existing second type of SGT MOSFET device. Figure 5 The image shows the active region 102 and the terminal region 103 located at the outer edge of the active region 102. The active region 102 includes multiple device unit structures. Figure 5 The image shows a device unit outlined in dashed box 104. The device unit structure within dashed box 104 and... Figure 2 The same applies. In the terminal region 103, a gate trench 101a is also provided, in which a shielding dielectric layer 3a and a source polysilicon 4a are provided, and a polysilicon gate 6a is also provided on the side of the source polysilicon 4a near the active region 102. Figure 5 In the process, the depletion region of the termination region 103 also ends at the bottom of the gate trench 101, so the sizes of the depletion regions of the active region 101 and the termination region 102 are approximately the same. Figure 5 The simple terminal structure in the terminal area 103 shown can meet the requirements.

[0040] But for Figure 3 The half-SGT MOSFET shown, if also using Figure 5 The structure of the terminal area 103 shown is about to Figure 5 Replace the epitaxial layer 2 in the middle with Figure 3 The stacked structure of epitaxial layers 2a and 2b in the middle requires depletion of the region of epitaxial layer 2a, and Figure 5 The terminal structure shown has no other gate trenches 101a to its right (outer side) of the gate trench 101a. That is, the gate trenches 101a in the terminal region 103 are not arranged alternately with the mesa regions between the gate trenches 101 and 101 as they are in the active region 102. This limits the widening of the depletion region by the source polysilicon 4a in the gate trench 101a of the terminal structure, thus increasing the electric field strength. Figure 5The electric field intensity of the bottom region of the gate trench 101a corresponding to the middle ring 105 increases, the first epitaxial layer 2 at the bottom of the ring 105 does not spread out, and finally the breakdown voltage of the device is reduced.

[0041] The simulation results show that, Figure 3 The half SGT shown in the figure must use Figure 5 The terminal structure shown in the figure reduces the BV by 30V.

[0042] Therefore, a more complex terminal structure must be used for the half SGT structure, and the BV of the terminal may be lower than that of the device cell region. SUMMARY

[0043] The technical problem to be solved by the present application is to provide a half SGT MOSFET device that can improve the breakdown voltage of the terminal region while not affecting the performance of the device cell in the active region. To this end, the present application also provides a manufacturing method for a half SGT MOSFET device.

[0044] To solve the above technical problems, the half SGT MOSFET device provided by the present application comprises:

[0045] A first epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate, and a second epitaxial layer doped with a first conductivity type is formed on the surface of the first epitaxial layer.

[0046] The half SGT MOSFET device is divided into an active region and a terminal region.

[0047] A plurality of device cells of the half SGT MOSFET device are formed in the active region, and the device cells comprise a gate structure formed in a gate trench and a source conductive layer formed in the gate trench; the gate trench passes through the second epitaxial layer.

[0048] In the active region, each of the gate trenches and the mesa regions between the gate trenches form an alternating arrangement structure.

[0049] The terminal structure in the terminal region comprises one or more terminal gate trenches passing through the second epitaxial layer, and a terminal source conductive material layer is formed in the terminal gate trench.

[0050] The first epitaxial layer is divided into a first region located in the active region and a second region located in the terminal region, and the doping concentrations of the first region and the second region are independently set.

[0051] The second epitaxial layer has a doping concentration higher than that of the first region, and the second region has a doping concentration lower than that of the first region, so that the second region can be fully depleted when the device is reverse biased, to improve the breakdown voltage of the terminal region.

[0052] A further improvement is that, in the active region, each of the source conductive material layers can produce a lateral depletion effect on the second epitaxial layer in the mesa region, the terminal source conductive material layer can produce a lateral depletion effect on the second epitaxial layer in the terminal region, and the terminal source conductive material layer produces a lateral depletion effect on the second epitaxial layer in the terminal region weaker than each of the source conductive material layers produces a lateral depletion effect on the second epitaxial layer in the mesa region, and the doping concentration of the second region is lowered to compensate for the weakening of the lateral depletion effect of the terminal source conductive material layer on the second epitaxial layer in the terminal region.

[0053] A further improvement is that, in the active region, the second epitaxial layer has a first breakdown voltage, the first epitaxial layer has a second breakdown voltage through longitudinal depletion, and the breakdown voltage of the semi-SGT MOSFET device in the active region is the sum of the first breakdown voltage and the second breakdown voltage;

[0054] The second epitaxial layer in the terminal region has a third breakdown voltage, and the second region has a fourth breakdown voltage through longitudinal depletion, and the breakdown voltage of the semi-SGT MOSFET device in the terminal region is the sum of the third breakdown voltage and the fourth breakdown voltage;

[0055] The doping concentration of the second region is lowered to improve the fourth breakdown voltage and make the breakdown voltage of the semi-SGT MOSFET device in the terminal region greater than or equal to that in the active region.

[0056] A further improvement is that, in the active region, the gate structure further comprises:

[0057] A gate conductive material layer, and the gate conductive material layer and the side surface of the corresponding gate trench are separated by a gate dielectric layer.

[0058] The source conductive material layer and the inner side surface of the corresponding gate trench are separated by a shielding dielectric layer.

[0059] The gate conductive material layer and the source conductive material layer are separated by a conductive material layer dielectric layer.

[0060] The gate structure is an up-down structure, and the gate conductive material layer is located directly above the source conductive material layer.

[0061] Or, the gate structure is left-right structure, and the gate conductive material layer is located on both sides of the top region of the source conductive material layer.

[0062] Further improvement is that, in the terminal area, a terminal gate conductive material layer is formed in the terminal gate trench or not.

[0063] Further improvement is that, in the active area, each of the device units further comprises:

[0064] A channel region composed of a well region doped with a second conductive type.

[0065] A source region doped with a first conductive type is formed on the surface of the channel region.

[0066] A drift region composed of the second epitaxial layer and the first epitaxial layer at the bottom of the channel region.

[0067] A drain region doped with a second conductive type is formed on the back surface of the semiconductor substrate.

[0068] A source electrode composed of a front metal layer is connected to the source region on the top through a via hole.

[0069] The source conductive material layer is also connected to the source electrode through a corresponding via hole on the top.

[0070] The gate conductive material layer is connected to a gate electrode composed of a front metal layer through a corresponding via hole on the top.

[0071] A back metal layer is formed on the back surface of the drain region and a drain electrode is composed of the back metal layer.

[0072] Further improvement is that, in the active area, the gate conductive material layer penetrates through the channel region and covers the channel region on the side.

[0073] The source conductive material layer covers the second epitaxial layer at the bottom of the channel region on the side; the deeper the gate trench is, the longer the longitudinal length of the source conductive material layer covering the second epitaxial layer is, and the greater the first withstand voltage is; the thicker the shielding dielectric layer is, the greater the first withstand voltage is; the deeper the gate trench is and the thicker the shielding dielectric layer is, the greater the stress of the semiconductor substrate is; the first withstand voltage is less than or equal to the maximum value defined by the stress of the semiconductor substrate.

[0074] Further improvement is that, in the terminal area, further comprises:

[0075] The well region which is the same as the well region composing the channel region in the active area.

[0076] No source region is formed on the surface of the well region.

[0077] The drift region and the drain region share the active region.

[0078] The terminal source conductive material layer is also connected to the source electrode through a corresponding via hole on the top.

[0079] A further improvement is that the maximum of the first breakdown voltage is less than or equal to 150V.

[0080] The thickness of the second epitaxial layer at the bottom of the channel region is 7-11μm.

[0081] The resistivity of the second epitaxial layer is 0.3-0.6Ω*cm.

[0082] A further improvement is that the shielding medium layer is an oxide layer, and the thickness of the shielding medium layer is 0.8-1.2μm.

[0083] A further improvement is that the second breakdown voltage is greater than or equal to 100V, and the thickness of the first epitaxial layer is 8-18μm; the doping concentration of the first region of the first epitaxial layer is 2.0-3.5Ω*cm.

[0084] A further improvement is that the doping concentration of the second region is 1 / 2, 1 / 3, 1 / 5 or 1 / 10 of the doping concentration of the first region.

[0085] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0086] The first epitaxial layer comprises a silicon epitaxial layer.

[0087] The second epitaxial layer comprises a silicon epitaxial layer.

[0088] The material of the source conductive material layer comprises polysilicon.

[0089] The process structure of the gate trench and the terminal gate trench is the same.

[0090] The process structure of the terminal source conductive material layer and the source conductive material layer is the same.

[0091] To solve the above technical problems, the manufacturing method of the semi-SGT MOSFET device provided by the present application adopts the following steps to form the first region and the second region:

[0092] The first epitaxial layer is formed on the semiconductor substrate according to the doping concentration of the second region.

[0093] The formation region of the first region is defined by photolithography, and the first region is opened.

[0094] The first conductive type ion implantation is performed to dope the first region and increase the doping concentration of the first region to a required value.

[0095] Further improvement is that the semiconductor substrate constitutes a wafer; the diameter of the wafer is 8 inches or above 12 inches.

[0096] To solve the above technical problems, the first region and the second region are formed by the following steps:

[0097] The first epitaxial layer is formed on the semiconductor substrate according to the doping concentration of the first region.

[0098] The second region is opened by photolithography to define the forming area of the second region.

[0099] The second conductive type ion implantation is performed to counter-dope the second region and decrease the doping concentration of the second region to a required value.

[0100] Further improvement is that the semiconductor substrate constitutes a wafer; the diameter of the wafer is 8 inches or above 12 inches.

[0101] The first epitaxial layer with a lower doping concentration than the second epitaxial layer is arranged at the bottom of the second epitaxial layer which can be covered by the side of the source conductive material layer, and the first epitaxial layer with a lower doping concentration can bear the longitudinal voltage resistance, so that the voltage resistance requirement of the semi-SGT MOSFET device is realized; at the same time, in order to overcome the problem that the terminal area voltage resistance is reduced due to the weak depletion of the second epitaxial layer caused by the limited number of terminal source conductive material layers, the doping concentrations of the first epitaxial layer in the active area and the terminal area are separately set, and the doping concentration of the second region of the first epitaxial layer in the terminal area is lower than that of the first region of the first epitaxial layer in the active area, so that the first epitaxial layer in the terminal area can be easily depleted, thereby improving the voltage resistance value of the terminal area and easily making the voltage resistance value of the semi-SGT MOSFET device in the terminal area higher than that in the active area; in this way, even if breakdown occurs, it will occur in the active area, and the breakdown current can be easily led out, thereby improving the performance of the device.

[0102] In addition, since the terminal area is not provided with a source area and thus cannot conduct electricity, the second region is only related to the voltage resistance of the device and is not related to the on-resistance of the device, so that the decrease of the doping concentration of the second region can improve the voltage resistance of the device without affecting the on-resistance of the device, that is, the performance of the device unit in the active area will not be affected.

[0103] In addition, the voltage resistance of the terminal region of the application can be improved by reducing the doping concentration of the second region, without complex terminal structure, so the application has the characteristic of simple process. BRIEF DESCRIPTION OF DRAWINGS

[0104] The application will be further described in detail below with reference to the drawings and specific embodiments:

[0105] Figure 1 is a device unit structure schematic diagram of the existing first SGT MOSFET device;

[0106] Figure 2 is a device unit structure schematic diagram of the existing second SGT MOSFET device;

[0107] Figure 3 is a device unit structure schematic diagram of the existing semi-SGT MOSFET device;

[0108] Figure 4A is Figure 2 is the body region distribution of the electric field intensity when the device unit structure of the corresponding existing second SGT MOSFET device is broken down;

[0109] Figure 4B is Figure 3 is the body region distribution of the electric field intensity when the device unit structure of the corresponding existing semi-SGT MOSFET device is broken down;

[0110] Figure 5 is a structure schematic diagram of the active region and the terminal region of the existing second SGT MOSFET device;

[0111] Figure 6 is a structure schematic diagram of the active region and the terminal region of the semi-SGT MOSFET device of the embodiment of the application;

[0112] Figures 7A-7B is a structure schematic diagram in the forming step of the first region and the second region of the first epitaxial layer in the manufacturing method of the first embodiment of the application;

[0113] Figures 8A-8B is a structure schematic diagram in the forming step of the first region and the second region of the first epitaxial layer in the manufacturing method of the second embodiment of the application. DETAILED DESCRIPTION

[0114] As Figure 6 shown, is the structure of the active region 402 and the terminal region 403 of the semi-SGT MOSFET device of the embodiment of the application; the semi-SGT MOSFET device of the embodiment of the application comprises:

[0115] A first epitaxial layer 302 of a first conductivity type is formed on a semiconductor substrate 301, and a second epitaxial layer 303 of the first conductivity type is formed on a surface of the first epitaxial layer 302.

[0116] The semi-SGT MOSFET device is divided into an active region 402 and a termination region 403.

[0117] A plurality of device units 404 of the semi-SGT MOSFET device are formed in the active region 402, Figure 6 Only one of the device units 404 is shown in the figure.

[0118] The device unit 404 includes a gate structure formed in a gate trench 401 and a source conductive material layer 304 formed in the gate trench 401; the gate trench 401 passes through the second epitaxial layer 303.

[0119] In the active region 402, each of the gate trenches 401 and the mesa regions between the gate trenches 401 form an alternating arrangement.

[0120] The termination region 403 has a termination structure including one or more termination gate trenches 401a passing through the second epitaxial layer 303, and a termination source conductive material layer 304a formed in the termination gate trench 401a.

[0121] The first epitaxial layer 302 is divided into a first region 3021 located in the active region 402 and a second region 3022 located in the termination region 403, and the doping concentrations of the first region 3021 and the second region 3022 are independently set.

[0122] The doping concentration of the second epitaxial layer 303 is higher than that of the first region 3021, and the higher doping concentration of the second epitaxial layer 303 can reduce the on-resistance of the device; at the same time, the second epitaxial layer 303 can be laterally depleted by the source conductive material layer 304, so as to maintain the withstand voltage capability of the second epitaxial layer 303.

[0123] The doping concentration of the second region 3022 is lower than that of the first region 3021, so that the second region 3022 can be completely depleted when the device is reverse biased, to the withstand voltage value of the termination region 403.

[0124] In the active region 402, each of the source conductive material layers 304 will cause lateral depletion to the second epitaxial layer 303 in the mesa region, the terminal source conductive material layer 304a will cause lateral depletion to the second epitaxial layer 303 in the terminal region 403, and the lateral depletion caused by the terminal source conductive material layer 304a to the second epitaxial layer 303 in the terminal region 403 is weaker than the lateral depletion caused by each of the source conductive material layers 304 to the second epitaxial layer 303 in the mesa region, and the weakening of the lateral depletion caused by the terminal source conductive material layer 304a to the second epitaxial layer 303 in the terminal region 403 is compensated by the reduced doping concentration of the second region 3022. Figure 5 Compared with the electric field intensity of the bottom region of the gate trench 101a corresponding to the ring 105 in the prior art and the spread to the first epitaxial layer 2, the electric field intensity of the bottom region of the gate trench 401a corresponding to the ring 405 in the embodiment of the present application is reduced, the second region 3022 is fully spread, i.e., fully depleted, and finally the breakdown voltage of the device is improved. Figure 6 Compared with the electric field intensity of the bottom region of the gate trench 101a corresponding to the ring 105 in the prior art and the spread to the first epitaxial layer 2, the electric field intensity of the bottom region of the gate trench 401a corresponding to the ring 405 in the embodiment of the present application is reduced, the second region 3022 is fully spread, i.e., fully depleted, and finally the breakdown voltage of the device is improved.

[0125] In the active region 402, the second epitaxial layer 303 has a first breakdown voltage, the first epitaxial layer 302 has a second breakdown voltage through longitudinal depletion, and the breakdown voltage of the semi-SGT MOSFET device in the active region 402 is the sum of the first breakdown voltage and the second breakdown voltage.

[0126] The second epitaxial layer 303 in the terminal region 403 has a third breakdown voltage, the second region 3022 has a fourth breakdown voltage through longitudinal depletion, and the breakdown voltage of the semi-SGT MOSFET device in the terminal region 403 is the sum of the third breakdown voltage and the fourth breakdown voltage.

[0127] The doping concentration of the second region 3022 is reduced to improve the fourth breakdown voltage and make the breakdown voltage of the semi-SGT MOSFET device in the terminal region 403 greater than or equal to the breakdown voltage in the active region 402.

[0128] In the embodiment of the present application, the doping concentration of the second region 3022 is 1 / 2, 1 / 3, 1 / 5, or 1 / 10 of the doping concentration of the first region 3021.

[0129] In the active region 402, the gate structure further comprises:

[0130] A gate conductive material layer 306, and a gate dielectric layer 305 is arranged between the gate conductive material layer 306 and the side surface of the corresponding gate trench 401.

[0131] The source conductive material layer 304 is separated from the inner side surface of the gate trench 401 by a shielding dielectric layer 303.

[0132] The gate conductive material layer 306 is separated from the source conductive material layer 304 by an interlayer dielectric layer of conductive material.

[0133] The gate structure is a left-right structure, and the gate conductive material layer 306 is located on both sides of the top area of the source conductive material layer 304. In other embodiments, it can also be an up-down structure, and the gate conductive material layer 306 is located directly above the source conductive material layer 304.

[0134] In the terminal area 403, a terminal gate conductive material layer 306a is formed in the terminal gate trench 401a or not.

[0135] In the active area 402, each device unit 404 further comprises:

[0136] A channel region composed of a well region 307 doped with a second conductive type.

[0137] A source region 308 heavily doped with a first conductive type is formed on the surface of the channel region.

[0138] A drift region composed of the second epitaxial layer 303 at the bottom of the channel region and the first epitaxial layer 302.

[0139] A drain region 309 heavily doped with a second conductive type is formed on the back of the semiconductor substrate 301.

[0140] The top of the source region 308 is connected to a source electrode composed of a front metal layer 310 through a via hole 309. The via hole 309 passes through an interlayer film 311.

[0141] The source conductive material layer 304 is also connected to the source electrode through the top corresponding via hole 309.

[0142] The gate conductive material layer 306 is connected to a gate electrode composed of a front metal layer 310 through the top corresponding via hole 309.

[0143] A back metal layer is formed on the back of the drain region and the drain electrode is composed of the back metal layer.

[0144] In the active area 402, the gate conductive material layer 306 passes through the channel region and laterally covers the channel region.

[0145] The source conductive material layer 304 covers the side of the second epitaxial layer 303 at the bottom of the channel region; the deeper the gate trench 401, the longer the longitudinal length of the second epitaxial layer 303 covered by the source conductive material layer 304, the greater the first voltage resistance; the thicker the shielding dielectric layer 303, the greater the first voltage resistance; the deeper the gate trench 401 and the thicker the shielding dielectric layer 303, the greater the stress of the semiconductor substrate 301; the first voltage resistance is less than or equal to the maximum value defined by the stress of the semiconductor substrate 301.

[0146] The terminal region 403 also includes:

[0147] The well region 307 is the same as the channel region in the active region 402.

[0148] The surface of the well region 307 does not form a source region 308.

[0149] The drift region and the drain region are shared with the active region 402.

[0150] The terminal source conductive material layer 304a is also connected to the source electrode through the corresponding via hole 309 at the top.

[0151] The semiconductor substrate 301 includes a silicon substrate.

[0152] The first epitaxial layer 302 includes a silicon epitaxial layer.

[0153] The second epitaxial layer 303 includes a silicon epitaxial layer.

[0154] The material of the source conductive material layer 304 includes polysilicon. The material of the gate conductive material layer 306 includes polysilicon.

[0155] The process structure of the gate trench 401 and the terminal gate trench 401a is the same.

[0156] The process structure of the terminal source conductive material layer 304a and the source conductive material layer 304 is the same.

[0157] The process structure of the terminal gate conductive material layer 306a and the gate conductive material layer 306 is the same.

[0158] The material of the gate dielectric layer 305 is an oxide layer, and the process conditions of the terminal gate dielectric layer are the same as those of the gate dielectric layer 305.

[0159] The material of the shielding dielectric layer 303 is an oxide layer, and the process conditions of the terminal shielding dielectric layer 303a are the same as those of the shielding dielectric layer 303.

[0160] The first embodiment of the present application is further illustrated below with specific parameters adopted in combination with a 250V half SGT MOSFET:

[0161] The maximum of the first breakdown voltage is less than or equal to 150V.

[0162] The thickness of the second epitaxial layer 303 at the bottom of the channel region is 7-11 μm.

[0163] The resistivity of the second epitaxial layer 303 is 0.3-0.6 Ω*cm.

[0164] The shielding dielectric layer 303 adopts an oxide layer, and the thickness of the shielding dielectric layer 303 is 0.8-1.2 μm.

[0165] The second breakdown voltage is greater than or equal to 100V, and the thickness of the first epitaxial layer 302 is 8-18 μm; the doping concentration of the first region 3021 of the first epitaxial layer 302 is 2.0-3.5 Ω*cm.

[0166] In the embodiment of the present application, the half SGT MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. It can also be that the half SGT MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0167] In the embodiment of the present application, the bottom of the second epitaxial layer 303 which can be covered by the side of the source conductive material layer 304 is provided with the first epitaxial layer 302 with a lower doping concentration than the second epitaxial layer 303, and the first epitaxial layer 302 with a lower doping concentration can bear the vertical breakdown voltage, thereby achieving the breakdown voltage requirement of the half SGT MOSFET device. Meanwhile, in order to overcome the problem that the terminal region 403 has a weak depletion of the second epitaxial layer 303 due to the limited number of terminal source conductive material layers 304a, thereby reducing the breakdown voltage of the terminal region 403, the doping concentration of the first epitaxial layer 302 in the active region 402 and the terminal region 403 is separately set, and the doping concentration of the second region 3022 of the first epitaxial layer 302 in the terminal region 403 is lower than the doping concentration of the first region 3021 of the first epitaxial layer 302 in the active region 402, so that the first epitaxial layer 302 in the terminal region 403 can be easily depleted, thereby increasing the breakdown voltage of the terminal region 403 and easily making the breakdown voltage of the half SGT MOSFET device in the terminal region 403 higher than that in the active region 402. In this way, even if breakdown occurs, it will occur in the active region 402, and the breakdown current can be easily led out, thereby improving the performance of the device.

[0168] In addition, since the terminal region 403 is not provided with the source region 308 and thus cannot conduct electricity, the second region 3022 is only related to the withstand voltage of the device and is not related to the on-resistance of the device, so that the doping concentration of the second region 3022 is reduced, which can improve the withstand voltage of the device without affecting the on-resistance of the device, that is, the performance of the device unit 404 of the active region 402 is not affected in the embodiment of the application.

[0169] As shown in FIG. 1, the first region 3021 and the second region 3022 of the first epitaxial layer in the manufacturing method of the first embodiment of the semi-SGT MOSFET device are formed. Figures 7A to 7B As shown in FIG. 1, the first region 3021 and the second region 3022 of the first epitaxial layer in the manufacturing method of the first embodiment of the semi-SGT MOSFET device are formed.

[0170] As shown in FIG. 1, the first region 3021 and the second region 3022 of the first epitaxial layer in the manufacturing method of the first embodiment of the semi-SGT MOSFET device are formed. Figure 7A As shown in FIG. 1, the first region 3021 and the second region 3022 of the first epitaxial layer in the manufacturing method of the first embodiment of the semi-SGT MOSFET device are formed. Figure 6 After the structure of the embodiment of the application shown in FIG. 1 is formed, the depth of the gate trench 301 and the thickness of the shielding dielectric layer 303 can be reduced, and a higher withstand voltage can be achieved, so that the stress of the wafer can be reduced, and the manufacturing process of the wafer with a large size can be applied.

[0171] The semiconductor substrate 301 is doped with a high-concentration first-conductivity-type. For a 250V semi-SGT, the resistivity of the first epitaxial layer 302 in FIG. 1 can be 15Ω*cm, which is much higher than the resistivity required to withstand 100V voltage. Figure 7A The resistivity of the first epitaxial layer 302 in FIG. 1 can be 15Ω*cm, which is much higher than the resistivity required to withstand 100V voltage.

[0172] As shown in FIG. 1, a photoresist pattern 501 is formed by a photolithography process to define the formation region of the first region 3021 and open the first region 3021. Figure 7B The first-conductivity-type ion implantation 502 is performed to dope the first region 3021 and increase the doping concentration of the first region 3021 to a required value.

[0173] The first-conductivity-type ion implantation 502 can be a single high-energy implantation such as 2MeV, and the implantation dose is 2e11cm3-2e12cm3 phosphorus implantation. Alternatively, the first-conductivity-type ion implantation 502 can be multiple implantations with different energies, so that the doping concentration in the drift region 2a is as uniform as possible.

[0174]

[0175] ​After implanting 502 ions of the first conductivity type, high-temperature annealing can be performed to make the distribution more uniform. Alternatively, the annealing process can be shared with the subsequent thermal processes of SGT.

[0176] like Figures 8A to 8B The diagram shown is a structural schematic of the formation steps of the first region and the second region of the first epitaxial layer in the manufacturing method of the SGT MOSFET device according to the second embodiment of the present invention. The second embodiment of the present invention uses the following steps to form the first region 3021 and the second region 3022:

[0177] like Figure 8A As shown, the first epitaxial layer 302 is formed on the semiconductor substrate 301 according to the doping concentration of the first region 3021. The semiconductor substrate 301 forms a wafer; the diameter of the wafer is 8 inches or 12 inches or more. This invention is formed by a method according to a first embodiment. Figure 6 The structure shown in the embodiment of the present invention can reduce the depth of the gate trench 301 and the thickness of the shielding dielectric layer 303, and achieve a higher withstand voltage, thereby reducing wafer stress and making it suitable for the manufacturing process of large-size wafers.

[0178] like Figure 8B As shown, a photoresist pattern 503 is formed using a photolithography process to define the formation area of ​​the second region 3022 and to open the second region 3022.

[0179] Perform second conductivity type ion implantation as indicated by label 504 to dedope the second region 3022 and reduce the doping concentration of the second region 3022 to the desired value.

[0180] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A half-SGT MOSFET device, characterized in that, include: A first epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate, and a second epitaxial layer doped with a first conductivity type is formed on the surface of the first epitaxial layer; A half-SGT MOSFET device is divided into an active region and a termination region; Multiple device units of the half-SGT MOSFET device are formed in the active region. Each device unit includes a gate structure formed in a gate trench and a source conductive material layer is formed in the gate trench. The gate trench passes through the second epitaxial layer; In the active region, each of the gate trenches and the mesa regions between the gate trenches form an alternating arrangement structure; The terminal region has a terminal structure, the terminal structure including one or more terminal gate trenches, the terminal gate trenches passing through the second epitaxial layer, and a terminal source conductive material layer formed in the terminal gate trenches; The first epitaxial layer is divided into a first region located in the active region and a second region located in the terminal region, and the doping concentrations of the first region and the second region are set independently; The doping concentration of the second epitaxial layer is higher than that of the first region, and the doping concentration of the second region is lower than that of the first region, so that the second region can be completely depleted when the device is reverse biased, thereby improving the breakdown voltage of the terminal region.

2. The half-SGT MOSFET device as described in claim 1, characterized in that: In the active region, when the device is reverse biased, each of the source conductive material layers will exert a lateral depletion effect on the second epitaxial layer in the mesa region, and the terminal source conductive material layer will exert a lateral depletion effect on the second epitaxial layer in the terminal region. The lateral depletion effect of the terminal source conductive material layer on the second epitaxial layer in the terminal region is weaker than the lateral depletion effect of each of the source conductive material layers on the second epitaxial layer in the mesa region. The reduction in doping concentration in the second region compensates for the weakening of the lateral depletion effect of the terminal source conductive material layer on the second epitaxial layer in the terminal region.

3. The half-SGT MOSFET device as described in claim 2, characterized in that: In the active region, when the device is reverse biased, the second epitaxial layer has a first breakdown voltage, and the first epitaxial layer has a second breakdown voltage through longitudinal depletion. The breakdown voltage of the half-SGT MOSFET device in the active region is the sum of the first breakdown voltage and the second breakdown voltage. The second epitaxial layer of the terminal region has a third breakdown voltage, the second region has a fourth breakdown voltage through longitudinal depletion, and the breakdown voltage of the half-SGT MOSFET device in the terminal region is the sum of the third breakdown voltage and the fourth breakdown voltage; The fourth breakdown voltage is increased by reducing the doping concentration in the second region, and the breakdown voltage of the half-SGT MOSFET device in the terminal region is greater than or equal to the breakdown voltage in the active region.

4. The half-SGT MOSFET device as described in claim 3, characterized in that: In the active region, the gate structure further includes: A gate conductive material layer, wherein a gate dielectric layer is spaced between the gate conductive material layer and the side surface of the corresponding gate trench; A shielding dielectric layer is spaced between the source conductive material layer and the inner surface of the corresponding gate trench. An interlayer dielectric layer of conductive material is provided between the gate conductive material layer and the source conductive material layer. The gate structure is an upper and lower structure, with the gate conductive material layer located directly above the source conductive material layer; Alternatively, the gate structure may be a left-right structure, with the gate conductive material layer located on both sides of the top region of the source conductive material layer.

5. The half-SGT MOSFET device as described in claim 4, characterized in that: In the terminal region, a terminal gate conductive material layer may or may not be formed in the terminal gate trench.

6. The half-SGT MOSFET device as described in claim 4, characterized in that: In the active region, each of the device units further includes: The channel region is composed of well regions doped with the second conductivity type; A source region heavily doped with a first conductivity type is formed on the surface of the channel region; The drift region is composed of the second epitaxial layer and the first epitaxial layer at the bottom of the channel region; A heavily doped drain region of the second conductivity type is formed on the back side of the semiconductor substrate; The top of the source region is connected to the source electrode, which is composed of a front-side metal layer, through a through-hole; The source conductive material layer is also connected to the source electrode through a corresponding through-hole at the top; The gate conductive material layer is connected to the gate composed of the front metal layer through a corresponding through-hole at the top; A back metal layer is formed on the back side of the drain region, and the back metal layer forms the drain electrode.

7. The half-SGT MOSFET device as described in claim 6, characterized in that: In the active region, the gate conductive material layer passes through the channel region and laterally covers the channel region; The source conductive material layer sideways covers the second epitaxial layer at the bottom of the channel region; the deeper the gate trench and the longer the longitudinal length of the source conductive material layer sideways covering the second epitaxial layer, the greater the first withstand voltage value; the thicker the shielding dielectric layer, the greater the first withstand voltage value; the deeper the gate trench and the thicker the shielding dielectric layer, the greater the stress on the semiconductor substrate; the first withstand voltage value is less than or equal to the maximum value limited by the stress on the semiconductor substrate.

8. The half-SGT MOSFET device as described in claim 6, characterized in that: The terminal area also includes: The well region is the same as the channel region that makes up the active region; No source region is formed on the surface of the well region; Both the drift region and the leak region are shared with the active region; The terminal source conductive material layer is also connected to the source electrode through a corresponding through-hole at the top.

9. The half-SGT MOSFET device as described in claim 7, characterized in that: The maximum value of the first withstand voltage is less than or equal to 150V; The thickness of the second epitaxial layer at the bottom of the channel region is 7 μm to 11 μm; The resistivity of the second epitaxial layer is 0.3Ω*cm to 0.6Ω*cm.

10. The half-SGT MOSFET device as described in claim 9, characterized in that: The shielding medium layer is an oxide layer, and the thickness of the shielding medium layer is 0.8μm to 1.2μm.

11. The half-SGT MOSFET device as described in claim 9, characterized in that: The second withstand voltage is greater than or equal to 100V, the thickness of the first epitaxial layer is 8μm to 18μm, and the doping concentration of the first region of the first epitaxial layer is 2.0Ω*cm to 3.5Ω*cm.

12. The half-SGT MOSFET device as described in claim 1, characterized in that: The doping concentration of the second region is 1 / 2, 1 / 3, 1 / 5 or 1 / 10 of the doping concentration of the first region.

13. The half-SGT MOSFET device as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate; The first epitaxial layer includes a silicon epitaxial layer; The second epitaxial layer includes a silicon epitaxial layer; The material of the source conductive material layer includes polycrystalline silicon; The gate trench and the terminal gate trench have the same process structure; The terminal source conductive material layer and the source conductive material layer have the same process structure.

14. The method for manufacturing a half-SGT MOSFET device as described in claim 1, characterized in that, The first region and the second region are formed using the following steps: The first epitaxial layer is formed on the semiconductor substrate according to the doping concentration of the second region; Photolithography defines the formation area of ​​the first region and opens the first region; First conductivity type ion implantation is performed to dope the first region and increase the doping concentration of the first region to the desired value.

15. The method for manufacturing a half-SGT MOSFET device as described in claim 14, characterized in that: The semiconductor substrate forms a wafer; the diameter of the wafer is 8 inches or 12 inches or more.

16. The method for manufacturing a half-SGT MOSFET device as described in claim 1, characterized in that, The first region and the second region are formed using the following steps: The first epitaxial layer is formed on the semiconductor substrate according to the doping concentration of the first region; Photolithography defines the formation area of ​​the second region and opens the second region; Second conductivity type ion implantation is performed to dedope the second region and reduce the doping concentration of the second region to the desired value.

17. The method for manufacturing a half-SGT MOSFET device as described in claim 16, characterized in that: The semiconductor substrate forms a wafer; the diameter of the wafer is 8 inches or 12 inches or more.

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