A non-isolated buck-type switched constant current source

Abstract

The present invention provides a non-isolated buck-type switched constant current source, comprising: a time-varying loop control voltage generation circuit, configured to generate a control current according to a loop control voltage, and simultaneously, under the control of a power switch tube drive signal and its inverted signal, generate a first time-varying current that follows the duty cycle of the conduction time of the power switch tube according to a reference voltage, and then generate a time-varying loop control voltage that follows the duty cycle of the conduction time of the power switch tube according to the control current and the first time-varying current; a time-varying conduction time generation circuit, connected to the output end of the time-varying loop control voltage generation circuit, configured to generate a second time-varying current that follows the duty cycle of the conduction time of the power switch tube according to a zero-temperature coefficient bias current under the control of the power switch tube drive signal and its inverted signal, and then generate a time-varying conduction time that follows the duty cycle of the conduction time of the power switch tube according to the time-varying loop control voltage and the second time-varying current, thereby obtaining a time-varying conduction time reach signal.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to a non-isolated buck switched constant current source. Background Art

[0002] The switching control architecture adopted by high-frequency switched constant current sources in mains LED lighting systems usually follows the fixed conduction time and inductor current approximate critical continuous switching control architecture commonly used in power factor correction power supplies.

[0003] In the inductor current critical continuous mode, in each switching cycle, once the inductor current drops to zero, the power switch is turned on again. However, at this time, the drain-source voltage of the power switch needs to drop from the maximum withstand voltage to nearly zero eventually, and its turn-on loss and the stress it bears are very large. To reduce the turn-on loss and stress of the power switch, the power switch is usually not turned on immediately when the inductor current drops to zero, but when the switching node voltage oscillates and the drain-source voltage of the power switch swings to the minimum value for the first time, the power switch is turned on, and its turn-on loss and stress are minimized; this is the inductor current approximate critical continuous mode, that is, the so-called quasi-resonant operating mode. In this mode, the oscillation duration of the switching node is very short, and the proportion of the oscillation current in the entire inductor current triangular waveform is also very small. It can be approximately considered that the inductor current waveform in the quasi-resonant mode is the same as the waveform in the inductor current critical continuous mode.

[0004] Currently, the switching control of common non-isolated buck switched constant current sources also adopts the fixed conduction time and quasi-resonant switching control architecture, and its power transfer stage and control loop are as Figure 1 shown, and its voltage and current waveforms are as Figure 2 shown. Among them, the AC bus voltage is rectified by a full-wave diode rectifier and then connected to the drain of the power switch M1 as the input of the buck power transfer stage; the voltage waveform on the current sampling resistor R CS in series with the inductor L represents the output current of the single-inductor buck power transfer stage. This current sampling voltage V CS is filtered by a low-pass filter (LPF) 100 to remove high-frequency switching glitches, and then differentially amplified with the reference voltage V REF by a transconductance error amplifier (EA) 200 to generate an integration current to charge and discharge the capacitor C COMP connected to the loop compensation COMP terminal, thereby generating a loop control voltage V COMP . After the power switch M1 is turned on in each switching cycle, the conduction time generation circuit 300 generates a conduction time according to the loop control voltage V COMPGenerate a conduction time arrival signal, which is processed by the logic control circuit 400 and then drives the power switch M1 to turn off by the drive circuit 500. The resistor voltage divider composed of the detection resistors R1 and R2 is connected in parallel with the inductor L, and the middle tap of the voltage divider is the detection DET terminal; after the power switch is turned off in each switching cycle, the diode D R Continues to conduct the inductor current. When the inductor current drops to zero, it causes the switching point SW to generate a ringing waveform; the zero current detection circuit 600 detects the detection voltage difference V DET -V SW from the DET terminal to the SW point. When the ringing waveform of this detection voltage difference changes from a positive value greater than zero to a value lower than zero, the zero current detection circuit 600 generates a zero current detection output signal, which is processed by the logic control circuit 400 and then drives the power switch M1 to conduct by the drive circuit 500, entering the next switching cycle, thereby forming a quasi-resonant switching control mode; among them, the operating frequency of the power switch M1 is usually in the order of dozens of kilohertz to hundreds of kilohertz.

[0005] Due to the differential amplification and integration effects of the transconductance error amplifier (EA) 200 and the loop compensation capacitor C COMP , the DC component of the current sampling voltage V CS is equal to the reference voltage V REF , thus ensuring a constant output current of the buck power transfer stage. In order to be compatible with achieving a high power factor for AC input, the output impedance of the transconductance error amplifier (EA) 200 and the loop bandwidth determined by the loop compensation capacitor C COMP are much lower than the 50 Hz power frequency of the mains. Under certain conditions of the mains AC voltage, the load LED lamp voltage, and the output current, after the switching constant current source enters the stable operating state, its loop control voltage V COMP fluctuates very little with the fluctuation of the mains AC voltage. The conduction time generation circuit 300 generates the conduction time of the power transistor basically independent of the power frequency of the mains according to the loop control voltage V COMP , forming a fixed conduction time switching control architecture.

[0006] The specific circuit of the conduction time generation circuit 300 in the above-mentioned existing non-isolated buck switching constant current source with a fixed conduction time and a quasi-resonant switching control architecture is as shown in Figure 3 , and its working waveform is as shown in Figure 4 ; among them, the loop control voltage V COMP is connected to the inverting input terminal of the comparator CMP, and the DRV signal in the same phase as the power switch drive signal is inverted by the inverter I and then connected to the gate of the NMOS transistor M N51 ; after the power switch M1 conducts, the DRV signal is at a high level. At this time, the NMOS transistor M N51 is turned off, and the zero temperature coefficient bias current I ZT charges the capacitor CTON Charging, when the voltage V TON at the upper end of the capacitor C CTON reaches the loop control voltage V COMP , the comparator CMP flips, and its output TONCMPO is a high-level narrow pulse signal. After being processed by the logic control circuit 400, this signal is used to drive the power switch tube M1 to turn off by the drive circuit 500. The amplifier OP is connected in the form of a unity-gain buffer. Its non-inverting input terminal is connected to a lower reference voltage V REF0 . When the power switch tube M1 is turned off, the DRV signal is at a low level. At this time, the NMOS tube M N51 conducts, and the capacitor C TON discharges until the voltage is equal to the output voltage of the amplifier OP, that is, the lower reference voltage V REF0 .

[0007] In the existing non-isolated buck-type switched constant current source, the power switch tube M1 of the single-inductor buck-type power transfer stage operates in a fixed conduction time and quasi-resonant switching control mode. Its inductor current operates in an approximately critical continuous mode, and the peak-to-peak value of the inductor current in each switching period where V IN is the pulsating DC input voltage, V OUT is the output voltage, L is the inductance value, and T ON is the conduction time of the power switch tube M1; thus, the average input current of the single-inductor buck-type power transfer stage with respect to the operating frequency of the power switch tube can be obtained where T OFF is the turn-off time of the power switch tube M1; for the single-inductor buck-type power transfer stage operating in an approximately critical continuous mode of the inductor current, according to the volt-second balance principle, there is where D is the duty cycle of the conduction time of the power switch tube M1 in each switching period; substituting it into the previous expression of the average input current, we can get

[0008] In the existing fixed conduction time and quasi-resonant switching control architecture, the conduction time T ON of the power switch tube M1 remains unchanged; for the mains lighting switched constant current source, the actual pulsating DC input voltage V IN of the single-inductor buck-type power transfer stage is the full-wave rectified voltage of the mains AC voltage V AC after diode full-wave rectification, and its fluctuation period is half of the mains AC power frequency period; from the above formula, it can be seen that the average input current I AVG of the single-inductor buck-type power transfer stage is not exactly proportional to the pulsating DC input voltage V IN , which contains (1 - D)·D, and this factor will vary with the pulsating DC input voltage V INThe waveform of the bun-shaped wave changes periodically; therefore, in the existing non-isolated buck-type switched constant current source that adopts a fixed conduction time and a quasi-resonant switching control mode, there is a large gap between the phase of its AC input current and the phase of the mains AC voltage, resulting in a not-high-enough AC input power factor (specifically as Figure 5 shown, at the leading edge of the average input current I AVG waveform, the current value is relatively high, while at the trailing edge of this waveform, the current value is relatively low, and the phase deviation between this waveform and the pulsating DC input voltage V IN of the bun-shaped wave is relatively large). SUMMARY OF THE INVENTION

[0009] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a non-isolated buck-type switched constant current source to solve the problem that the AC input power factor of the existing non-isolated buck-type switched constant current source is not high enough due to the large phase difference between the AC input current and the mains AC voltage.

[0010] To achieve the above purpose and other related purposes, the present invention provides a non-isolated buck-type switched constant current source, and the non-isolated buck-type switched constant current source includes:

[0011] A time-varying loop control voltage generating circuit, which is used to generate a control current according to the loop control voltage, and at the same time, under the control of the power switch tube drive signal and its inverted signal, generate a first time-varying current that follows the duty cycle of the power switch tube conduction time according to the reference voltage, and then generate a time-varying loop control voltage that follows the duty cycle of the power switch tube conduction time according to the control current and the first time-varying current;

[0012] A time-varying conduction time generating circuit, connected to the output end of the time-varying loop control voltage generating circuit, which is used to generate a second time-varying current that follows the duty cycle of the power switch tube conduction time according to the zero temperature coefficient bias current under the control of the power switch tube drive signal and its inverted signal, and then generate a time-varying conduction time that follows the duty cycle of the power switch tube conduction time according to the time-varying loop control voltage and the second time-varying current under the control of the inverted signal of the power switch tube drive signal, so as to obtain a time-varying conduction time reach signal.

[0013] Optionally, the time-varying loop control voltage generating circuit includes:

[0014] A control current generating module, which is used to generate a control initial current according to the loop control voltage, and then perform current mirroring on the control initial current to generate the control current;

[0015] The first time-varying current generating module is configured to generate a first time-varying initial current according to the reference voltage, and then generate the first time-varying current that follows the duty cycle of the power switch tube conduction time under the control of the power switch tube driving signal and its inverted signal;

[0016] The time-varying loop control voltage generating module is connected to the output end of the control current generating module and the output end of the first time-varying current generating module, and is configured to establish a linear relationship between the control current and the first time-varying current through a translinear loop, and generate the time-varying loop control voltage that follows the duty cycle of the power switch tube conduction time accordingly.

[0017] Optionally, the control current generating module includes: a first operational amplifier, a first NMOS transistor, a first resistor, a first PMOS transistor current mirror, and a first NMOS transistor current mirror. The non-inverting input terminal of the first operational amplifier is connected to the loop control voltage, the inverting input terminal of the first operational amplifier is connected to the source terminal of the first NMOS transistor, the output terminal of the first operational amplifier is connected to the gate terminal of the first NMOS transistor, the source terminal of the first NMOS transistor is connected to the control ground through the first resistor, the substrate terminal of the first NMOS transistor is connected to the control ground, the drain terminal of the first NMOS transistor is connected to the current input arm of the first PMOS transistor current mirror, the current output arm of the first PMOS transistor current mirror is connected to the current input arm of the first NMOS transistor current mirror, and the current output arm of the first NMOS transistor current mirror serves as the output terminal of the control current generating module; wherein, the current mirror ratio of the first PMOS transistor current mirror is 1:P1, and the current mirror ratio of the first NMOS transistor current mirror is 1:N1.

[0018] Optionally, the first time-varying current generating module includes:

[0019] The first time-varying initial current generating unit is configured to generate a reference corresponding current according to the reference voltage, and then perform current mirroring on the reference corresponding current to generate the first time-varying initial current;

[0020] The first time-varying current generating unit is connected to the output end of the first time-varying initial current generating unit, and is configured to selectively output the first time-varying initial current under the control of the power switch tube driving signal and its inverted signal, and then perform filtering and current mirroring on the output first time-varying initial current to generate the first time-varying current.

[0021] Optionally, the first time-varying initial current generating unit includes: a second operational amplifier, a second NMOS transistor, a second resistor, and a second PMOS transistor current mirror. The non-inverting input terminal of the second operational amplifier is connected to the reference voltage, the inverting input terminal of the second operational amplifier is connected to the source terminal of the second NMOS transistor, the output terminal of the second operational amplifier is connected to the gate terminal of the second NMOS transistor, the source terminal of the second NMOS transistor is connected to the control ground through the second resistor, the substrate terminal of the second NMOS transistor is connected to the control ground, the drain terminal of the second NMOS transistor is connected to the current input arm of the second PMOS transistor current mirror, and the current output arm of the second PMOS transistor current mirror serves as the output terminal of the first time-varying initial current generating unit; wherein, the current mirror ratio of the second PMOS transistor current mirror is 1:P2.

[0022] Optionally, the first time-varying current generating unit includes: a first PMOS transistor, a second PMOS transistor, a first inverter, a first capacitor, a third resistor, a third operational amplifier, and a second NMOS transistor current mirror. The source terminals of the first PMOS transistor and the second PMOS transistor are both connected to the output terminal of the first time-varying initial current generating unit, the substrate terminals of the first PMOS transistor and the second PMOS transistor are both connected to the control power supply voltage, the gate terminal of the first PMOS transistor is connected to the power switch transistor driving signal through the first inverter, the drain terminal of the first PMOS transistor is connected to the control ground, the gate terminal of the second PMOS transistor is connected to the power switch transistor driving signal, the drain terminal of the second PMOS transistor is connected to one end of the third resistor and one end of the first capacitor, the other end of the third resistor is connected to the non-inverting input terminal of the third operational amplifier and the current input arm of the second NMOS transistor current mirror, the other end of the first capacitor is connected to the output terminal of the third operational amplifier, the inverting input terminal of the third operational amplifier is connected to its output terminal, and the current output arm of the second NMOS transistor current mirror serves as the output terminal of the first time-varying current generating unit; wherein, the current mirror ratio of the second NMOS transistor current mirror is 1:N2.

[0023] Optionally, the time-varying loop control voltage generating module includes: a reference current source, a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a third PMOS transistor, a fourth PMOS transistor, a third PMOS transistor current mirror, a third NMOS transistor, and a fourth resistor. The current input terminal of the reference current source is connected to the control power supply voltage. The current output terminal of the reference current source is connected to the collector of the first NPN transistor and the base of the second NPN transistor. The emitter of the first NPN transistor is connected to the control ground. The base of the first NPN transistor is connected to the output terminal of the control current generating module and the emitter of the second NPN transistor. The collector of the second NPN transistor is connected to the drain terminal of the third PMOS transistor. The gate terminal of the third PMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the third PMOS transistor are both connected to the control power supply voltage. The base of the third NPN transistor is connected to the output terminal of the first time-varying current generating module and the emitter of the fourth NPN transistor. The emitter of the third NPN transistor is connected to the control ground. The collector of the third NPN transistor is connected to the current input arm of the third PMOS transistor current mirror. The base of the fourth NPN transistor is connected to the base of the second NPN transistor. The collector of the fourth NPN transistor is connected to the drain terminal of the fourth PMOS transistor. The gate terminal of the fourth PMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the fourth PMOS transistor are both connected to the control power supply voltage. The current output arm of the third PMOS transistor current mirror is connected to one end of the fourth resistor, which also serves as the output terminal of the time-varying loop control voltage generating module. The other end of the fourth resistor is connected to the drain terminal of the third NMOS transistor. The gate terminal of the third NMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the third NMOS transistor are both connected to the control ground. Wherein, the current mirror ratio of the third PMOS transistor current mirror is 1:P3.

[0024] Optionally, the time-varying conduction time generating circuit includes:

[0025] A second time-varying current generating module, configured to generate a second time-varying initial current according to the zero-temperature-coefficient bias current, and then generate a second time-varying current that follows the duty cycle of the power switch tube conduction time under the control of the power switch tube drive signal and its inverted signal;

[0026] A time-varying conduction time generation module, connected to the output end of the time-varying loop control voltage generation circuit and the output end of the second time-varying current generation module, is configured to charge a capacitor with the second time-varying current under the control of an inverted signal of the power switch tube drive signal, so as to generate a time-varying conduction time that follows the duty cycle change of the power switch tube conduction time when the capacitor terminal voltage reaches the time-varying loop control voltage.

[0027] Optionally, the second time-varying current generation module includes:

[0028] A second time-varying initial current generation unit, configured to generate a biased corresponding current according to the zero temperature coefficient bias current, and then perform current mirroring on the biased corresponding current to generate the second time-varying initial current;

[0029] A second time-varying current generation unit, connected to the output end of the second time-varying initial current generation unit, is configured to selectively output the second time-varying initial current under the control of the power switch tube drive signal and its inverted signal, and then filter and perform current mirroring on the output second time-varying initial current to generate the second time-varying current.

[0030] Optionally, the second time-varying initial current generation unit includes: a zero temperature coefficient bias current source, a fourth operational amplifier, a fourth NMOS transistor, a fifth resistor, a sixth resistor, and a fourth PMOS transistor current mirror. The current input end of the zero temperature coefficient bias current source is connected to the control power supply voltage. The current output end of the zero temperature coefficient bias current source is connected to one end of the fifth resistor and the non-inverting input end of the fourth operational amplifier. The other end of the fifth resistor is connected to the control ground. The inverting input end of the fourth operational amplifier is connected to the source terminal of the fourth NMOS transistor. The output end of the fourth operational amplifier is connected to the gate terminal of the fourth NMOS transistor. The source terminal of the fourth NMOS transistor is connected to the control ground through the sixth resistor. The substrate terminal of the fourth NMOS transistor is connected to the control ground. The drain terminal of the fourth NMOS transistor is connected to the current input arm of the fourth PMOS transistor current mirror. The current output arm of the fourth PMOS transistor current mirror serves as the output end of the second time-varying initial current generation unit; wherein, the current mirroring ratio of the fourth PMOS transistor current mirror is 1:P4.

[0031] Optionally, the second time-varying current generating unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a second inverter, a second capacitor, a seventh resistor, a fifth operational amplifier, a third NMOS transistor current mirror, and a fifth PMOS transistor current mirror. The source terminals of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the output terminal of the second time-varying initial current generating unit. The substrate terminals of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the control power supply voltage. The gate terminal of the fifth PMOS transistor is connected to the power switch transistor driving signal. The drain terminal of the fifth PMOS transistor is connected to the control ground. The gate terminal of the sixth PMOS transistor is connected to the power switch transistor driving signal through the second inverter. The drain terminal of the sixth PMOS transistor is connected to one end of the seventh resistor and one end of the second capacitor. The other end of the seventh resistor is connected to the non-inverting input terminal of the fifth operational amplifier and the current input arm of the third NMOS transistor current mirror. The other end of the second capacitor is connected to the output terminal of the fifth operational amplifier. The inverting input terminal of the fifth operational amplifier is connected to its output terminal. The current output arm of the third NMOS transistor current mirror is connected to the current input arm of the fifth PMOS transistor current mirror. The current output arm of the fifth PMOS transistor current mirror serves as the output terminal of the second time-varying current generating unit. Wherein, the current mirror ratio of the third NMOS transistor current mirror is 1:N3, and the current mirror ratio of the fifth PMOS transistor current mirror is 1:P5.

[0032] Optionally, the time-varying conduction time generating module includes: a comparator, a fifth NMOS transistor, a sixth NMOS transistor, a third capacitor, and a third inverter. The non-inverting input terminal of the comparator is connected to the output terminal of the second time-varying current generating module, the drain terminal of the fifth NMOS transistor, and one end of the third capacitor. The inverting input terminal of the comparator is connected to the output terminal of the time-varying loop control voltage generating circuit. The output terminal of the comparator serves as the output terminal of the time-varying conduction time generating module. The gate terminal of the fifth NMOS transistor is connected to the power switch transistor driving signal through the third inverter. The source terminal of the fifth NMOS transistor is connected to the drain terminal and the gate terminal of the sixth NMOS transistor. The substrate terminal of the fifth NMOS transistor, the substrate terminal of the sixth NMOS transistor, the source terminal of the sixth NMOS transistor, and the other end of the third capacitor are all connected to the control ground.

[0033] Optionally, the non-isolated buck switch constant current source further includes:

[0034] An input filter capacitor, one end of which is connected to the mains AC voltage through a rectifier bridge, and the other end is connected to the system ground, for performing high-frequency filtering on the pulsating DC voltage after rectifying the mains AC voltage by the rectifier bridge to generate a pulsating DC input voltage;

[0035] A power switch transistor, whose drain terminal is connected to one end of the input filter capacitor, whose source terminal is connected to the system ground through a series-connected inductor and capacitor, and is also connected to the system ground through a freewheeling diode. Its gate terminal is connected to a power switch transistor drive signal, which is used to control the charging and discharging of the branch where the inductor and capacitor are located according to its own conduction or cutoff, so as to adjust the output current and achieve constant current output;

[0036] A current sampling resistor, connected between the source terminal of the power switch transistor and the inductor, for sampling the output current;

[0037] A low-pass filter, connected to the connection point between the current sampling resistor and the source terminal of the power switch transistor, for performing low-pass filtering on the current sampling voltage;

[0038] A transconductance error amplifier, whose non-inverting input terminal is connected to a reference voltage, and whose inverting input terminal is connected to the output terminal of the low-pass filter, for differentially amplifying the reference voltage and the current sampling voltage after low-pass filtering to generate an integration current;

[0039] A compensation capacitor, one end of which is connected to the output terminal of the transconductance error amplifier and the input terminal of the time-varying loop control voltage generation circuit, and the other end of which is connected to the connection point between the current sampling resistor and the inductor and is connected to the control ground, for charging and discharging the capacitor according to the integration current to generate a loop control voltage;

[0040] A resistor voltage divider, connected to both ends of the inductor, for dividing the voltage across the inductor to generate a detected voltage difference;

[0041] A zero-current detection circuit, connected to the output terminal of the resistor voltage divider, for detecting the detected voltage difference and generating a zero-current detection output signal when the ringing waveform of the detected voltage difference changes from greater than zero to less than zero;

[0042] A logic control circuit, connected to the output terminal of the time-varying conduction time generation circuit and the output terminal of the zero-current detection circuit, for performing logic processing on the time-varying conduction time arrival signal or the zero-current detection output signal;

[0043] A drive circuit, connected to the output terminal of the logic control circuit, for generating a power switch transistor drive signal according to the output of the logic control circuit to control the conduction or cutoff of the power switch transistor.

[0044] As described above, a non-isolated buck-type switched constant current source of the present invention replaces the existing conduction time generation circuit with a newly designed time-varying loop control voltage generation circuit and a time-varying conduction time generation circuit, forming a new time-varying conduction time and quasi-resonant switching control architecture. By making the conduction time of the power switch tube follow the duty cycle of the conduction time of the power switch tube, the phase of the average input current of the non-isolated buck-type switched constant current source is corrected to be close to the phase of the pulsating DC input voltage, that is, the phase of the AC input current is close to the phase of the mains AC voltage, thereby reducing the high-order harmonic components in the AC input current and improving the AC input power factor. Description of the Drawings

[0045] Figure 1 It shows a circuit structure block diagram of a non-isolated buck-type switched constant current source in an embodiment.

[0046] Figure 2 It shows the voltage and current waveform diagrams of a non-isolated buck-type switched constant current source in an embodiment.

[0047] Figure 3 It shows the specific circuit diagram of the conduction time generation circuit in a non-isolated buck-type switched constant current source in an embodiment.

[0048] Figure 4 It shows the working waveform diagram of the conduction time generation circuit in an embodiment.

[0049] Figure 5 It shows the waveform diagrams of the average input current of a non-isolated buck-type switched constant current source, the mains AC voltage, and the pulsating DC input voltage in an embodiment.

[0050] Figure 6 It shows a circuit structure block diagram of the non-isolated buck-type switched constant current source in an embodiment.

[0051] Figure 7 It shows the specific circuit diagram of the time-varying loop control voltage generation circuit in the non-isolated buck-type switched constant current source in an embodiment.

[0052] Figure 8 It shows the specific circuit diagram of the time-varying conduction time generation circuit in the non-isolated buck-type switched constant current source in an embodiment.

[0053] Figure 9 It shows the waveform diagrams of the average input current of a non-isolated buck-type switched constant current source, the mains AC voltage, and the pulsating DC input voltage in an embodiment.

[0054] Description of Component Labels

[0055] 100 Low-pass filter

[0056] 200 Transconductance Error Amplifier

[0057] 300 Turn - on Time Generation Circuit

[0058] 400 Logic Control Circuit

[0059] 500 Driver Circuit

[0060] 600 Zero - Current Detection Circuit

[0061] 700 Time - varying Loop Control Voltage Generation Circuit

[0062] 701 Control Current Generation Module

[0063] 702 First Time - varying Current Generation Module

[0064] 7021 First Time - varying Initial Current Generation Unit

[0065] 7022 First Time - varying Current Generation Unit

[0066] 703 Time - varying Loop Control Voltage Generation Module

[0067] 800 Time - varying Turn - on Time Generation Circuit

[0068] 801 Second Time - varying Current Generation Module

[0069] 8011 Second Time - varying Initial Current Generation Unit

[0070] 8012 Second Time - varying Current Generation Unit

[0071] 802 Time - varying Turn - on Time Generation Module Detailed Implementation Manner

[0072] The following describes the implementation manner of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] Please refer to Figures 6 to 9 Note that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0074] Such as Figure 6As shown in the figure, this embodiment provides a non-isolated buck-type switched constant current source, and the non-isolated buck-type switched constant current source includes:

[0075] A time-varying loop control voltage generating circuit 700, configured to generate a control current I COMP according to the loop control voltage V COMP . Meanwhile, under the control of the power switch tube driving signal DRV and its inverted signal, a first time-varying current I REF0 that follows the duty cycle change of the power switch tube conduction time is generated according to the reference voltage V DB . Then, according to the control current I COMP and the first time-varying current I DB , a time-varying loop control voltage V COMP_PFC that follows the duty cycle change of the power switch tube conduction time is generated;

[0076] A time-varying conduction time generating circuit 800, connected to the output end of the time-varying loop control voltage generating circuit 700, is configured to generate a second time-varying current I ZT that follows the duty cycle change of the power switch tube conduction time according to the zero temperature coefficient bias current I TON under the control of the power switch tube driving signal DRV and its inverted signal. Then, under the control of the inverted signal of the power switch tube driving signal DRV, a time-varying conduction time T COMP_PFC that follows the duty cycle change of the power switch tube conduction time is generated according to the time-varying loop control voltage V TON and the second time-varying current I ON , so as to obtain a time-varying conduction time arrival signal.

[0077] Wherein, the "power switch tube driving signal DRV and its inverted signal" can also be replaced by "a driving signal in the same phase as the power switch tube driving signal and its inverted signal", which has no substantial impact on this embodiment.

[0078] As an example, as Figure 6 shown, the non-isolated buck-type switched constant current source further includes:

[0079] An input filter capacitor C IN , one end of which is connected to the mains AC voltage V AC through a rectifier bridge, and the other end is connected to the system ground, and is configured to perform high-frequency filtering on the pulsating DC voltage after rectifying the mains AC voltage V AC by the rectifier bridge to generate a pulsating DC input voltage V IN ;

[0080] A power switch tube M1, whose drain terminal is connected to one end of the input filter capacitor C IN , and whose source terminal is connected to the system ground through a series-connected inductor L and capacitor COUT connected to the system, and also through the freewheeling diode D R connected to the system, whose gate terminal is connected to the power switch tube drive signal DRV, and is used to control the charging and discharging of the branch where the inductor and capacitor are located according to its own conduction or cutoff, so as to adjust the output current and achieve constant current output;

[0081] Current sampling resistor R CS , connected between the source terminal of the power switch tube M1 and the inductor L, and is used to sample the output current;

[0082] Low-pass filter 100, connected to the current sampling resistor R CS and the connection point of the source terminal of the power switch tube M1 (i.e., at node CS), and is used to perform low-pass filtering on the current sampling voltage;

[0083] Transconductance error amplifier 200, whose non-inverting input terminal is connected to the reference voltage V REF0 , whose inverting input terminal is connected to the output terminal of the low-pass filter 100, and is used to differentially amplify the reference voltage V REF0 and the current sampling voltage after low-pass filtering to generate an integral current;

[0084] Compensation capacitor C COMP , one end of which is connected to the output terminal of the transconductance error amplifier 200 and the input terminal of the time-varying loop control voltage generation circuit 700, and the other end is connected to the connection point of the current sampling resistor R CS and the inductor L (i.e., at node SW) and is connected to the control ground, and is used to charge and discharge the capacitor according to the integral current to generate a loop control voltage V COMP ;

[0085] Resistor divider, connected to both ends of the inductor L, and is used to divide the voltage across the inductor to generate a detected voltage difference;

[0086] Zero-current detection circuit 600, connected to the output terminal of the resistor divider, and is used to detect the detected voltage difference, and generate a zero-current detection output signal when the ringing waveform of the detected voltage difference changes from greater than zero to less than zero;

[0087] Logic control circuit 400, connected to the output terminal of the time-varying conduction time generation circuit 800 and the output terminal of the zero-current detection circuit 600, and is used to perform logic processing on the time-varying conduction time arrival signal or the zero-current detection output signal;

[0088] Drive circuit 500, connected to the output terminal of the logic control circuit 400, and is used to generate a power switch tube drive signal DRV according to the output of the logic control circuit 400 to control the conduction or cutoff of the power switch tube M1.

[0089] Specifically, the low-pass filter 100, the transconductance error amplifier 200, the logic control circuit 400, the drive circuit 500, and the zero-current detection circuit 600 are all existing circuit structures, and the specific circuit composition thereof is not limited in this example.

[0090] It should be noted that the "control ground" and "system ground" mentioned in this embodiment are both relative reference grounds, but they are not the same point; among them, the "control ground" is the potential zero point defined when analyzing the switching control loop including the low-pass filter 100, the transconductance error amplifier 200, the time-varying loop control voltage generation circuit 700, the time-varying conduction time generation circuit 800, the zero-current detection circuit 600, the logic control circuit 400, and the drive circuit 500, so that the voltage and current signals therein are easier to identify and analyze; while the "system ground" is the potential zero point defined when analyzing the single-inductor buck power transfer stage including the input capacitor C IN , the power switch M1, the inductor L, the output capacitor C OUT , the freewheeling diode D R , and the load LED string D1~D n ), so that the voltage and current signals therein are easier to identify and analyze. Correspondingly, the "control power supply voltage" described in this embodiment is to provide a low-voltage power supply voltage for the switching control loop with the control ground as the potential zero point, and its energy also comes from the pulsating DC voltage after rectifying the mains AC voltage. The specific voltage conversion circuit involved is well-known to those skilled in the art, so it will not be elaborated here.

[0091] As an example, as Figure 7 shown, the time-varying loop control voltage generation circuit 700 includes:

[0092] A control current generation module 701, configured to generate a control initial current I COMP according to the loop control voltage V 11 , and then perform current mirroring on the control initial current I 11 to generate the control current I COMP (that is, I 12 );

[0093] A first time-varying current generation module 702, configured to generate a first time-varying initial current I REF1 according to the reference voltage V 22 , and then, under the control of the power switch drive signal DRV and its inverted signal, generate the first time-varying current I 22 that follows the duty cycle change of the power switch conduction time according to the first time-varying initial current I DB (that is, I 24));

[0094] The time-varying loop control voltage generation module 703 is connected to the output end of the control current generation module 701 and the output end of the first time-varying current generation module 702, and is used to establish the control current I through a translinear loop COMP and the first time-varying current I DB a linear relationship therebetween, and thereby generate the time-varying loop control voltage V that follows the duty cycle change of the power switch tube conduction time COMP_PFC .

[0095] Specifically, as Figure 7 shown, the control current generation module 701 includes: a first operational amplifier OP1, a first NMOS transistor M N1 , a first resistor R1, a first PMOS transistor current mirror I cmp1 and a first NMOS transistor current mirror I cmn1 , the non-inverting input terminal of the first operational amplifier OP1 is connected to the loop control voltage V COMP , the inverting input terminal of the first operational amplifier OP1 is connected to the source terminal of the first NMOS transistor M N1 , the output terminal of the first operational amplifier OP1 is connected to the gate terminal of the first NMOS transistor M N1 , the source terminal of the first NMOS transistor M N1 is connected to the control ground through the first resistor R1, the substrate terminal of the first NMOS transistor M N1 is connected to the control ground, the drain terminal of the first NMOS transistor M N1 is connected to the current input arm of the first PMOS transistor current mirror I cmp1 , the current output arm of the first PMOS transistor current mirror I cmp1 is connected to the current input arm of the first NMOS transistor current mirror I cmn1 , the current output arm of the first NMOS transistor current mirror I cmn1 is used as the output terminal of the control current generation module 701; wherein, the current mirror ratio of the first PMOS transistor current mirror I cmp1 is 1:P1, and the current mirror ratio of the first NMOS transistor current mirror I cmn1 is 1:N1.

[0096] In this example, the first operational amplifier OP1, the first NMOS transistor M N1 and the first resistor R1 form a current-series negative feedback structure. From the equality of the voltages at the two input terminals of the first operational amplifier OP1, it can be obtained that At this time

[0097] Specifically, asFigure 7 As shown, the first time-varying current generation module 702 includes:

[0098] A first time-varying initial current generation unit 7021, configured to generate a reference corresponding current I according to the reference voltage V REF1 ; then, perform current mirroring on the reference corresponding current I 21 to generate the first time-varying initial current I 21 ; 22

[0099] A first time-varying current generation unit 7022, connected to the output end of the first time-varying initial current generation unit 7021, configured to selectively output the first time-varying initial current I under the control of the power switch tube drive signal DRV and its inverted signal 22 ; then, perform filtering and current mirroring on the output first time-varying initial current I 22 to generate the first time-varying current I DB (i.e., I 24 ).

[0100] Among them, as Figure 7 shown, the first time-varying initial current generation unit 7021 includes: a second operational amplifier OP2, a second NMOS transistor M N2 , a second resistor R2, and a second PMOS transistor current mirror I cmp2 . The non-inverting input terminal of the second operational amplifier OP2 is connected to the reference voltage V REF1 . The inverting input terminal of the second operational amplifier OP2 is connected to the source terminal of the second NMOS transistor M N2 . The output terminal of the second operational amplifier OP2 is connected to the gate terminal of the second NMOS transistor M N2 . The source terminal of the second NMOS transistor M N2 is connected to the control ground through the second resistor R2. The substrate terminal of the second NMOS transistor M N2 is connected to the control ground. The drain terminal of the second NMOS transistor M N2 is connected to the current input arm of the second PMOS transistor current mirror I cmp2 . The current output arm of the second PMOS transistor current mirror I cmp2 serves as the output end of the first time-varying initial current generation unit 7021. Among them, the current mirroring ratio of the second PMOS transistor current mirror I cmp2 is 1:P2.

[0101] In this example, the second operational amplifier OP2, the second NMOS transistor M N2and the second resistor R2 form a current-series negative feedback structure. From the equality of the voltages at the two input terminals of the second operational amplifier OP2, it can be obtained that At this time,

[0102] Among them, as Figure 7 shown, the first time-varying current generating unit 7022 includes: a first PMOS transistor M P1 , a second PMOS transistor M P2 , a first inverter I1, a first capacitor C1, a third resistor R3, a third operational amplifier OP3, and a second NMOS transistor current mirror I cmn2 . The source terminal of the first PMOS transistor M P1 and the source terminal of the second PMOS transistor M P2 are both connected to the output terminal of the first time-varying initial current generating unit 7021. The substrate terminals of the first PMOS transistor M P1 and the second PMOS transistor M P2 are both connected to the control power supply voltage VDD. The gate terminal of the first PMOS transistor M P1 is connected to the power switch transistor drive signal DRV through the first inverter I1. The drain terminal of the first PMOS transistor M P1 is connected to the control ground. The gate terminal of the second PMOS transistor M P2 is connected to the power switch transistor drive signal DRV. The drain terminal of the second PMOS transistor M P2 is connected to one end of the third resistor R3 and one end of the first capacitor C1. The other end of the third resistor R3 is connected to the non-inverting input terminal of the third operational amplifier OP3 and the current input arm of the second NMOS transistor current mirror I cmn2 . The other end of the first capacitor C1 is connected to the output terminal of the third operational amplifier OP3. The inverting input terminal of the third operational amplifier OP3 is connected to its output terminal. The current output arm of the second NMOS transistor current mirror I cmn2 is used as the output terminal of the first time-varying current generating unit 7022. Among them, the current mirror ratio of the second NMOS transistor current mirror I cmn2 is 1:N2.

[0103] In this example, when the power switch transistor M1 is turned on, the power switch transistor drive signal DRV is at a high level, and its inverted signal is at a low level. At this time, the first PMOS transistor M P1 is turned on, the second PMOS transistor M P2 is turned off, and the first time-varying initial current I 22 passes through the first PMOS transistor M P1Flows to the control ground; when the power switch tube M1 is turned off, the power switch tube drive signal DRV is at a low level, and its inverted signal is at a high level. At this time, the first PMOS tube M P1 Is turned off, and the second PMOS tube M P2 Is turned on, and the first time-varying initial current I 22 Flows through the second PMOS tube M P2 To the node F1; therefore, the drain current I P2 Of the second PMOS tube M D_MP2 Is a rectangular current wave with a high value of A low value of zero, and a high value duty cycle of (1 - D), where D is the conduction time duty cycle of the power switch tube.

[0104] The third resistor R3, the first capacitor C1, the third operational amplifier OP3, and the second NMOS tube current mirror I cmn2 Constitute a current filtering structure, where the third operational amplifier OP3 is connected as a unity-gain buffer, so that the voltage of the lower node F2 of the third resistor R3 is equal to the voltage of the lower node F3 of the first capacitor C1. At this time, the third resistor R3 and the first capacitor C1 can still be regarded as connected in parallel; at the same time, since the input current of the third operational amplifier OP3 is zero, the current I 23 Flowing through the third resistor R3 all flows into the current input arm of the second NMOS tube current mirror I cmn2 At this time It can be seen from the above formula that the third resistor R3 and the first capacitor C1 constitute a first-order filter to filter the drain current I P2 Of the second PMOS tube M D_MP2 After filtering, the current is converted and output through the second NMOS tube current mirror I cmn2 If the bandwidth frequency Of the first-order filter is much lower than the switching frequency of the power switch tube M1, it can be considered that the current flowing into the second NMOS tube current mirror I cmn2 Is the DC component I P2 Of the drain current I D_MP2 Of the second PMOS tube M 22 ·(1 - D), at this time

[0105] Specifically, as Figure 7 Shown, the time-varying loop control voltage generation module 703 includes: a reference current source I REF0 、A first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a third PMOS tube M P3 、A fourth PMOS tube MP4 and the third PMOS transistor current mirror I cmp3 and the third NMOS transistor M N3 and the fourth resistor R4. The current input end of the reference current source I REF0 is connected to the control power supply voltage VDD. The current output end of the reference current source I REF0 is connected to the collector of the first NPN transistor Q1 and the base of the second NPN transistor Q2. The emitter of the first NPN transistor Q1 is connected to the control ground. The base of the first NPN transistor Q1 is connected to the output end of the control current generation module 701 and the emitter of the second NPN transistor Q2. The collector of the second NPN transistor Q2 is connected to the drain end of the third PMOS transistor M P3 . The gate end of the third PMOS transistor M P3 is connected to its drain end. The source end and the substrate end of the third PMOS transistor M P3 are both connected to the control power supply voltage VDD. The base of the third NPN transistor Q3 is connected to the output end of the first time-varying current generation module 702 and the emitter of the fourth NPN transistor Q4. The emitter of the third NPN transistor Q3 is connected to the control ground. The collector of the third NPN transistor Q3 is connected to the current input arm of the third PMOS transistor current mirror I cmp3 . The base of the fourth NPN transistor Q4 is connected to the base of the second NPN transistor Q2. The collector of the fourth NPN transistor Q4 is connected to the drain end of the fourth PMOS transistor M P4 . The gate end of the fourth PMOS transistor M P4 is connected to its drain end. The source end and the substrate end of the fourth PMOS transistor M P4 are both connected to the control power supply voltage VDD. The current output arm of the third PMOS transistor current mirror I cmp3 is connected to one end of the fourth resistor R4 and simultaneously serves as the output end of the time-varying loop control voltage generation module 703. The other end of the fourth resistor R4 is connected to the drain end of the third NMOS transistor M N3 . The gate end of the third NMOS transistor M N3 is connected to its drain end. The source end and the substrate end of the third NMOS transistor M N3 are both connected to the control ground. Wherein, the current mirror ratio of the third PMOS transistor current mirror I cmp3 is 1:P3.

[0106] In this example, the first NPN transistor Q1, the second NPN transistor Q2, the third NPN transistor Q3, and the fourth NPN transistor Q4 form a transconductance linear loop. The relationship between the base-emitter voltages of each NPN transistor is V BE1 +V BE2 =V BE3 +V BE4 . If the base currents of each NPN transistor are ignored, then there is where I E1 , I E2 , I E3 , I E4 are the emitter currents of Q1, Q2, Q3, and Q4 respectively, V T is the thermoelectric potential, and I S1 , I S2 , I S3 , I S4 are the reverse saturation currents of the emitter junctions of Q1, Q2, Q3, and Q4 respectively; when the layout emitter areas of Q1, Q2, Q3, and Q4 are the same, there is I S1 =I S2 =I S3 =I S4 . Therefore, by transforming the above formula, we can get I E1 ·I E2 =I E3 ·I E4 .

[0107] Since the emitter current of Q1 is equal to the collector current and is the reference current I REF0 ; the emitter current of Q2 is the control current I COMP , the emitter current of Q3 is equal to the collector current and is I 31 , and the emitter current of Q4 is the first time-varying current I DB . Substituting into the previous formula, we have I REF0 ·I COMP =I 31 ·I DB , that is, there is Since I 32 =P3·I 31 , the voltage generated by the current I 32 on the fourth resistor R4 and the fourth PMOS transistor M P4 is Substituting the expressions of I COMP and I DB into the above formula, the time-varying loop control voltage

[0108] As an example, as Figure 8 shown, the time-varying conduction time generation circuit 800 includes:

[0109] A second time-varying current generation module 801, configured to generate a second time-varying initial current I according to the zero temperature coefficient bias current I ZT and then, under the control of the power switch tube drive signal DRV and its inverted signal, generate a second time-varying current I that follows the duty cycle change of the power switch tube conduction time 42 (i.e., I 42 ); TON (that is, I 45 );

[0110] A time-varying conduction time generation module 802, connected to the output end of the time-varying loop control voltage generation circuit 700 and the output end of the second time-varying current generation module 801, is configured to charge a capacitor through the second time-varying current I under the control of the inverted signal of the power switch tube drive signal DRV, so as to generate a time-varying conduction time T that follows the duty cycle change of the power switch tube conduction time when the capacitor terminal voltage V TON reaches the time-varying loop control voltage V CTON ; COMP_PFC (i.e., T ON );

[0111] Specifically, as Figure 8 shown, the second time-varying current generation module 801 includes:

[0112] A second time-varying initial current generation unit 8011, configured to generate a bias corresponding current I according to the zero temperature coefficient bias current I ZT and then perform current mirroring on the bias corresponding current I 41 to generate the second time-varying initial current I 41 ; 42

[0113] A second time-varying current generation unit 8012, connected to the output end of the second time-varying initial current generation unit 8011, is configured to select and output the second time-varying initial current I under the control of the power switch tube drive signal DRV and its inverted signal 42 and then perform filtering and current mirroring on the output second time-varying initial current I 42 to generate the second time-varying current I TON (i.e., I 45 );

[0114] Among them, as Figure 8 shown, the second time-varying initial current generation unit 8011 includes: a zero temperature coefficient bias current source I ZT , a fourth operational amplifier OP4, a fourth NMOS transistor M N4 , a fifth resistor R5, a sixth resistor R6, and a fourth PMOS transistor current mirror I​cmp4 , the current input terminal of the zero temperature coefficient bias current source I ZT is connected to the control power supply voltage VDD, and the current output terminal of the zero temperature coefficient bias current source I ZT is connected to one end of the fifth resistor R5 and the non-inverting input terminal of the fourth operational amplifier OP4. The other end of the fifth resistor R5 is connected to the control ground, and the inverting input terminal of the fourth operational amplifier OP4 is connected to the source terminal of the fourth NMOS transistor M N4 . The output terminal of the fourth operational amplifier OP4 is connected to the gate terminal of the fourth NMOS transistor M N4 . The source terminal of the fourth NMOS transistor M N4 is connected to the control ground through the sixth resistor R6. The substrate terminal of the fourth NMOS transistor M N4 is connected to the control ground. The drain terminal of the fourth NMOS transistor M N4 is connected to the current input arm of the fourth PMOS transistor current mirror I cmp4 . The current output arm of the fourth PMOS transistor current mirror I cmp4 serves as the output terminal of the second time-varying initial current generating unit 8011; wherein, the current mirror ratio of the fourth PMOS transistor current mirror I cmp4 is 1:P4.

[0115] In this example, the zero temperature coefficient bias current I ZT flows to the control ground through the fifth resistor R5, and the voltage generated on the fifth resistor R5 is V I = I ZT · R5; the fourth operational amplifier OP4, the fourth NMOS transistor M N4 and the sixth resistor R6 form a current-series negative feedback structure. From the equality of the voltages at the two input terminals of the fourth operational amplifier OP4, it can be obtained that At this time

[0116] Among them, as Figure 8 shown, the second time-varying current generating unit 8012 includes: a fifth PMOS transistor M P5 , a sixth PMOS transistor M P6 , a second inverter I2, a second capacitor C2, a seventh resistor R7, a fifth operational amplifier OP5, a third NMOS transistor current mirror I cmn3 , a fifth PMOS transistor current mirror I cmp5 . The source terminals of the fifth PMOS transistor M P5 and the sixth PMOS transistor M P6 are both connected to the output terminal of the second time-varying initial current generating unit 8011. The source terminal of the fifth PMOS transistor M P5The bottom end of the substrate and the sixth PMOS transistor M P6 The bottom ends of the substrates are all connected to the control power supply voltage VDD. The fifth PMOS transistor M P5 The gate terminal is connected to the power switch transistor drive signal DRV. The fifth PMOS transistor M P5 The drain terminal is connected to the control ground. The sixth PMOS transistor M P6 The gate terminal is connected to the power switch transistor drive signal DRV through the second inverter I2. The sixth PMOS transistor M P6 The drain terminal is connected to one end of the seventh resistor R7 and one end of the second capacitor C2. The other end of the seventh resistor R7 is connected to the non-inverting input terminal of the fifth operational amplifier OP5 and the current input arm of the third NMOS transistor current mirror I cmn3 The other end of the second capacitor C2 is connected to the output terminal of the fifth operational amplifier OP5. The inverting input terminal of the fifth operational amplifier OP5 is connected to its output terminal. The current output arm of the third NMOS transistor current mirror I cmn3 Is connected to the current input arm of the fifth PMOS transistor current mirror I cmp5 The current input arm of the fifth PMOS transistor current mirror I cmp5 The current output arm serves as the output terminal of the second time-varying current generating unit 8012; wherein, the current mirror ratio of the third NMOS transistor current mirror I cmn3 Is 1:N3, and the current mirror ratio of the fifth PMOS transistor current mirror I cmp5 Is 1:P5.

[0117] In this example, when the power switch transistor M1 is turned off, the power switch transistor drive signal DRV is at a low level, and its inverted signal is at a high level. At this time, the fifth PMOS transistor M P5 Conducts, the sixth PMOS transistor M P6 Is turned off, and the second time-varying initial current I 42 Flows to the control ground through the fifth PMOS transistor M P5 When the power switch transistor M1 is turned on, the power switch transistor drive signal DRV is at a high level, and its inverted signal is at a low level. At this time, the fifth PMOS transistor M P5 Is turned off, the sixth PMOS transistor M P6 Conducts, and the second time-varying initial current I 42 Flows to the node F4 through the sixth PMOS transistor M P6 Therefore, the drain current I P6 Of the sixth PMOS transistor M D_MP6 Is a rectangular current wave with a high value of A low value of zero, and a high value duty cycle of D, where D is the conduction time duty cycle of the power switch transistor.

[0118] The seventh resistor R7, the second capacitor C2, the fifth operational amplifier OP5, and the third NMOS transistor current mirror I cmn3 constitute a current filtering structure, where the fifth operational amplifier OP5 is connected as a unity-gain buffer, such that the voltage at the lower node F5 of the seventh resistor R7 is equal to the voltage at the lower node F6 of the second capacitor C2. At this time, the seventh resistor R7 and the second capacitor C2 can still be regarded as being in parallel; meanwhile, since the input current of the fifth operational amplifier OP5 is zero, the current I flowing through the seventh resistor R7 43 flows entirely into the current input arm of the third NMOS transistor current mirror I cmn3 At this time It can be seen from the above formula that the seventh resistor R7 and the second capacitor C2 constitute a first-order filter to filter the drain current I P6 of the sixth PMOS transistor M D_MP6 After filtering, the current passes through the third NMOS transistor current mirror I cmn3 and the fifth PMOS transistor current mirror I cmp5 for conversion and output; if the bandwidth frequency of the first-order filter is much lower than the switching frequency of the power switch transistor M1, it can be considered that the current flowing into the third NMOS transistor current mirror I cmn3 is the DC component I P6 ·D of the drain current I D_MP6 of the sixth PMOS transistor M 42 At this time

[0119] Specifically, as Figure 8 shown, the time-varying conduction time generation module 802 includes: a comparator CMP, a fifth NMOS transistor M N5 , a sixth NMOS transistor M N6 , a third capacitor C3, and a third inverter I3. The non-inverting input terminal of the comparator CMP is connected to the output terminal of the second time-varying current generation module 801, the drain terminal of the fifth NMOS transistor M N5 , and one end of the third capacitor C3. The inverting input terminal of the comparator CMP is connected to the output terminal of the time-varying loop control voltage generation circuit 700. The output terminal of the comparator CMP serves as the output terminal of the time-varying conduction time generation module 802. The gate terminal of the fifth NMOS transistor M N5 is connected to the power switch transistor drive signal DRV through the third inverter I3. The source terminal of the fifth NMOS transistor M N5 is connected to the drain terminal of the sixth NMOS transistor M N6 and the drain terminal of the sixth NMOS transistor M N6The gate terminal of the fifth NMOS transistor M N5 The substrate terminal of the sixth NMOS transistor M N6 The substrate terminal of the sixth NMOS transistor M N6 The source terminal and the other end of the third capacitor C3 are all connected to the control ground.

[0120] In this example, when the power switch transistor M1 is turned on, the power switch drive signal DRV is at a high level. At this time, the fifth NMOS transistor M N5 is turned off, and the second time-varying current I TON charges the third capacitor C3. When the voltage V CTON at the upper end of the third capacitor C3 reaches the time-varying loop control voltage V COMP_PFC , the comparator CMP flips, and its output TONCMPO generates a high-level narrow pulse. When the power switch transistor M1 is turned off, the power switch drive signal DRV is at a low level. At this time, the fifth NMOS transistor M N5 is turned on, and the third capacitor C3 discharges to a voltage equal to the gate-source voltage V N6 of the sixth NMOS transistor M GS_MN6 ; Therefore, the second time-varying current I TON charges the third capacitor C3 from the gate-source voltage V N6 of the sixth NMOS transistor M GS_MN6 to the time-varying loop control voltage V COMP_PFC . The time taken determines the time-varying on-time T ON of the power switch transistor. Then, there is I TON ·T ON =(V COMP_PFC -V GS_MN6 )·C3; Substitute the expressions of I TON and V COMP_PFC into the above formula, and approximately consider V GS_MN3 ≈V GS , then the time-varying on-time of the power switch transistor can be obtained If we let For a determined integrated circuit design, K is a constant that remains unchanged. Then the time-varying on-time

[0121] In the case where the inductor current is approximately in the critical continuous operating mode, the average input current of the non-isolated buck power transfer stage with respect to the switching frequency of the power switch where V IN is the pulsating DC input voltage, L is the inductance value, and D is the duty cycle of the on-time of the power switch transistor; Substitute the expression of the time-varying on-time T ON into the above formula, then there is where K is a constant and V COMP is the loop control voltage.

[0122] It can be seen that under the conditions of a certain determined mains AC voltage, load LED lamp voltage, and output current, after the switching constant current source enters the stable working state, the fluctuation amplitude of its loop control voltage V COMP can be basically ignored along with the fluctuation of the mains AC voltage; it can be known from the above formula that the average input current of the non-isolated buck-type switching constant current source described in this embodiment is proportional to the pulsating DC input voltage V IN is proportional.

[0123] The voltage and current waveforms of the non-isolated buck-type switching constant current source described in this embodiment are as Figure 8 shown: The mains AC voltage V AC is a sine waveform, and its frequency is the 50Hz mains power frequency; the pulsating DC input voltage V IN is a flat-top waveform, and its frequency is twice the power frequency. For the switching constant current source adopting the time-varying conduction time switching control architecture that changes with the duty cycle D of the current power switch tube conduction time proposed in this embodiment, the waveform of its average input current I AVG is as Figure 8 shown, and the phase of this waveform is basically the same as that of the pulsating DC input voltage V IN ; that is to say, the non-isolated buck-type switching constant current source described in this embodiment has the function of correcting the phase of the average input current, making the phase of the average input current close to the phase of the pulsating DC input voltage, that is, making the phase of the AC input current close to the phase of the mains AC voltage, thereby reducing the high-order harmonic components in the AC input current and improving the AC input power factor.

[0124] In summary, for a non-isolated buck-type switching constant current source of the present invention, a newly designed time-varying loop control voltage generation circuit and a time-varying conduction time generation circuit are used to replace the existing conduction time generation circuit, forming a new time-varying conduction time and quasi-resonant switching control architecture. By making the conduction time of the power switch tube follow the duty cycle of the power switch tube conduction time, the phase of the average input current of the non-isolated buck-type switching constant current source is corrected to be close to the phase of the pulsating DC input voltage, that is, making the phase of the AC input current close to the phase of the mains AC voltage, thereby reducing the high-order harmonic components in the AC input current and improving the AC input power factor. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0125] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A non-isolated step-down switched constant current source, characterized in that, The non-isolated buck-type switched constant current source includes: A time-varying loop control voltage generating circuit, which is used to generate a control current according to the loop control voltage. At the same time, under the control of the power switch tube driving signal and its inverted signal, a first time-varying current that follows the duty cycle of the power switch tube conduction time is generated according to the reference voltage. Then, a time-varying loop control voltage that follows the duty cycle of the power switch tube conduction time is generated according to the control current and the first time-varying current; A time-varying conduction time generating circuit, connected to the output end of the time-varying loop control voltage generating circuit, which is used to generate a second time-varying current that follows the duty cycle of the power switch tube conduction time according to the zero temperature coefficient bias current under the control of the power switch tube driving signal and its inverted signal. Then, under the control of the inverted signal of the power switch tube driving signal, a time-varying conduction time that follows the duty cycle of the power switch tube conduction time is generated according to the time-varying loop control voltage and the second time-varying current, so as to obtain a time-varying conduction time arrival signal; The non-isolated buck-type switched constant current source further includes: A transconductance error amplifier, whose non-inverting input terminal is connected to the reference voltage, and whose inverting input terminal is connected to the current sampling voltage, which is used to perform differential amplification on the reference voltage and the current sampling voltage to generate an integration current, wherein the current sampling voltage is generated by sampling the output current; A compensation capacitor, one end of which is connected to the output end of the transconductance error amplifier and the input end of the time-varying loop control voltage generating circuit, and the other end is connected to the control ground, which is used to charge and discharge the capacitor according to the integration current to generate the loop control voltage; A zero current detection circuit, which is used to generate a zero current detection output signal when the ringing waveform of the detected voltage difference changes from greater than zero to less than zero, wherein the detected voltage difference is generated by dividing the voltage across the inductor; A logic control circuit, connected to the output end of the time-varying conduction time generating circuit and the output end of the zero current detection circuit, which is used to perform logic processing on the time-varying conduction time arrival signal or the zero current detection output signal; A driving circuit, connected to the output end of the logic control circuit, which is used to generate a power switch tube driving signal according to the output of the logic control circuit to control the conduction or turn-off of the power switch tube.

2. The non-isolated step-down switching constant current source according to claim 1, characterized in that, The time-varying loop control voltage generating circuit includes: A control current generating module, which is used to generate a control initial current according to the loop control voltage, and then perform current mirroring on the control initial current to generate the control current; A first time-varying current generating module, which is used to generate a first time-varying initial current according to the reference voltage, and then generate the first time-varying current that follows the duty cycle of the power switch tube conduction time according to the first time-varying initial current under the control of the power switch tube driving signal and its inverted signal; A time-varying loop control voltage generation module is connected to the output end of the control current generation module and the output end of the first time-varying current generation module, and is used to establish a linear relationship between the control current and the first time-varying current through a translinear loop, and generate the time-varying loop control voltage that follows the duty cycle change of the conduction time of the power switch tube accordingly.

3. The non-isolated step-down switched constant current source according to claim 2, characterized in that, The control current generation module includes: a first operational amplifier, a first NMOS transistor, a first resistor, a first PMOS transistor current mirror, and a first NMOS transistor current mirror. The non-inverting input terminal of the first operational amplifier is connected to the loop control voltage. The inverting input terminal of the first operational amplifier is connected to the source terminal of the first NMOS transistor. The output terminal of the first operational amplifier is connected to the gate terminal of the first NMOS transistor. The source terminal of the first NMOS transistor is connected to the control ground through the first resistor. The substrate terminal of the first NMOS transistor is connected to the control ground. The drain terminal of the first NMOS transistor is connected to the current input arm of the first PMOS transistor current mirror. The current output arm of the first PMOS transistor current mirror is connected to the current input arm of the first NMOS transistor current mirror. The current output arm of the first NMOS transistor current mirror serves as the output terminal of the control current generation module. Among them, the current mirror ratio of the first PMOS transistor current mirror is 1:P1, and the current mirror ratio of the first NMOS transistor current mirror is 1:N1.

4. The non-isolated buck-type switched constant current source according to claim 2, wherein, The first time-varying current generation module includes: A first time-varying initial current generation unit is used to generate a reference corresponding current according to the reference voltage, and then perform current mirroring on the reference corresponding current to generate the first time-varying initial current. A first time-varying current generation unit is connected to the output end of the first time-varying initial current generation unit, and is used to selectively output the first time-varying initial current under the control of the power switch tube drive signal and its inverted signal, and then filter and perform current mirroring on the output first time-varying initial current to generate the first time-varying current.

5. The non-isolated buck-type switching constant current source according to claim 4, wherein The first time-varying initial current generation unit includes: a second operational amplifier, a second NMOS transistor, a second resistor, and a second PMOS transistor current mirror. The non-inverting input terminal of the second operational amplifier is connected to the reference voltage. The inverting input terminal of the second operational amplifier is connected to the source terminal of the second NMOS transistor. The output terminal of the second operational amplifier is connected to the gate terminal of the second NMOS transistor. The source terminal of the second NMOS transistor is connected to the control ground through the second resistor. The substrate terminal of the second NMOS transistor is connected to the control ground. The drain terminal of the second NMOS transistor is connected to the current input arm of the second PMOS transistor current mirror. The current output arm of the second PMOS transistor current mirror serves as the output terminal of the first time-varying initial current generation unit. Among them, the current mirror ratio of the second PMOS transistor current mirror is 1:P2.

6. The non-isolated buck-type switching constant current source according to claim 4, wherein The first time-varying current generating unit includes: a first PMOS transistor, a second PMOS transistor, a first inverter, a first capacitor, a third resistor, a third operational amplifier, and a second NMOS transistor current mirror. The source terminals of the first PMOS transistor and the second PMOS transistor are both connected to the output terminal of the first time-varying initial current generating unit. The substrate terminals of the first PMOS transistor and the second PMOS transistor are both connected to the control power supply voltage. The gate terminal of the first PMOS transistor is connected to the power switch transistor driving signal through the first inverter. The drain terminal of the first PMOS transistor is connected to the control ground. The gate terminal of the second PMOS transistor is connected to the power switch transistor driving signal. The drain terminal of the second PMOS transistor is connected to one end of the third resistor and one end of the first capacitor. The other end of the third resistor is connected to the non-inverting input terminal of the third operational amplifier and the current input arm of the second NMOS transistor current mirror. The other end of the first capacitor is connected to the output terminal of the third operational amplifier. The inverting input terminal of the third operational amplifier is connected to its output terminal. The current output arm of the second NMOS transistor current mirror serves as the output terminal of the first time-varying current generating unit; wherein, the current mirror ratio of the second NMOS transistor current mirror is 1:N2.

7. The non-isolated buck-type switched constant current source according to claim 2, wherein The time-varying loop control voltage generation module includes: a reference current source, a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a third PMOS transistor, a fourth PMOS transistor, a third PMOS transistor current mirror, a third NMOS transistor, and a fourth resistor. The current input terminal of the reference current source is connected to the control power supply voltage. The current output terminal of the reference current source is connected to the collector of the first NPN transistor and the base of the second NPN transistor. The emitter of the first NPN transistor is connected to the control ground. The base of the first NPN transistor is connected to the output terminal of the control current generation module and the emitter of the second NPN transistor. The collector of the second NPN transistor is connected to the drain terminal of the third PMOS transistor. The gate terminal of the third PMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the third PMOS transistor are both connected to the control power supply voltage. The base of the third NPN transistor is connected to the output terminal of the first time-varying current generation module and the emitter of the fourth NPN transistor. The emitter of the third NPN transistor is connected to the control ground. The collector of the third NPN transistor is connected to the current input arm of the third PMOS transistor current mirror. The base of the fourth NPN transistor is connected to the base of the second NPN transistor. The collector of the fourth NPN transistor is connected to the drain terminal of the fourth PMOS transistor. The gate terminal of the fourth PMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the fourth PMOS transistor are both connected to the control power supply voltage. The current output arm of the third PMOS transistor current mirror is connected to one end of the fourth resistor, and at the same time, it serves as the output terminal of the time-varying loop control voltage generation module. The other end of the fourth resistor is connected to the drain terminal of the third NMOS transistor. The gate terminal of the third NMOS transistor is connected to its drain terminal. The source terminal and the substrate terminal of the third NMOS transistor are both connected to the control ground; wherein, the current mirror ratio of the third PMOS transistor current mirror is 1:P3.

8. The non-isolated step-down switching constant current source according to claim 1, characterized in that, The time-varying conduction time generation circuit includes: A second time-varying current generation module, configured to generate a second time-varying initial current according to the zero temperature coefficient bias current, and then, under the control of the power switch tube drive signal and its inverted signal, generate a second time-varying current that follows the duty cycle change of the power switch tube conduction time according to the second time-varying initial current; A time-varying conduction time generation module, connected to the output terminal of the time-varying loop control voltage generation circuit and the output terminal of the second time-varying current generation module, configured to charge a capacitor through the second time-varying current under the control of the inverted signal of the power switch tube drive signal, so as to generate a time-varying conduction time that follows the duty cycle change of the power switch tube conduction time when the capacitor terminal voltage reaches the time-varying loop control voltage.

9. The non-isolated buck-type switched constant current source according to claim 8, wherein The second time-varying current generation module includes: A second time-varying initial current generating unit, configured to generate a bias corresponding current according to the zero temperature coefficient bias current, and then perform current mirroring on the bias corresponding current to generate the second time-varying initial current; A second time-varying current generating unit, connected to the output end of the second time-varying initial current generating unit, configured to selectively output the second time-varying initial current under the control of the power switch tube driving signal and its inverted signal, and then filter and perform current mirroring on the output second time-varying initial current to generate the second time-varying current.

10. The non-isolated buck-type switched constant current source according to claim 9, wherein The second time-varying initial current generating unit includes: a zero temperature coefficient bias current source, a fourth operational amplifier, a fourth NMOS transistor, a fifth resistor, a sixth resistor, and a fourth PMOS transistor current mirror. The current input end of the zero temperature coefficient bias current source is connected to the control power supply voltage. The current output end of the zero temperature coefficient bias current source is connected to one end of the fifth resistor and the non-inverting input end of the fourth operational amplifier. The other end of the fifth resistor is connected to the control ground. The inverting input end of the fourth operational amplifier is connected to the source end of the fourth NMOS transistor. The output end of the fourth operational amplifier is connected to the gate end of the fourth NMOS transistor. The source end of the fourth NMOS transistor is connected to the control ground through the sixth resistor. The substrate end of the fourth NMOS transistor is connected to the control ground. The drain end of the fourth NMOS transistor is connected to the current input arm of the fourth PMOS transistor current mirror. The current output arm of the fourth PMOS transistor current mirror serves as the output end of the second time-varying initial current generating unit; wherein, the current mirroring ratio of the fourth PMOS transistor current mirror is 1:P4.

11. The non-isolated step-down switching constant current source according to claim 9, wherein The second time-varying current generating unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a second inverter, a second capacitor, a seventh resistor, a fifth operational amplifier, a third NMOS transistor current mirror, and a fifth PMOS transistor current mirror. The source terminals of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the output terminal of the second time-varying initial current generating unit. The substrate terminals of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the control power supply voltage. The gate terminal of the fifth PMOS transistor is connected to the power switch transistor driving signal. The drain terminal of the fifth PMOS transistor is connected to the control ground. The gate terminal of the sixth PMOS transistor is connected to the power switch transistor driving signal through the second inverter. The drain terminal of the sixth PMOS transistor is connected to one end of the seventh resistor and one end of the second capacitor. The other end of the seventh resistor is connected to the non-inverting input terminal of the fifth operational amplifier and the current input arm of the third NMOS transistor current mirror. The other end of the second capacitor is connected to the output terminal of the fifth operational amplifier. The inverting input terminal of the fifth operational amplifier is connected to its output terminal. The current output arm of the third NMOS transistor current mirror is connected to the current input arm of the fifth PMOS transistor current mirror. The current output arm of the fifth PMOS transistor current mirror serves as the output terminal of the second time-varying current generating unit. Among them, the current mirror ratio of the third NMOS transistor current mirror is 1:N3, and the current mirror ratio of the fifth PMOS transistor current mirror is 1:P5.

12. The non-isolated step-down switched constant current source according to claim 8, characterized in that, The time-varying conduction time generating module includes: a comparator, a fifth NMOS transistor, a sixth NMOS transistor, a third capacitor, and a third inverter. The non-inverting input terminal of the comparator is connected to the output terminal of the second time-varying current generating module, the drain terminal of the fifth NMOS transistor, and one end of the third capacitor. The inverting input terminal of the comparator is connected to the output terminal of the time-varying loop control voltage generating circuit. The output terminal of the comparator serves as the output terminal of the time-varying conduction time generating module. The gate terminal of the fifth NMOS transistor is connected to the power switch transistor driving signal through the third inverter. The source terminal of the fifth NMOS transistor is connected to the drain terminal and the gate terminal of the sixth NMOS transistor. The substrate terminal of the fifth NMOS transistor, the substrate terminal of the sixth NMOS transistor, the source terminal of the sixth NMOS transistor, and the other end of the third capacitor are all connected to the control ground.

13. The non-isolated buck-type switched constant current source according to claim 1, characterized in that, The non-isolated buck-type switched constant current source further includes: An input filter capacitor, one end of which is connected to the mains AC voltage through a rectifier bridge, and the other end is connected to the system ground, for performing high-frequency filtering on the pulsating DC voltage after rectifying the mains AC voltage by the rectifier bridge to generate a pulsating DC input voltage; A power switch transistor, whose drain terminal is connected to one end of the input filter capacitor, whose source terminal is connected to the system ground through a series-connected inductor and capacitor, and is also connected to the system ground through a freewheeling diode. Its gate terminal is connected to a power switch transistor drive signal, which is used to control the charging and discharging of the branch where the inductor and capacitor are located according to its own conduction or cutoff, thereby adjusting the output current to achieve a constant current output; A current sampling resistor, connected between the source terminal of the power switch transistor and the inductor, which is used to sample the output current to generate the current sampling voltage; A low-pass filter, connected to the connection point between the current sampling resistor and the source terminal of the power switch transistor, which is used to perform low-pass filtering on the current sampling voltage; The inverting input terminal of the transconductance error amplifier is connected to the output terminal of the low-pass filter, which is used to differentially amplify the reference voltage and the current sampling voltage that has undergone low-pass filtering to generate an integrated current; A resistor divider, connected to both ends of the inductor, which is used to divide the voltage across the inductor to generate the detected voltage difference; The zero-current detection circuit is connected to the output terminal of the resistor divider.

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