A COT constant on-time circuit for high-power power management

Abstract

The present invention discloses a COT (Constant On-Time) circuit for high-power power management, belonging to the field of switching power supplies. It adopts the technology of accurately setting the current signals related to V<subgt;IN< / subgt> and R<subgt>ON< / subgt>, and accurately mirroring the current signals related to V<subgt;IN< / subgt> and R<subgt>ON< / subgt> to charge a capacitor. At the same time, through a single-shot timer and a comparator, the capacitor signal and a fixed voltage are compared, generating a technology of constant on-time related to V<subgt;IN< / subgt> and a switching frequency related to V<subgt;OUT< / subgt>. It solves the problem of achieving a constant frequency without using an internal oscillator, and at the same time realizes the self-control of the switching frequency.

Description

Technical Field

[0001] The present invention belongs to the field of switching power supplies, and particularly relates to a COT constant on-time circuit for high-power power management. Background Art

[0002] In the field of consumer electronics, various electronic devices need power supplies to operate. Switching power management chips are an indispensable part of electronic systems. Among them, the switching power supply with COT control mode has only a comparator in the loop, so the loop response is fast. Its excellent load transient response and smooth operation mode switching have been well applied in the power field. The architecture of a DC / DC converter with COT control mode can use a one-shot timer to generate a constant on-time T on , during which the internal main switch is turned on, and the on-time is determined by T on . After the on-time, the main switch must remain off until the divided feedback voltage of the output voltage is lower than the set value of the fixed reference again, and the one-shot timer circuit continues to work.

[0003] This one-shot timer generates a constant on-time T IN related to the power supply voltage V on , which is inversely proportional to the input voltage. Since the duty cycle D is V OUT / V IN , and T on is the duty cycle D divided by the switching frequency, this characteristic shows that when V OUT is fixed, the operating frequency is fixed and independent of the load. Therefore, a constant on-time circuit for a switching power supply with constant on-time control mode is needed, which can be used in a DC / DC converter with COT control mode architecture, where the constant on-time is related to V IN , and the switching frequency is related to V OUT . Summary of the Invention

[0004] In order to overcome the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a COT constant on-time circuit for high-power power management to solve the problem in the prior art that when V OUT is fixed, the operating frequency is fixed and independent of the load.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] The present invention discloses a COT constant on-time circuit for high-power power management, including a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a third P-type MOS transistor PM3, a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, a first N-type triode NPN1, a second N-type triode NPN2, a third N-type triode NPN3, a fourth N-type triode NPN4, and an external resistor R ON , a first resistor R1, a second resistor R2, a capacitor C1, and a comparator;

[0007] The gate of the first P-type MOS transistor PM1 is connected to the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, the gate of the fourth P-type MOS transistor PM4, and is connected to the external bias current IBIAS1. The drain of the second P-type MOS transistor PM2 is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, and the gate of the third N-type MOS transistor NM3. The drain of the third P-type MOS transistor PM3 is connected to the collector of the first N-type triode NPN1 and the gate of the fifth N-type MOS transistor NM5. The drain of the fourth P-type MOS transistor PM4 is connected to the collector of the second N-type triode NPN2 and the gate of the fourth N-type MOS transistor NM4. The gate of the fifth P-type MOS transistor PM5 is connected to the drain of the fifth P-type MOS transistor PM5, the gate of the sixth P-type MOS transistor PM6, and the collector of the fourth N-type triode NPN4. The drain of the sixth P-type MOS transistor PM6 is connected to the positive terminal of the capacitor c1 and the negative terminal of the comparator. The drain of the second N-type MOS transistor NM2 is connected to the source of the fourth N-type MOS transistor NM4, the base of the first N-type triode NPN1, and the base of the second N-type triode NPN2. The drain of the third N-type MOS transistor NM3 is connected to the source of the fifth N-type MOS transistor NM5, the base of the third N-type triode NPN3, and the base of the fourth N-type triode NPN4. The drain of the fourth N-type MOS transistor NM4 is connected to the internal power supply VCC. The drain of the fifth N-type MOS transistor NM5 is connected to the internal power supply VCC. The emitter of the first N-type triode NPN1 is connected to the resistor R ONOne end of it is connected to one end of the first resistor R1; the emitter of the second N-type triode NPN2 is connected to one end of the second resistor R2, the emitter of the third N-type triode NPN3, and the emitter of the fourth N-type triode NPN4; the collector of the third N-type triode NPN3 is connected to the internal power supply VCC, and the sources of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, and the sixth P-type MOS transistor PM6 are all connected to the internal power supply VCC, and the sources of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, and the third N-type MOS transistor NM3 are all connected to the ground GND.

[0008] Preferably, the resistor R ON is much larger than the first resistor R1, so that the current I at the port of the first resistor R1 R1 is V IN / R ON .

[0009] Preferably, the number of the first N-type triodes NPN1 is m times that of the second N-type triodes NPN2, the resistance value of the second resistor R2 is m times that of the first resistor R1, and I NPN1 is m times of I NPN2 , so that VR1 is equal to VR2.

[0010] I NPN1 = m×I NPN2 (6)

[0011] V IN / R [[ID=##**##]] ON = m×(IN PN3 +IN PN4 ) (7)

[0012] Preferably, the number of the fourth N-type triodes NPN4 is one-nth of the sum of the numbers of the third N-type triodes NPN3 and the fourth N-type triodes NPN4, so that:

[0013] I NPN4 =(I NPN3 +I [[ID=##**##]] NPN4 ) / n (8)

[0014]

[0015] Preferably, when I PM5 = I PM6 = I [[ID=##**##]] NPN4 ), this current periodically charges the capacitor c1.

[0016] Note: There are some repeated tags in the original text which might be an error. I've translated it as is while keeping those tags as they are. If you have any further clarifications about the text or the tags, please let me know.Preferably, the substrates of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, and the sixth P-type MOS transistor PM6 are connected to the internal power supply VCC.

[0017] Preferably, the substrates of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, and the fifth N-type MOS transistor NM5 are connected to the ground GND.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] A COT constant on-time circuit for high-power power management disclosed by the present invention enables the system to generate a constant frequency of the switching power supply without an oscillator circuit. This frequency is only related to V OUT and can achieve self-control of the switching frequency. By means of the peripheral resistor R ON , it has the advantage of being able to control the magnitude of the switching frequency. By the peripheral resistor R ON and V IN to generate a current I R1 which is a signal of F IN / R ON , the circuit is simple and can be realized without an amplifier. Through the multiple relationship between the first N-type triode NPN1 and the second N-type triode NPN2, and the multiple relationship between the second resistor R2 and the first resistor R1, a current signal that is a multiple of the current I R1 can be accurately mirrored, avoiding the inaccuracy of the current caused by effects such as body bias during current mirroring. By periodically charging the capacitor C1 with the current, a constant on-time T IN related to the power supply voltage V ON is generated, which is inversely proportional to the input voltage. Since the duty cycle D is V OUT / V IN , and T ON is the duty cycle D divided by the switching frequency, this characteristic shows that when V OUT is fixed, the operating frequency is fixed and independent of the load. Therefore, this circuit can generate a constant on-time related to V IN , and the switching frequency is related to V OUT .

[0020] Furthermore, the resistor R ON is much larger than the first resistor R1, making the current I R1 at the port of the first resistor R1 be V IN / R ON , which is beneficial to generating a value only related to V IN and R ONThe relevant current signal can ensure the current accuracy and provide a current signal related only to V IN and R ON .

[0021] Furthermore, the number of the first NPN transistor NPN1 is m times that of the second NPN transistor NPN2, and the resistance value of the second resistor R2 is m times that of the first resistor R1. I NPN1 is m times of I NPN2 , so that VR1 is equal to VR2, which is beneficial to accurately mirror the current signal that is a multiple of the current I R1 , making it convenient to calculate the multiple of the current.

[0022] Furthermore, when I PM5 = I PM6 = I NPN4 , the current periodically charges the capacitor C1, which is beneficial to generating a voltage triangular wave related to the V IN and R ON signals for comparison with a comparator in the subsequent stage to generate a constant on-time signal, and finally generate a frequency signal related to V OUT , without the need for an oscillator circuit. Description of the Drawings

[0023] Figure 1 is the circuit diagram of the constant on-time related to the power supply voltage of the present invention. Detailed Embodiments

[0024] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0026] The present invention will be further described in detail below with reference to the accompanying drawings:

[0027] The present invention provides a constant on-time circuit related to the power supply voltage V implemented through an internal circuit, which is applied to a switching power supply in COT control mode, and is mainly applied to a buck DC / DC converter with a COT control mode architecture, realizing that a single-shot timer generates a constant on-time. The constant on-time T IN is inversely proportional to the input voltage and directly proportional to the output voltage. Therefore, the constant on-time is related to V on , and the switching frequency is related to V IN . OUT

[0028] The described constant on-time circuit related to the power supply voltage for COT control mode includes a constant on-time circuit, which is a single-shot timer, and the on-time is related to V IN .

[0029] Specific implementation form of the constant on-time circuit Figure 1 As shown, the turn-on of the upper switch of the COT control mode switching power supply control system is determined by comparing the divided voltage feedback voltage of the output voltage with the set value of a fixed reference. When the divided voltage feedback voltage of the output voltage is lower than the set value of the fixed reference, the upper switch turns on, and the turn-off of the upper switch is determined by T on generated by the constant on-time circuit.

[0030] The conduction time of the main switch tube is determined by the external resistor R ON and is inversely proportional to the input voltage V IN . The conduction time can be designed by formula (1),

[0031]

[0032] Since,

[0033]

[0034] T on = D × T SW (3)

[0035]

[0036] Therefore, it can be obtained that,

[0037]

[0038] where the external resistor R ON is the resistor for setting the conduction time T ON , V OUT is the system output voltage, V IN ​is the system input voltage, D is the duty cycle, and T on represents the constant on-time, and F SW is the system switching frequency, and F SW is the system switching period. It can be obtained from the above formula that the constant on-time T on is related to V IN , and the switching frequency F SW is related to V OUT .

[0039] The circuit consists of Figure 1 as shown, the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6, the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, the fifth N-type MOS transistor NM5, the first NPN-type transistor NPN1, the second NPN-type transistor NPN2, the third NPN-type transistor NPN3, the fourth NPN-type transistor NPN4, the external resistor R ON , the first resistor R1, the second resistor R2, and the capacitor C1 to generate a triangular wave with a constant on-time, and charge the capacitor C1 periodically. The specific implementation method is as follows: The port of the first resistor R1 is V IN is the voltage division of R ON and the first resistor R1. During design, the resistor R ON is much larger than the first resistor R1. Therefore, the current IR1 at the port of the first resistor R1 can be approximately regarded as V IN / R ON . The number of the first NPN-type transistors NPN1 is m times that of the second NPN-type transistors NPN2, and the resistance value of the second resistor R2 is m times that of the first resistor R1. I NPN1 is m times of I NPN2 . So VR1 is equal to VR2. From the circuit,

[0040] I NPN1 = m×I NPN2 (6)

[0041] V IN / R ON = m×(I NPN3 +I NPN4 ) (7)

[0042] The number of the fourth NPN-type transistors NPN4 is one-nth of the sum of the numbers of the third NPN-type transistors NPN3 and the fourth NPN-type transistors NPN4. Therefore,

[0043] I NPN4 =(I NPN3 +I NPN4) / n (8)

[0044]

[0045] From the circuit, I PM5 = I PM6 = I NPN4 , and this current charges the capacitor C1 periodically.

[0046] The voltage of the capacitor C1 and the fixed voltage VREF are fed into a comparator for comparison to obtain a square-wave signal, i.e., a constant on-time.

[0047] According to the capacitor charge and discharge formula CU = IT, it can be obtained that

[0048] C1 × VREF = I NPN4 × T ON (10)

[0049] It can be obtained that

[0050]

[0051]

[0052] So A = C1 × VREF × m × n, and the constant on-time T on is only related to the external resistor R ON and the power supply voltage V IN , and the switching frequency F sw is only related to the external resistor R ON and the output voltage V OUT .

[0053] See Figure 1 , and the specific connection relationship is as follows:

[0054] The gate of the first P-type MOS transistor PM1 is connected to the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, the gate of the fourth P-type MOS transistor PM4, and is connected to the external bias current IBIAS1. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0055] The gate of the second P-type MOS transistor PM2 is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the third P-type MOS transistor PM3, the gate of the fourth P-type MOS transistor PM4, and is connected to the external bias current IBIAS1. The drain is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0056] The gate of the third P-type MOS transistor PM3 is connected to the gates of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the fourth P-type MOS transistor PM4, and is connected to the external bias current IBIAS1. The drain is connected to the collector of the first N-type triode NPN1 and the gate of the fifth N-type MOS transistor NM5. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0057] The gate of the fourth P-type MOS transistor PM4 is connected to the gates of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, and is connected to the external bias current IBIAS1. The drain is connected to the collector of the second N-type triode NPN2 and the gate of the fourth N-type MOS transistor NM4. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0058] The gate of the fifth P-type MOS transistor PM5 is connected to the drain of the fifth P-type MOS transistor PM5, the gate of the sixth P-type MOS transistor PM6, and the collector of the fourth N-type triode NPN4. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0059] The gate of the sixth P-type MOS transistor PM6 is connected to the gate of the fifth P-type MOS transistor PM5, the drain of the fifth P-type MOS transistor PM5, and the collector of the fourth N-type triode NPN4. The drain is connected to the positive terminal of the capacitor C1 and the negative terminal of the comparator. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC;

[0060] The gate of the first N-type MOS transistor NM1 is connected to the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3, and the drain of the second P-type MOS transistor PM2. The source is connected to the ground GND, and the substrate is connected to the ground GND;

[0061] The gate of the second N-type MOS transistor NM2 is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the third N-type MOS transistor NM3, and the drain of the second P-type MOS transistor PM2. The drain is connected to the source of the fourth N-type MOS transistor NM4, the base of the first N-type triode NPN1, and the base of the second N-type triode NPN2. The source is connected to the ground GND, and the substrate is connected to the ground GND;

[0062] The gate of the third N-type MOS transistor NM3 is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, and the drain of the second P-type MOS transistor PM2. The drain is connected to the source of the fifth N-type MOS transistor NM5, the base of the third N-type triode NPN3, and the base of the fourth N-type triode NPN4. The source is connected to the ground GND, and the substrate is connected to the ground GND;

[0063] The gate of the fourth N-type MOS transistor NM4 is connected to the drain of the fourth P-type MOS transistor PM4 and the collector of the second N-type triode NPN2. The drain is connected to the internal power supply VCC. The source is connected to the base of the first N-type triode NPN1, the base of the second N-type triode NPN2, and the drain of the second N-type MOS transistor NM2. The substrate is connected to the ground GND;

[0064] The gate of the fifth N-type MOS transistor NM5 is connected to the drain of the third P-type MOS transistor PM3 and the collector of the first N-type triode NPN1. The drain is connected to the internal power supply VCC. The source is connected to the base of the third N-type triode NPN3, the base of the fourth N-type triode NPN4, and the drain of the third N-type MOS transistor NM3. The substrate is connected to the ground GND;

[0065] The base of the first N-type triode NPN1 is connected to the source of the fourth N-type MOS transistor NM4, the base of the second N-type triode NPN2, and the drain of the second N-type MOS transistor NM2. The collector is connected to the drain of the third P-type MOS transistor PM3 and the gate of the fifth N-type MOS transistor NM5. The emitter is connected to one end of the resistor RON and one end of the first resistor R1;

[0066] The base of the second N-type triode NPN2 is connected to the source of the fourth N-type MOS transistor NM4, the base of the first N-type triode NPN1, and the drain of the second N-type MOS transistor NM2. The collector is connected to the gate of the fourth N-type MOS transistor NM4 and the drain of the fourth P-type MOS transistor PM4. The emitter is connected to one end of the second resistor R2, the emitter of the third N-type triode NPN3, and the emitter of the fourth N-type triode NPN4;

[0067] The base of the third N-type triode NPN3 is connected to the drain of the third N-type MOS transistor NM3, the source of the fifth N-type MOS transistor NM5, and the base of the fourth N-type triode NPN4. The collector is connected to the internal power supply VCC. The emitter is connected to one end of the second resistor R2, the emitter of the second N-type triode NPN2, and the emitter of the fourth N-type triode NPN4;

[0068] The base of the fourth N-type triode NPN4 is connected to the drain of the third N-type MOS transistor NM3, the source of the fifth N-type MOS transistor NM5, and the base of the third N-type triode NPN3. The collector is connected to the gate of the fifth P-type MOS transistor PM5, the drain of the fifth P-type MOS transistor PM5, and the gate of the sixth P-type MOS transistor PM6. The emitter is connected to one end of the second resistor R2, the emitter of the second N-type triode NPN2, and the emitter of the third N-type triode NPN3;

[0069] One end of the external resistor RON is connected to the external power supply VIN, and the other end of the resistor is connected to the emitter of the first N-type triode NPN1 and one end of the first resistor R1;

[0070] One end of the first resistor R1 is connected to the emitter of the first N-type triode NPN1 and one end of the external resistor RON, and the other end is connected to the ground GND;

[0071] One end of the second resistor R2 is connected to the emitter of the second N-type triode NPN2, the emitter of the third N-type triode NPN3, and the emitter of the fourth N-type triode NPN4, and the other end is connected to the ground GND;

[0072] The positive end of the capacitor C1 is connected to the drain of the sixth P-type MOS transistor PM6 and the negative pole of the comparator, and the negative end of the capacitor C1 is connected to the ground GND;

[0073] The positive input terminal of the comparator is connected to the fixed voltage reference VREF. The negative input terminal of the comparator is connected to the positive end of the capacitor C1 and the drain of the sixth P-type MOS transistor PM6. The output of the comparator is a constant conduction time signal T ON 。

[0074] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A COT (Constant On-Time) circuit for high-power power management, characterized in that, It includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a third P-type MOS transistor PM3, a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, a first N-type triode NPN1, a second N-type triode NPN2, a third N-type triode NPN3, a fourth N-type triode NPN4, and a resistor , a first resistor R1, a second resistor R2, a capacitor and a comparator; The gate of the first P-type MOS transistor PM1 is connected to the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, the gate of the fourth P-type MOS transistor PM4, and is connected to the external bias current IBIAS1. The drain of the second P-type MOS transistor PM2 is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3. The drain of the third P-type MOS transistor PM3 is connected to the collector of the first N-type bipolar transistor NPN1, the gate of the fifth N-type MOS transistor NM5. The drain of the fourth P-type MOS transistor PM4 is connected to the collector of the second N-type bipolar transistor NPN2, the gate of the fourth N-type MOS transistor NM4. The gate of the fifth P-type MOS transistor PM5 is connected to the drain of the fifth P-type MOS transistor PM5, the gate of the sixth P-type MOS transistor PM6, the collector of the fourth N-type bipolar transistor NPN4. The drain of the sixth P-type MOS transistor PM6 is connected to the positive terminal, the negative terminal of the comparator. The drain of the second N-type MOS transistor NM2 is connected to the source of the fourth N-type MOS transistor NM4, the base of the first N-type bipolar transistor NPN1, the base of the second N-type bipolar transistor NPN2. The drain of the third N-type MOS transistor NM3 is connected to the source of the fifth N-type MOS transistor NM5, the base of the third N-type bipolar transistor NPN3, the base of the fourth N-type bipolar transistor NPN4. The drain of the fourth N-type MOS transistor NM4 is connected to the internal power supply VCC. The drain of the fifth N-type MOS transistor NM5 is connected to the internal power supply VCC. The emitter of the first N-type bipolar transistor NPN1 is connected to one end of the resistor and one end of the first resistor R1. The emitter of the second N-type bipolar transistor NPN2 is connected to one end of the second resistor R2, the emitter of the third N-type bipolar transistor NPN3, the emitter of the fourth N-type bipolar transistor NPN4. The collector of the third N-type bipolar transistor NPN3 is connected to the internal power supply VCC. The sources of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, and the sixth P-type MOS transistor PM6 are all connected to the internal power supply VCC. The sources of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, and the third N-type MOS transistor NM3 are all connected to the ground GND.

2. The COT constant on-time circuit for high-power power management according to claim 1, wherein Resistor is much greater than the first resistor R1, so that the current at the port of the first resistor R1 is .

3. The COT constant on-time circuit for high-power power management according to claim 1, wherein The number of the first N-type triodes NPN1 is times that of the second N-type triodes NPN2, and the resistance value of the second resistor R2 is times that of the first resistor R1, which is times of , so that VR1 is equal to VR2.

4. A COT constant on-time circuit for high-power power management according to claim 3, wherein 。 5. A COT constant on-time circuit for high-power power management according to claim 1, characterized in that, The number of the fourth N-type triode NPN4 is one of the sum of the numbers of the third N-type triode NPN3 and the fourth N-type triode NPN4, so that: 。 6. The COT constant on-time circuit for high-power power management according to claim 1, wherein When this current periodically charges the capacitor .

7. The COT constant on-time circuit for high-power power management according to claim 1, characterized in that, the substrates of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, and the sixth P-type MOS transistor PM6 are connected to the internal power supply VCC.

8. The COT constant on-time circuit for high-power power management according to claim 1, characterized in that, the substrates of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, and the fifth N-type MOS transistor NM5 are connected to the ground GND.

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