A COT Constant On-Time Circuit for High-Performance Power Management

Abstract

The present invention discloses a COT (Constant On-Time) circuit for high-performance power management, belonging to the field of switched-mode power supplies. R<subgt;ON< / subgt; is connected to the ground, and a current signal related to V<subgt;IN< / subgt> and R<subgt;ON< / subgt> is set through an internal circuit. By using the mirror signal of the current signal to charge a capacitor, and at the same time, comparing the capacitor signal and a fixed voltage through a single-shot timer and a comparator, a technique for generating a constant on-time related to V<subgt;IN< / subgt> and a switching frequency related to V<subgt;OUT< / subgt> is achieved. This solves the problem of not needing to use an internal oscillator to achieve a constant frequency, and at the same time realizes the self-control of the switching frequency.

Description

Technical Field

[0001] The present invention belongs to the field of switching power supplies, and particularly relates to a COT constant on-time circuit for high-performance power management. Background Art

[0002] In the field of consumer electronics, various electronic devices require power supplies to operate. Switching power management chips are an indispensable part of electronic systems. Among them, switching power supplies with COT control mode have only a comparator in the loop, so the loop response is fast. Due to their excellent load transient response and smooth operation mode switching, they have been well applied in the power supply field.

[0003] The architecture of a DC / DC converter with a COT control mode can use a one-shot timer to generate a constant on-time , during which the internal main switch is turned on, and the on-time is determined by . After the on-time, the main switch must remain off until the divided feedback voltage of the output voltage is lower than the set value of the fixed reference again, and the one-shot timer circuit continues to operate. This one-shot timer generates a constant on-time related to the power supply voltage , which is inversely proportional to the input voltage. Since the duty cycle D is , is the duty cycle D divided by the switching frequency, so this characteristic shows that when is fixed, the operating frequency is fixed and independent of the load.

[0004] Therefore, a circuit for generating a constant on-time for a switching power supply with a constant on-time control mode is needed, which can be related to the constant on-time in a DC / DC converter with a COT control mode architecture, and the switching frequency is related to and . Summary of the Invention

[0005] In order to overcome the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a COT constant on-time circuit for high-performance power management, so as to solve the problem that when is fixed in the prior art one-shot timer, the operating frequency is fixed and independent of the load.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions:

[0007] The present invention discloses a COT constant on-time circuit for high-performance power management, including: an external resistor , the first resistor R1, the second resistor R2, the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, the first PNP transistor PNP1, the second PNP transistor PNP2, the third PNP transistor PNP3, the fourth PNP transistor PNP4, and a capacitor and a comparator;

[0008] The gate of the first N-type MOS transistor NM1 is connected to the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3, the gate of the fourth N-type MOS transistor NM4, and is connected to the external bias current IBIAS1. The drain of the second N-type MOS transistor NM2 is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, and the gate of the third P-type MOS transistor PM3. The drain of the third N-type MOS transistor NM3 is connected to the collector of the first PNP transistor PNP1 and the gate of the fifth P-type MOS transistor PM5. The drain of the fourth N-type MOS transistor NM4 is connected to the collector of the second PNP transistor PNP2 and the gate of the fourth P-type MOS transistor PM4. The drain of the second P-type MOS transistor PM2 is connected to the source of the fourth P-type MOS transistor PM4, the base of the first PNP transistor PNP1, and the base of the second PNP transistor PNP2. The drain of the third P-type MOS transistor PM3 is connected to the source of the fifth P-type MOS transistor PM5, the base of the third PNP transistor PNP3, and the base of the fourth PNP transistor PNP4. The drains of the fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5 are both grounded. The emitter of the first PNP transistor PNP1 is connected to one end of an external resistor and one end of the first resistor R1. The emitter of the second PNP transistor PNP2 is connected to one end of the resistor R2, the emitter of the third PNP transistor PNP3, and the emitter of the fourth PNP transistor PNP4. The collector of the third PNP transistor PNP3 is grounded. The collector of the fourth PNP transistor PNP4 is connected to the positive terminal of the capacitor and the negative input terminal of the comparator. The emitter is connected to one end of the second resistor R2, the emitter of the second PNP transistor PNP2, and the emitter of the third PNP transistor PNP3. The other end of the second resistor R2 is connected to the power supply VIN. The external resistor One end is connected to the ground GND, and the other end is connected to the emitter of the first P-type triode PNP1 and one end of the first resistor R1. The other end of the first resistor R1 is connected to the power supply VIN; the sources of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, and the fourth N-type MOS transistor NM4 are all grounded; the sources of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type MOS transistor PM3 are all connected to the internal power supply VCC, and the capacitor The positive terminal of is connected to the collector of the fourth P-type triode PNP4 and the negative input terminal of the comparator. The negative terminal of the capacitor is connected to the ground GND. The positive input terminal of the comparator is connected to the fixed voltage reference VREF, and the negative input terminal of the comparator is connected to the capacitor The positive terminal and the drain of the sixth P-type MOS transistor PM6 are connected.

[0009] Preferably, the current flowing through the external resistor is much greater than the current flowing through the third N-type MOS transistor NM3, so that the current flowing through the external resistor is .

[0010] Preferably, the number of the first P-type triodes PNP1 is times that of the second P-type triode PNP2, and the resistance value of the second resistor R2 is times that of the first resistor R1, is times of , from the circuit,

[0011] .

[0012] Preferably, the number of the fourth P-type triodes PNP4 is one over the sum of the number of the third P-type triode PNP3 and the fourth P-type triode PNP4, so that

[0013]

[0014] .

[0015] Preferably, the current periodically charges the capacitor .

[0016] Preferably, the voltage of the capacitor is compared with the fixed voltage VREF in the comparator to obtain a square wave signal, that is, a constant on-time , according to the capacitor charge and discharge formula, it can be obtained that

[0017]

[0018] It can be obtained that

[0019]

[0020] Therefore , the constant on - time is only related to the external resistor and the power supply voltage The switching frequency is only related to the external resistor and the output voltage related.

[0021] Preferably, the substrates of the first N - type MOS transistor NM1, the second N - type MOS transistor NM2, the third N - type MOS transistor NM3, and the fourth N - type MOS transistor NM4 are all connected to the ground GND.

[0022] Preferably, the substrates of the first P - type MOS transistor PM1, the second P - type MOS transistor PM2, the third P - type MOS transistor PM3, the fourth P - type MOS transistor PM4, and the fifth P - type MOS transistor PM5 are all connected to the internal power supply VCC.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] A COT (Constant On - Time) constant - on - time circuit for high - performance power management disclosed by the present invention can generate a constant frequency related to without the need for an oscillator circuit, and can achieve self - control of the switching frequency. Through the peripheral resistor , it has the advantage of being able to control the magnitude of the switching frequency. Through the peripheral resistor and generate a current for signal, the circuit is simple and can be achieved without an amplifier. Through the multiple relationship between PNP1 and PNP2, and the multiple relationship between R2 and R1, a current signal that is a multiple of the current can be accurately mirrored, and the inaccuracy of the current caused by body - bias and other effects during current mirroring can be avoided. Through the current charge the capacitor periodically to generate a constant on - time related to the power supply voltage , which is inversely proportional to the input voltage. Since the duty cycle D is , is the duty cycle D divided by the switching frequency, so this characteristic shows that when is fixed, the operating frequency is fixed and independent of the load. Therefore, this circuit can generate a constant on - time related to , and the switching frequency is related to is related to

[0025] Furthermore, the resistance is much larger than R1, making the current at the R1 port be , which is beneficial to generate a current signal related only to and , and can ensure the accuracy of the current. At the same time, it provides a current signal related only to and .

[0026] Furthermore, the number of PNP1 is times that of PNP2, and the resistance value of R2 is times that of R1 being times of makes VR1 equal to VR2, which is beneficial to accurately mirror a current signal that is a multiple of the current , making it convenient to calculate the multiple of the current.

[0027] Furthermore, when , the current periodically charges the capacitor, which is beneficial to generate a voltage triangular wave related to and signals for comparison with a comparator at the subsequent stage to generate a constant conduction time signal, and finally generate a frequency signal related to , without the need for an oscillator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a circuit diagram of a constant conduction time set by an external resistor according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the description, claims and the above drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0031] The present invention will be further described in detail below with reference to the drawings:

[0032] The present invention discloses a constant on-time circuit related to the power supply voltage implemented through an internal circuit, which is applied to a switching power supply in COT control mode, and realizes a single-shot timer to generate a constant on-time. The on-time is inversely proportional to the input voltage and directly proportional to the output voltage. Therefore, the constant on-time is related to and the switching frequency is related to

[0033] The described constant on-time circuit related to the power supply voltage for COT control mode includes a constant on-time circuit, which is a single-shot timer, and the on-time is related to

[0034] The specific implementation form of the constant on-time circuit Figure 1 is shown as follows. The turn-on of the upper transistor in the COT control mode switching power supply control system is determined by comparing the divided voltage feedback voltage of the output voltage with the set value of the fixed reference. When the divided voltage feedback voltage of the output voltage is lower than the set value of the fixed reference, the upper transistor turns on, and the turn-off of the upper transistor is determined by the generated by the constant on-time circuit.

[0035] The conduction time of the main switch transistor is determined by the external resistor and is inversely proportional to the input voltage . The conduction time can be designed by formula (1),

[0036]

[0037] Since,

[0038]

[0039] Therefore, it can be obtained that, ​​​

[0040]

[0041] Among them, the external resistor is the resistor for setting the conduction time , is the system output voltage, is the system input voltage, D is the duty cycle, represents the constant conduction time, is the system switching frequency, is the system switching period. It can be obtained from the above formula that the constant conduction time is related to , and the switching frequency is related to .

[0042] The circuit consists of Figure 1 as shown. The external resistor , the first resistor R1, the second resistor R2, the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, the first PNP transistor PNP1, the second PNP transistor PNP2, the third PNP transistor PNP3, the fourth PNP transistor PNP4, and the capacitor constitute a triangular wave for generating a constant conduction time, and periodically charge the capacitor . The specific implementation method is as follows: The current flowing through the port of the first resistor R1 is equal to the sum of the current flowing through the external resistor and the current flowing through the first PNP transistor PNP1 and the third N-type MOS transistor NM3. Since the current flowing through the external resistor is much larger than the current flowing through the third N-type MOS transistor NM3, the current flowing through the external resistor is approximately . The number of the first PNP transistor PNP1 is times that of the second PNP transistor PNP2, and the resistance value of the second resistor R2 is times that of the first resistor R1. is times of . From the circuit,

[0043]

[0044] The number of the fourth PNP transistor PNP4 is one - fraction of the sum of the number of the third PNP transistor PNP3 and the fourth PNP transistor PNP4. Therefore, it can be obtained that

[0045]

[0046]

[0047] From the circuit, the current charges the capacitor periodically.

[0048] The voltage of the capacitor and the fixed voltage VREF are fed into a comparator for comparison to obtain a square wave signal, i.e., a constant on-time.

[0049] According to the capacitor charge and discharge formula, it can be obtained that

[0050]

[0051] it can be obtained that

[0052]

[0053] Therefore , the constant on-time is only related to the external resistor and the power supply voltage . The switching frequency is only related to the external resistor and the output voltage .

[0054] The specific connection relationship is as follows:

[0055] The gate of the first N-type MOS transistor NM1 is connected to the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3, the gate of the fourth N-type MOS transistor NM4, and is connected to the external bias current IBIAS1. The source is connected to the ground GND, and the substrate is connected to the ground GND;

[0056] The gate of the second N-type MOS transistor NM2 is connected to the gate of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the third N-type MOS transistor NM3, the gate of the fourth N-type MOS transistor NM4, and is connected to the external bias current IBIAS1. The drain is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3. The source is connected to the ground GND, and the substrate is connected to the ground GND;

[0057] The gate of the third N-type MOS transistor NM3 is connected to the gates of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the fourth N-type MOS transistor NM4, and is connected to the external bias current IBIAS1. The drain is connected to the collector of the first PNP transistor PNP1 and the gate of the fifth P-type MOS transistor PM5. The source is connected to the ground GND, and the substrate is connected to the ground GND.

[0058] The gate of the fourth N-type MOS transistor NM4 is connected to the gates of the first N-type MOS transistor NM1, the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3, and is connected to the external bias current IBIAS1. The drain is connected to the collector of the second PNP transistor PNP2 and the gate of the fourth P-type MOS transistor PM4. The source is connected to the ground GND, and the substrate is connected to the ground GND.

[0059] The gate of the first P-type MOS transistor PM1 is connected to the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, and the drain of the second N-type MOS transistor NM2. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC.

[0060] The gate of the second P-type MOS transistor PM2 is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the third P-type MOS transistor PM3, and the drain of the second N-type MOS transistor NM2. The drain is connected to the source of the fourth P-type MOS transistor PM4, the base of the first PNP transistor PNP1, and the base of the second PNP transistor PNP2. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC.

[0061] The gate of the third P-type MOS transistor PM3 is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, and the drain of the second N-type MOS transistor NM2. The drain is connected to the source of the fifth P-type MOS transistor PM5, the base of the third PNP transistor PNP3, and the base of the fourth PNP transistor PNP4. The source is connected to the internal power supply VCC, and the substrate is connected to the internal power supply VCC.

[0062] The gate of the fourth P-type MOS transistor PM4 is connected to the drain of the fourth N-type MOS transistor NM4 and the collector of the second PNP transistor PNP2. The drain is connected to the ground GND. The source is connected to the base of the first PNP transistor PNP1, the base of the second PNP transistor PNP2, and the drain of the second P-type MOS transistor PM2. The substrate is connected to the internal power supply VCC.

[0063] The gate of the fifth P-type MOS transistor PM5 is connected to the drain of the third N-type MOS transistor NM3 and the collector of the first PNP transistor PNP1. The drain is connected to the ground GND, and the source is connected to the bases of the third PNP transistor PNP3, the fourth PNP transistor PNP4, and the drain of the third P-type MOS transistor PM3. The substrate is connected to the internal power supply VCC;

[0064] The base of the first PNP transistor PNP1 is connected to the source of the fourth P-type MOS transistor PM4, the base of the second PNP transistor PNP2, and the drain of the second P-type MOS transistor PM2. The collector is connected to the drain of the third N-type MOS transistor NM3 and the gate of the fifth P-type MOS transistor PM5. The emitter is connected to one end of the external resistor RON and one end of the resistor R1;

[0065] The base of the second PNP transistor PNP2 is connected to the source of the fourth P-type MOS transistor PM4, the base of the first PNP transistor PNP1, and the drain of the second P-type MOS transistor PM2. The collector is connected to the gate of the fourth P-type MOS transistor PM4 and the drain of the fourth N-type MOS transistor NM4. The emitter is connected to one end of the resistor R2, the emitter of the third PNP transistor PNP3, and the emitter of the fourth PNP transistor PNP4;

[0066] The base of the third PNP transistor PNP3 is connected to the drain of the third P-type MOS transistor PM3, the base of the fourth PNP transistor PNP4, and the source of the fifth P-type MOS transistor PM5. The collector is connected to the ground GND. The emitter is connected to one end of the resistor R2, the emitter of the second PNP transistor PNP2, and the emitter of the fourth PNP transistor PNP4;

[0067] The base of the fourth PNP transistor PNP4 is connected to the drain of the third P-type MOS transistor PM3, the source of the fifth P-type MOS transistor PM5, and the base of the third PNP transistor PNP3. The collector is connected to the positive end of the capacitor and the negative input terminal of the comparator. The emitter is connected to one end of the resistor R2, the emitter of the second PNP transistor PNP2, and the emitter of the third PNP transistor PNP3;

[0068] The external resistor One end is connected to the ground GND, and the other end is connected to the emitter of the first PNP transistor PNP1 and one end of the resistor R1;

[0069] One end of the resistor R1 is connected to the emitter of the first PNP transistor PNP1 and one end of the external resistor The other end is connected to the power supply Connected;

[0070] One end of the resistor R2 is connected to the emitters of the second PNP transistor PNP2, the third PNP transistor PNP3, and the fourth PNP transistor PNP4, and the other end is connected to the power supply connected;

[0071] Capacitor The positive terminal of is connected to the collector of the fourth PNP transistor PNP4 and the negative input of the comparator, and the negative terminal of the capacitor is connected to the ground GND;

[0072] The positive input of the comparator is connected to the fixed voltage reference VREF, and the negative input of the comparator is connected to the positive terminal of the capacitor and the drain of the sixth PMOS transistor PM6. The output of the comparator is a constant on-time signal .

[0073] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A COT (Constant On-Time) circuit for high-performance power management, characterized in that, Including: External resistor , a first resistor R1, a second resistor R2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a third P-type MOS transistor PM3, a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a first PNP transistor PNP1, a second PNP transistor PNP2, a third PNP transistor PNP3, a fourth PNP transistor PNP4, a capacitor and a comparator; The gate of the first N-type MOS transistor NM1 is connected to the drain of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, the gate of the third N-type MOS transistor NM3, the gate of the fourth N-type MOS transistor NM4, and is connected to the external bias current IBIAS1. The drain of the second N-type MOS transistor NM2 is connected to the gate of the first P-type MOS transistor PM1, the drain of the first P-type MOS transistor PM1, the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3. The drain of the third N-type MOS transistor NM3 is connected to the collector of the first PNP transistor PNP1, the gate of the fifth P-type MOS transistor PM5. The drain of the fourth N-type MOS transistor NM4 is connected to the collector of the second PNP transistor PNP2, the gate of the fourth P-type MOS transistor PM4. The drain of the second P-type MOS transistor PM2 is connected to the source of the fourth P-type MOS transistor PM4, the base of the first PNP transistor PNP1, the base of the second PNP transistor PNP2. The drain of the third P-type MOS transistor PM3 is connected to the source of the fifth P-type MOS transistor PM5, the base of the third PNP transistor PNP3, the base of the fourth PNP transistor PNP4. The drains of the fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5 are both grounded. The emitter of the first PNP transistor PNP1 is connected to one end of the external resistor and one end of the first resistor R1. The emitter of the second PNP transistor PNP2 is connected to one end of the resistor R2, the emitter of the third PNP transistor PNP3, the emitter of the fourth PNP transistor PNP4. The collector of the third PNP transistor PNP3 is grounded. The collector of the fourth PNP transistor PNP4 is connected to the positive end of the capacitor and the negative input terminal of the comparator. The emitter of the fourth PNP transistor PNP4 is connected to one end of the second resistor R2, the emitter of the second PNP transistor PNP2, the emitter of the third PNP transistor PNP3. The other end of the second resistor R2 is connected to the power supply VIN. One end of the external resistor is connected to the ground GND. One end of the external resistor is connected to the emitter of the first PNP transistor PNP1 and one end of the first resistor R1. The other end of the first resistor R1 is connected to the power supply VIN. The sources of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, and the fourth N-type MOS transistor NM4 are all grounded. The sources of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type MOS transistor PM3 are all connected to the internal power supply VCC. The positive end of the capacitor is connected to the collector of the fourth PNP transistor PNP4 and the negative input terminal of the comparator. The negative end of the capacitor is connected to the ground GND. The positive input terminal of the comparator is connected to the fixed voltage reference VREF. The negative input terminal of the comparator is connected to the capacitor is connected to the positive terminal and the collector of the fourth PNP transistor PNP4.

2. The COT constant on-time circuit for high-performance power management according to claim 1, wherein The current flowing through the external resistor is much larger than the current flowing through the third N-type MOS transistor NM3, such that the current flowing through the external resistor is .

3. The COT constant on-time circuit for high-performance power management according to claim 1, characterized in that, The number of the first P-type triodes PNP1 is times that of the second P-type triodes PNP2, and the resistance value of the second resistor R2 is times that of the first resistor R1. For times of , according to the circuit, 。 4. A COT constant on-time circuit for high-performance power management according to claim 1, characterized in that, The number of the fourth PNP transistor PNP4 is one of the sum of the number of the third PNP transistor PNP3 and the number of the fourth PNP transistor PNP4, such that one, such that 。 5. The COT constant on-time circuit for high-performance power management according to claim 4, wherein Current periodically charges a capacitor.

6. The COT constant on-time circuit for high-performance power management according to claim 1, wherein Capacitance The voltage of the capacitance is compared with the fixed voltage VREF in a comparator to obtain a square wave signal, i.e., a constant on-time According to the capacitance charging and discharging formula, it can be obtained that It can be obtained that Therefore , the constant on-time is only related to the external resistor and the supply voltage . The switching frequency is only related to the external resistor and the output voltage .

7. The COT constant on-time circuit for high-performance power management according to claim 1, wherein The substrates of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, and the fourth N-type MOS transistor NM4 are all connected to the ground GND.

8. A COT constant on-time circuit for high-performance power management according to claim 1, characterized in that, The substrates of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, and the fifth P-type MOS transistor PM5 are all connected to the internal power supply VCC.

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