Centralized control type interleaved parallel circuit and current sharing method thereof and readable storage medium

Abstract

The present application relates to a current sharing method for a centralized control interleaved parallel circuit, comprising setting a duty cycle of a first parallel circuit in the interleaved parallel circuit as a first duty cycle, setting a duty cycle of a second parallel circuit in the interleaved parallel circuit as a second duty cycle; setting a second duty cycle compensation quantity for ensuring that currents of the two parallel circuits are equal at the end of one switching cycle based on a ratio between a bus voltage value of the interleaved parallel circuit and a voltage difference between a first duty cycle, an input voltage sampled at a zero-crossing point of a triangular carrier of the first parallel circuit and an input voltage sampled at a period value. The present application also relates to a computer readable storage medium and a centralized control interleaved parallel circuit. The present application can solve the problem of uneven current among circuits in a low-cost and easy-to-implement manner, and improve the sinusoidal degree of the second parallel circuit.

Description

Technical Field

[0001] This invention relates to the field of interleaved parallel circuits, and more specifically, to a current sharing method for a centrally controlled interleaved parallel circuit, a computer-readable storage medium, and a centrally controlled interleaved parallel circuit. Background Technology

[0002] Compared to low-power circuits, high-power circuits have correspondingly larger EMI circuits and energy storage filter parameters, and also place relatively greater demands on the current stress of the switching transistors. To achieve miniaturization and weight reduction, interleaved parallel technology is introduced. Interleaved parallel connection can reduce inductor current ripple and switching transistor current stress, and can also reduce circuit parameters and increase power density. Interleaved parallel control can be implemented through centralized or decentralized control methods. Decentralized control can improve system reliability, but it is relatively complex and costly; therefore, centralized control is usually used in existing technologies. However, centralized interleaved parallel circuits suffer from uneven current distribution among multiple circuits. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a current sharing method, a computer-readable storage medium, and a centralized control interleaved parallel circuit, which can solve the problem of uneven current between circuits in a low-cost and easy-to-implement manner, in view of the above-mentioned defects of the prior art.

[0004] The technical solution adopted by this invention to solve its technical problem is: a current sharing method for a centralized control interleaved parallel circuit, comprising:

[0005] S1. Set the duty cycle of the first parallel circuit in the interleaved parallel circuit to the first duty cycle, and set the duty cycle of the second parallel circuit in the interleaved parallel circuit to the second duty cycle.

[0006] S2. The ratio between the voltage difference between the input voltage sampled at the zero-crossing point of the triangular carrier wave of the first parallel circuit and the input voltage sampled at the periodic value, based on the first duty cycle, and the bus voltage value of the interleaved parallel circuit, is set as a second duty cycle compensation amount to ensure that the currents of the two parallel circuits are equal at the end of a switching cycle.

[0007] The current sharing method for the centralized control interleaved parallel circuit described in this invention further includes:

[0008] S3. Calculate the real-time current of the second parallel circuit in the interleaved parallel circuit based on the real-time current of the first parallel circuit, the compensation amount of the first duty cycle and the second duty cycle, and perform closed-loop control on the second parallel circuit based on the real-time current of the second parallel circuit.

[0009] In the current sharing method of the centralized control interleaved parallel circuit described in this invention, in step S2, ,in This indicates the second duty cycle. This indicates the first duty cycle. This indicates the compensation amount for the second duty cycle. This represents the bus voltage value of the interleaved parallel circuit. This indicates the switching period of the interleaved parallel circuit.

[0010] In the centralized control type interleaved parallel circuit current sharing method of the present invention, the first parallel circuit and the second parallel circuit are the same circuit. In step S3, the current sharing of the second parallel circuit in the first step is calculated based on the following formula. n Midpoint current during the rising phase of each switching cycle:

[0011]

[0012] in, This represents the midpoint current during the rising phase of the second parallel circuit. This represents the midpoint current during the rising phase of the first parallel circuit. This represents the inductance value of the first parallel circuit or the second parallel circuit. This represents the number of periods and takes a positive integer value. This represents the input voltage of the interleaved parallel circuit. Indicates the input voltage at Time and ( ) The difference in time.

[0013] In the centralized control type interleaved parallel circuit current sharing method of the present invention, in step S3, the current sharing of the second parallel circuit in the first step is calculated based on the following formula. n Midpoint current during the descent phase within a switching cycle:

[0014]

[0015] in, This represents the midpoint current during the falling phase of the second parallel circuit. This represents the midpoint current during the falling phase of the first parallel circuit.

[0016] In the current sharing method of the centralized control type interleaved parallel circuit described in this invention, the real-time current of the first parallel circuit and the real-time current of the second parallel circuit are equal at the beginning of any switching cycle and at the end of any switching cycle, but are not equal at the end of energy storage. hour, The current ripple of the second parallel circuit is greater than that of the first parallel circuit. hour, The current ripple of the second parallel circuit is smaller than that of the first parallel circuit.

[0017] In the current sharing method of the centralized control interleaved parallel circuit described in this invention, the interleaved parallel circuit includes a PFC interleaved parallel circuit and an INV interleaved parallel circuit.

[0018] In the current sharing method for a centralized control interleaved parallel circuit described in this invention, the interleaved parallel circuit comprises N parallel circuits, where N is a positive integer greater than or equal to 2. Another technical solution adopted by this invention to solve its technical problem is to construct a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the current sharing method for the centralized control interleaved parallel circuit.

[0019] Another technical solution adopted by the present invention to solve its technical problem is to construct a centralized control interleaved parallel circuit, including at least a first parallel circuit and a second parallel circuit and a controller. The controller stores a computer program, and when the computer program is executed by the controller, it implements the current sharing method according to the centralized control interleaved parallel circuit.

[0020] The current sharing method, computer-readable storage medium, and centralized control interleaved parallel circuit of this invention, by compensating the duty cycle of the second parallel circuit according to the change in input voltage, can solve the problem of uneven current distribution between circuits in a low-cost and easily implementable manner, and improve the sinusoidal nature of the second parallel circuit. Furthermore, the real-time current of the second parallel circuit can be calculated based on the real-time current of the first parallel circuit, the first duty cycle, and the aforementioned change in input voltage, allowing it to participate in the closed-loop control of the second parallel circuit. Compared to the traditional centralized control interleaved parallel circuit, the second parallel circuit now possesses a current loop, meaning that the current of the second parallel circuit can be controlled in real time without sampling the second parallel circuit current, improving the dynamic response of the second parallel circuit to the input current. Additionally, by compensating the duty cycle of the second parallel circuit, the dynamic response of the second parallel circuit to the input voltage can be improved. Attached Figure Description

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0022] Figure 1 This is a flowchart of the first embodiment of the current sharing method for a centralized control interleaved parallel circuit according to a preferred embodiment of the present invention;

[0023] Figure 2 This is a flowchart of a second embodiment of the current sharing method for a centralized control interleaved parallel circuit according to a preferred embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of a centralized control type interleaved parallel circuit and its control signal, which uses the same duty cycle control.

[0025] Figure 4 It uses the same duty cycle control. Figure 3 The diagram shows the sampling and signal transmission of a centralized control interleaved parallel circuit.

[0026] Figure 5 Is adopted Figure 1 The diagram shows the current sharing method for a centralized control interleaved parallel circuit, used to control the sampling and signal generation of the circuit.

[0027] Figure 6 Is adopted Figure 2 The diagram shows the control signal of the centralized control interleaved parallel circuit, which is controlled by the current sharing method of the centralized control interleaved parallel circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] This invention relates to a current sharing method for a centrally controlled interleaved parallel circuit. The method includes setting the duty cycle of a first parallel circuit in the interleaved parallel circuit to a first duty cycle and setting the duty cycle of a second parallel circuit in the interleaved parallel circuit to a second duty cycle. The method derives a compensation amount for the second duty cycle that ensures equal current in the two parallel circuits at the end of a switching cycle. This compensation amount is expressed as the ratio between the voltage difference between the input voltage sampled at the zero-crossing point of the triangular carrier wave in the first parallel circuit and the input voltage sampled at the periodic value, and the bus voltage value of the interleaved parallel circuit. By compensating the duty cycle of the second parallel circuit based on changes in the input voltage, this invention can solve the problem of uneven current distribution between circuits in a low-cost and easily implemented manner, and also improve the sinusoidal characteristic of the second parallel circuit.

[0030] Figure 1 This is a flowchart of the first embodiment of the current sharing method for a centralized control interleaved parallel circuit, which is a preferred embodiment of the present invention. Figure 1 As shown, in step S1, the duty cycle of the first parallel circuit in the interleaved parallel circuit is set to the first duty cycle, and the duty cycle of the second parallel circuit in the interleaved parallel circuit is set to the second duty cycle. In a preferred embodiment of the present invention, the interleaved parallel circuit may include a PFC interleaved parallel circuit and an INV interleaved parallel circuit, and may include N parallel circuits, where N is a positive integer greater than or equal to 2. For example, a circuit such as... Figure 3The diagram shows a centralized control two-way PFC interleaved parallel circuit. Of course, in other preferred embodiments of the invention, other types of interleaved parallel circuits can be selected, and these circuits may include, for example, three or more parallel circuits. In a preferred embodiment of the invention, it is assumed that the inductance values ​​of the centralized control two-way PFC interleaved parallel circuit are equal, and the influence of the bus on the duty cycle is not considered; the bus voltage value is assumed to be... Switching cycle of the interleaved parallel circuit The value inside is constant. The duty cycle of the first parallel circuit in the interleaved parallel circuit is set to the first duty cycle. The duty cycle of the second parallel circuit in the interleaved parallel circuit is set to the second duty cycle. .

[0031] In step S2, the ratio between the voltage difference between the input voltage sampled at the zero-crossing point of the triangular carrier wave of the first parallel circuit and the input voltage sampled at the periodic value, based on the first duty cycle, and the bus voltage value of the interleaved parallel circuit, is set as a second duty cycle compensation amount to ensure that the currents of the two parallel circuits are equal at the end of a switching cycle. Preferably, in this invention, it is assumed that in the first... n At the beginning of the cycle, the inductor currents of the two PFC interleaved parallel circuits are equal, and the control objective is to [achieve the desired result in the first cycle]. n At the end of each cycle, the inductor currents of the two PFC interleaved parallel circuits are equal, and the compensation amount for the second duty cycle can be obtained as follows: It should meet ,in This indicates the second duty cycle. This indicates the first duty cycle. This represents the bus voltage value of the interleaved parallel circuit. This indicates the switching period of the interleaved parallel circuit.

[0032] Thus, for a centrally controlled interleaved parallel circuit, this invention can solve the problem of uneven current between circuits in a low-cost and easy-to-implement manner by compensating the duty cycle of the second parallel circuit according to the change in input voltage, and improve the sinusoidal nature of the second parallel circuit.

[0033] Figure 2 This is a flowchart of a second embodiment of the current sharing method for a centralized control interleaved parallel circuit, which is a preferred embodiment of the present invention. Figure 2As shown, in step S1, the duty cycle of the first parallel circuit in the interleaved parallel circuit is set as the first duty cycle, and the duty cycle of the second parallel circuit in the interleaved parallel circuit is set as the second duty cycle. In step S2, based on the first duty cycle, the ratio between the voltage difference between the zero-crossing sampling input voltage and the periodic value sampling input voltage of the first parallel circuit and the bus voltage value of the interleaved parallel circuit is set as a second duty cycle compensation circuit to ensure that the currents of the two parallel circuits are equal at the end of a switching cycle. In this embodiment, the above two steps can be referred to... Figure 1 The embodiments shown will not be described again here.

[0034] Further as Figure 2 As shown, this preferred embodiment further includes step S3, namely, optimization of the control loop. In step S3, the real-time current of the second parallel circuit in the interleaved parallel circuit is calculated based on the real-time current of the first parallel circuit, the first duty cycle, and the compensation amount of the second duty cycle, and closed-loop control of the second parallel circuit is performed based on the real-time current of the second parallel circuit. Preferably, the second parallel circuit can be calculated based on the following formula in the first... n Midpoint current during the rising phase of each switching cycle:

[0035]

[0036] in, This represents the midpoint current during the rising phase of the second parallel circuit. This represents the midpoint current during the rising phase of the first parallel circuit. This represents the inductance value of the first parallel circuit or the second parallel circuit. This represents the number of periods and takes a positive integer value. This represents the input voltage of the interleaved parallel circuit. Indicates the input voltage at Time and ( ) The difference in time.

[0037] The second parallel circuit is calculated based on the following formula in the [missing information]. n Midpoint current during the descent phase within a switching cycle:

[0038]

[0039] in, This represents the midpoint current during the falling phase of the second parallel circuit. This represents the midpoint current during the falling phase of the first parallel circuit.

[0040] In this preferred embodiment, the real-time current of the first parallel circuit and the real-time current of the second parallel circuit are equal at the beginning of any switching cycle and at the end of any switching cycle, but they are not equal at the end of energy storage, that is, the current ripples of the two circuits are different. hour, The current ripple of the second parallel circuit is greater than that of the first parallel circuit. hour, The current ripple of the second parallel circuit is smaller than that of the first parallel circuit. In fact, the difference between the two ripples is very small, and the two currents can be considered to be equal in real time.

[0041] In this preferred embodiment, the real-time current of the first parallel circuit, the first duty cycle, and the aforementioned voltage can be used to... Time and ( ) The change in the current at any given time is used to calculate the real-time current of the second parallel circuit, allowing it to participate in the closed-loop control of the second parallel circuit. Compared to the traditional centralized control type interleaved parallel circuit, the second parallel circuit has a current loop, which means that the current of the second parallel circuit can be controlled in real time without sampling the current of the second parallel circuit, thereby improving the dynamic response of the second parallel circuit to the input current.

[0042] To better illustrate the principles of this invention, the following will use... Figure 3 The centralized control interleaved parallel circuit shown below provides a further detailed description of a preferred embodiment of the present invention. Furthermore, to better illustrate the effects of the present invention, [the following is a more detailed description of the circuit]. Figure 3 The principle and problems of the centralized control interleaved parallel circuit shown are further explained when using the same duty cycle control.

[0043] against Figure 3 The centralized control interleaved parallel circuit shown, if using the same duty cycle control, its sampling and control signals are as follows: Figure 4 As shown. If the duty cycle of the first parallel circuit in the interleaved parallel circuit is... Duty cycle of the second parallel circuit They are equal, both equal to the duty cycle of the Boost circuit. If , Compare Lag of 180°. The inductance of the first parallel circuit is negligible here. The inductance value of the second parallel circuit The difference between them, namely Ignoring the influence of the bus on the duty cycle, the bus voltage is assumed to be within the switching cycle of the centralized control interleaved parallel circuit. It is a constant value over the time scale And assume the first n At the start of each switching cycle, the currents in the two inductors of the first and second parallel circuits are equal. Assume the switching frequency of the PFC is... The inductor current of the first parallel circuit sampling frequency From the KVL equations, we can obtain:

[0044] No. n Within a cycle, the current difference between the two paths corresponding to the moment when the switching transistor transitions from on to off state.

[0045]

[0046] No. n At the end of each cycle, the current difference between the two paths

[0047]

[0048] Input voltage Within the range of 0 to 90°, , Furthermore, the current error accumulates with each switching cycle, and the difference between the two at 90° is [value missing]. Within the input voltage range of 90° to 180°, , The same logic applies to the negative half-cycle, so compared to the inductor current of the first parallel circuit... In other words, the inductor current of the second parallel circuit The sinusoidal property is not good. Therefore, for the interleaved parallel PFC circuit with centralized control, if the duty cycles of the two circuits are made equal, there are two problems: first, the current is not evenly distributed between the two circuits; second, the current sinusoidal property of the second parallel circuit is not good.

[0049] To address this, we employ the method of this invention to adjust the duty cycle of the first parallel circuit in the interleaved parallel circuit. Duty cycle of the second parallel circuit Set them to be different, that is Its sampling and control signals are as follows Figure 5 As shown. The inductance of the first parallel circuit is ignored here. The inductance value of the second parallel circuit The difference between them, namely Ignoring the influence of the bus on the duty cycle, the bus voltage is assumed to be within the switching cycle of the centralized control interleaved parallel circuit. It is a constant value over the time scale And assume the first n At the start of each switching cycle, the currents in the two inductors of the first and second parallel circuits are equal, that is... The goal is that at the end of a cycle, the currents of the two inductors in the first and second parallel circuits are equal. Then, according to the KVL formula, ...

[0050]

[0051]

[0052] have to

[0053]

[0054] Therefore, for the wave generation stage alone, the first parallel circuit uses the duty cycle of the Boost circuit itself. The duty cycle of the second parallel circuit is... Subtract one variable from the base, namely the duty cycle compensation amount. This ensures that the currents of the two circuits are equal at the end of a switching cycle.

[0055] about The acquisition can be implemented in the EPWM configuration of a digital signal processor (DSP). If the switching frequency of the interleaved parallel circuit is... , The sampling frequency is Only the midpoint current during the current rise phase is collected; The sampling frequency is For the control system, the first n The input voltage used to calculate the first duty cycle of the first parallel circuit within a switching cycle is the first... n The midpoint voltage collected this time However, the input voltage used to calculate the second duty cycle of the second parallel circuit is higher than that of the second parallel circuit. Voltage value lagging by 180° . The data is acquired by triggering the AD converter at the zero-crossing point (ZERO) of the triangular carrier wave in the first parallel circuit. If the AD converter is triggered at the triangular carrier wave period value (PRD), the sampled value at that point is... The voltage difference can be obtained by calculating the difference between the periodic sampled voltage value and the zero-crossing sampled voltage value. By calculating this voltage difference... and bus voltage value The ratio can be used to obtain the compensation amount for the second duty cycle. .

[0056] Thus, this invention, by dynamically compensating the duty cycle of the second parallel circuit based on the change in input voltage within 0.5 switching cycles for a multi-channel interleaved parallel circuit using centralized control, has the following advantages: 1) Low cost, saving costs compared to distributed control. n -1 Hall or CT, conditioning and AD resources; 2) Compared with centralized control with the same duty cycle, the current sharing effect is better, and the inductor current sinusoidality of the second parallel circuit is better.

[0057] Furthermore, the next step is to further combine... Figure 6 This section describes the optimization of the control loop portion of a further preferred embodiment of the present invention. Substituting equation (5) into equation (3) yields:

[0058]

[0059] The midpoint current during the rising phase of the second parallel circuit can be calculated using the following formula:

[0060]

[0061] The midpoint current of the falling phase of the second parallel circuit can be calculated based on the following formula:

[0062]

[0063] From equations (7) and (8), the midpoint currents of the second parallel circuit during the rising and falling phases in each switching cycle can be obtained. Furthermore, the current loop can be equivalent to the inductor voltage in the duty cycle formula. The inductor current of the second parallel circuit Compared to the inductor current of the first parallel circuit Coefficient in the increment at the midpoint , can be with In Since the inductor current of the first parallel circuit is canceled out, no complex calculations are needed. Therefore, without needing to collect the inductor current of the second parallel circuit, the real-time current of the second parallel circuit can be obtained through a simple method, enabling current closed-loop control. In this embodiment, the inductor current of the first parallel circuit is required. and input voltage The sampling frequency is The control frequency is .

[0064] Furthermore, if the second circuit duty cycle compensation method shown in formula (5) is adopted, the inductor current of the second parallel circuit will be... The inductor current of the first parallel circuit The current ripple is the same at the beginning and end of a cycle, but different at the end of the energy storage cycle, meaning the current ripple is different in the two paths. hour, The current ripple of the second parallel circuit is larger than that of the first parallel circuit. hour, The current ripple in the second parallel circuit is smaller than that in the first parallel circuit. In fact, The value is small, approximately 0.1% of the rated current, and its impact is minimal. Therefore, ignoring the slight difference in ripple between the two paths, the two currents can be considered equal in real time. Thus, the actual current of the second parallel circuit can be reconstructed using formula (7-8) and used in the closed-loop control of the second parallel circuit. Compared to traditional centralized control interleaved parallel circuits, the second parallel circuit now possesses a current loop, meaning that the current of the second parallel circuit is controlled in real time without sampling it, improving the dynamic response of the second parallel circuit to the input current. Furthermore, by compensating for the duty cycle of the second parallel circuit, its dynamic response to the input voltage can be improved. In summary, compared to centralized control with the same duty cycle, the advantages of the current sharing method proposed in this invention are that the second parallel circuit can respond promptly to changes in input voltage and current, exhibits good dynamic characteristics, and is easily implemented in a DSP.

[0065] The current sharing method for the centralized control interleaved parallel circuit of this invention compensates for the duty cycle of the second parallel circuit based on the change in input voltage over 0.5 switching cycles. This solves the problem of uneven current distribution between circuits in a low-cost and easily implementable manner, and improves the sinusoidal characteristic of the second parallel circuit. Furthermore, the real-time current of the second parallel circuit can be calculated based on the real-time current of the first parallel circuit, the first duty cycle, and the aforementioned change in input voltage over 0.5 switching cycles, thereby participating in closed-loop control and responding promptly to changes in input voltage and current, improving the dynamic response of the second parallel circuit, and thus exhibiting good dynamic performance.

[0066] In the current sharing method of the centralized control interleaved parallel circuit described in this invention, the interleaved parallel circuit is a circuit whose input or output is a time-varying signal, including PFC interleaved parallel circuit and INV interleaved parallel circuit, but not limited to these two circuits.

[0067] In the current sharing method for a centralized control interleaved parallel circuit described in this invention, the interleaved parallel circuit includes N parallel circuits, where N is a positive integer greater than or equal to 2. The number of parallel circuits N can be determined according to specific requirements; correspondingly, the sampling and control frequency needs to be increased to [a higher value]. .

[0068] This invention can be implemented through hardware, software, or a combination of both. It can be implemented centrally in at least one computer system, or distributed in a decentralized manner by different parts of several interconnected computer systems. Any computer system or other device capable of implementing the method of this invention is applicable. A common combination of hardware and software can be a general-purpose computer system with computer programs installed, controlling the computer system to operate according to the method of this invention by installing and executing the programs.

[0069] This invention can also be implemented by a computer program product. Therefore, this invention also relates to a computer-readable storage medium having a computer program stored thereon, the computer program containing all the features of the current sharing method for the centralized control interleaved parallel circuit of this invention, which, when installed in a computer system, can implement the method of this invention. The computer program referred to in this document means any expression of a set of instructions that can be written in any programming language, code, or symbol, which enables a system to have information processing capabilities to directly achieve a specific function, or to achieve a specific function after performing one or both of the following steps: a) converting it into another language, code, or symbol; b) reproducing it in a different format.

[0070] Another preferred embodiment of the present invention includes a centrally controlled interleaved parallel circuit, comprising at least a first parallel circuit and a second parallel circuit and a controller, wherein the controller stores a computer program that, when executed by the controller, implements a current sharing method according to the centrally controlled interleaved parallel circuit. Those skilled in the art will understand that the first parallel circuit and the second parallel circuit may be constructed using any known parallel circuit known in the art.

[0071] The computer-readable storage medium and centralized control interleaved parallel circuit of the present invention, by compensating the duty cycle of the second parallel circuit based on the duty cycle of the first parallel circuit and the change in the time-varying voltage signal, can solve the problem of uneven current between circuits in a low-cost and easily implementable manner, and improve the sinusoidal nature of the second parallel circuit. Furthermore, the real-time current of the second parallel circuit can be calculated based on the real-time current of the first parallel circuit and the aforementioned change in the time-varying voltage signal, thereby participating in closed-loop control and responding promptly to changes in input voltage, current, and bus, improving the dynamic response of each parallel circuit, and thus exhibiting good dynamic performance.

[0072] Although the present invention has been described through specific embodiments, those skilled in the art will understand that various modifications and equivalent substitutions can be made to the invention without departing from its scope. Furthermore, various modifications can be made to the invention for specific situations or materials without departing from its scope. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A current sharing method for a centralized control interleaved parallel circuit, characterized in that, include: S1. Set the duty cycle of the first parallel circuit in the interleaved parallel circuit to the first duty cycle, and set the duty cycle of the second parallel circuit in the interleaved parallel circuit to the second duty cycle. S2. The ratio between the input voltage difference between the zero-crossing sampling of the triangular carrier wave of the first parallel circuit and the input voltage of the periodic value sampling and the bus voltage of the interleaved parallel circuit is set as a second duty cycle compensation amount to ensure that the current of the two parallel circuits is equal at the end of a switching cycle, and the second duty cycle is calculated based on the difference between the first duty cycle and the second duty cycle compensation amount. S3. Calculate the real-time current of the second parallel circuit in the interleaved parallel circuit based on the real-time current of the first parallel circuit, the compensation amount of the first duty cycle and the second duty cycle, and perform closed-loop control on the second parallel circuit based on the real-time current of the second parallel circuit. In step S2, ,in This indicates the second duty cycle. This indicates the first duty cycle. This indicates the second duty cycle compensation amount. This represents the bus voltage value of the interleaved parallel circuit. This indicates the switching period of the interleaved parallel circuit; Indicates the input voltage at Time and ( ) The difference in time; This represents the input voltage sampled at the zero-crossing point of the triangular carrier wave in the first parallel circuit.

2. The current sharing method for a centralized control interleaved parallel circuit according to claim 1, characterized in that... In step S3, the second parallel circuit is calculated based on the following formula in the first step. n Midpoint current during the rising phase of each switching cycle: in, This represents the midpoint current during the rising phase of the second parallel circuit. This represents the midpoint current during the rising phase of the first parallel circuit. This represents the inductance value of the first parallel circuit or the second parallel circuit. This represents the number of periods and takes a positive integer value. This represents the input voltage of the interleaved parallel circuit.

3. The current sharing method for a centralized control interleaved parallel circuit according to claim 2, characterized in that, In step S3, the second parallel circuit is calculated based on the following formula in the first step. n Midpoint current during the descent phase within a switching cycle: in, This represents the midpoint current during the falling phase of the second parallel circuit. This represents the midpoint current during the falling phase of the first parallel circuit.

4. The current sharing method for a centralized control interleaved parallel circuit according to claim 3, characterized in that, The real-time current of the first parallel circuit and the real-time current of the second parallel circuit are equal at the beginning of any switching cycle and at the end of any switching cycle, but are not equal at the end of energy storage. hour, The current ripple of the second parallel circuit is greater than that of the first parallel circuit. hour, The current ripple of the second parallel circuit is smaller than that of the first parallel circuit.

5. The current sharing method for a centralized control interleaved parallel circuit according to claim 4, characterized in that, The interleaved parallel circuit includes a PFC interleaved parallel circuit and an INV interleaved parallel circuit.

6. The current sharing method for a centralized control interleaved parallel circuit according to claim 4, characterized in that, The interleaved parallel circuit includes N parallel circuits, where N is a positive integer greater than or equal to 2.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the current sharing method for the centralized control interleaved parallel circuit according to any one of claims 1-6.

8. A centralized control type interleaved parallel circuit, comprising at least a first parallel circuit and a second parallel circuit and a controller, wherein the controller stores a computer program, characterized in that, When the computer program is executed by the controller, it implements the current sharing method for the centralized control interleaved parallel circuit according to any one of claims 1-6.

Images