Circuit devices and oscillators

Abstract

A circuit arrangement and an oscillator are provided, capable of adjusting the duty cycle of a clock signal with high precision. The circuit arrangement includes: an oscillation circuit electrically connected to a first node electrically connected to one end of an oscillator and a second node electrically connected to the other end of the oscillator, generating an oscillation signal by oscillating the oscillator; a waveform shaping circuit connected to the first node, receiving the oscillation signal from the first node and outputting a clock signal obtained by waveform shaping of the oscillation signal; and a duty cycle adjustment circuit that supplies a bias voltage, variably adjusted according to adjustment data, to the first node, thereby adjusting the duty cycle of the clock signal.

Description

Technical Field

[0001] This invention relates to circuit devices and oscillators, etc. Background Technology

[0002] Conventional circuits with oscillation circuits that cause oscillators such as quartz oscillators to oscillate are known. In such circuits, it is desirable to achieve high precision in the duty cycle of the clock signal generated based on the oscillation signal. For example, in Patent Document 1, a bias circuit with a bias voltage of approximately half the output power supply voltage is provided at the input terminal of the output circuit. This enables an oscillation circuit that can reduce waveform distortion on the high-voltage side or low-voltage side of the amplitude with a high margin and easily adjust the duty cycle of the output waveform to 50%.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-35302

[0004] However, in the oscillation circuit of Patent Document 1, the duty cycle of the clock signal cannot be adjusted with high precision when the waveform of the signal input to the output circuit itself produces nonlinear distortion. Summary of the Invention

[0005] This disclosure relates to a circuit device comprising: an oscillation circuit electrically connected to a first node electrically connected to one end of an oscillator and a second node electrically connected to the other end of the oscillator, generating an oscillation signal by oscillating the oscillator; a waveform shaping circuit connected to the first node, receiving the oscillation signal from the first node and outputting a clock signal obtained by waveform shaping of the oscillation signal; and a duty cycle adjustment circuit supplying a bias voltage variably adjusted according to adjustment data to the first node, thereby adjusting the duty cycle of the clock signal.

[0006] In addition, another aspect of this disclosure relates to an oscillator comprising: the circuit arrangement described above; and the oscillator. Attached Figure Description

[0007] Figure 1 This is an example of the structure of the circuit device in this embodiment.

[0008] Figure 2 This is a detailed structural example of the circuit device in this embodiment.

[0009] Figure 3 This is a more detailed structural example of the circuit device in this embodiment.

[0010] Figure 4 It is a chart that shows the relationship between the adjustment value of the adjusted data and the duty cycle.

[0011] Figure 5It is a chart showing the process variation of the duty cycle of the clock signal.

[0012] Figure 6 It is a chart showing the process variation of the duty cycle when the duty cycle adjustment circuit is used.

[0013] Figure 7 This is a structural example of the circuit device in the first comparative example of this embodiment.

[0014] Figure 8 This is a structural example of the circuit device in the second comparative example of this embodiment.

[0015] Figure 9 This is a variation of the circuit device in this embodiment.

[0016] Figure 10 This is a variation of the circuit device in this embodiment.

[0017] Figure 11 This is a variation of the circuit device in this embodiment.

[0018] Figure 12 This is an example of the structure of a duty cycle adjustment circuit.

[0019] Figure 13 This is an example of an oscillator construction.

[0020] Label Explanation

[0021] 4: Oscillator; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18: External Terminal; 19: External Terminal; 20: Circuit Device; 30: Oscillator Circuit; 32: Variable Capacitor Circuit; 40: Waveform Shaping Circuit; 50: Duty Cycle Adjustment Circuit; 52: Voltage Divider Circuit; 54: Selection Circuit; 60: Processing Circuit; 62: Non-Volatile Memory; 70: Output Buffer Circuit; 90: Power Supply Circuit; 92: Temperature Compensation Circuit; 94: Temperature Sensor Circuit; 120: Circuit Device; 130: Oscillator Circuit; 140: Waveform Shaping Circuit; 220: Circuit Device; 230: Oscillator Circuit; 240: Waveform Shaping Circuit; 250: Bias Circuit; 260: Constant Current Circuit; ADJ: Adjustment Data; BMP: Bump; CB, CF1, CF2, CG: Capacitors; CK: Clock signal; CKQ: Output clock signal; CV1: Variable capacitor element; CV2: Variable capacitor element; CX, CX1, CX2: Capacitors; IS: Current source; IVA1, IVA2, IVB1, IVB2: Inverting circuit; N1: Node 1; N2: Node 2; VCMP: Temperature compensation voltage; R1~Rm-1: Resistor; RB: Feedback resistor; RBS, RCP, RRF, RRFB, RFFC, RX: Resistor; TCK: Clock terminal; TGND: Ground terminal; TR: Bipolar transistor; TVDD: Power supply terminal; TXI, TXO: Terminal; VBS: Bias voltage; VDD: Power supply voltage; VR1~VRm-1: Voltage divider voltage; VREF, VREFB, VREFC: Reference voltage; XI, XO: Oscillation signal. Detailed Implementation

[0022] The embodiments will now be described. Furthermore, the embodiments described below do not unduly limit the scope of the claims. Also, not all structures described in these embodiments are necessarily essential structural elements.

[0023] 1. Circuit device

[0024] Figure 1 An example of the structure of the circuit device 20 of this embodiment is shown. The circuit device 20 of this embodiment includes an oscillation circuit 30, a waveform shaping circuit 40, and a duty cycle adjustment circuit 50. Furthermore, as will be described later... Figure 13 As described above, the oscillator 4 of this embodiment includes an oscillator 10 and a circuit device 20. The oscillator 10 is electrically connected to the circuit device 20. For example, the oscillator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps in a package that houses the oscillator 10 and the circuit device 20.

[0025] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented, for example, using a quartz resonator or similar vibrating plate. For instance, the oscillator 10 can be implemented using a quartz resonator with a shearing angle of AT or SC, a tuning fork type quartz resonator, or a double tuning fork type quartz resonator. For example, the oscillator 10 can be an oscillator built into a temperature-compensated quartz oscillator (TCXO) without a thermostat, or an oscillator built into a thermostat-type quartz oscillator (OCXO) with a thermostat. Alternatively, the oscillator 10 can be an oscillator built into an SPXO (Simple Packaged Crystal Oscillator). Furthermore, the oscillator 10 of this embodiment can also be implemented using various vibrating plates, such as those other than shearing type, tuning fork type, or double tuning fork type, or piezoelectric resonators made of materials other than quartz. For example, as the oscillator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro ElectroMechanical Systems) oscillator formed using a silicon substrate as a silicon oscillator can also be used.

[0026] Circuit device 20 is an integrated circuit device called an IC (Integrated Circuit). For example, circuit device 20 is an IC manufactured by semiconductor technology, which is a semiconductor chip on a semiconductor substrate on which circuit elements are formed.

[0027] The oscillation circuit 30 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 30 is electrically connected to a first node N1 electrically connected to one end of the oscillator 10 and a second node N2 electrically connected to the other end of the oscillator 10, generating oscillation signals XI and XO by causing the oscillator 10 to oscillate. Specifically, the oscillation circuit 30 is electrically connected to a terminal TXI electrically connected to one end of the oscillator 10 and a terminal TXO electrically connected to the other end of the oscillator 10, generating oscillation signals XI and XO by causing the oscillator 10 to oscillate. Terminal TXI is the first terminal, and terminal TXO is the second terminal. Terminals TXI and TXO are, for example, pads of the circuit device 20 of the IC. The oscillation circuit 30 can be implemented, for example, by a drive circuit for oscillation and passive components such as capacitors or resistors provided between terminals TXI and TXO. The drive circuit can be implemented, for example, by a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 30, and the drive circuit drives the oscillator 10 with voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 30, various types of oscillation circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used. Furthermore, a variable capacitor circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitor circuit. The variable capacitor circuit can be implemented, for example, using a variable capacitor element such as a varactor diode. Alternatively, it can be implemented using a capacitor array whose capacitance values ​​are binary-weighted and a switch array connected to the capacitor array. The variable capacitor circuit is electrically connected, for example, to a first signal line connected to terminal TXI. The oscillation circuit 30 may also have: a first variable capacitor circuit electrically connected to the first signal line connected to terminal TXI; and a second variable capacitor circuit electrically connected to a second signal line connected to terminal TXO. In addition, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals and transmitting information via electrical signals. An electrical connection can also be a connection via passive components, etc.

[0028] The waveform shaping circuit 40 is a circuit that shapes the waveform of the oscillation signal XI. It is a buffer circuit that receives the oscillation signal XI as input and outputs a clock signal CK. For example, the waveform shaping circuit 40 is connected to the first node N1, receives the oscillation signal XI from the first node N1, and outputs a clock signal CK obtained by shaping the oscillation signal XI. For example, the waveform shaping circuit 40 shapes a sinusoidal oscillation signal XI and outputs a rectangular wave clock signal CK. The waveform shaping circuit 40 can be configured, for example, by multiple inverting circuits.

[0029] The duty cycle adjustment circuit 50 is a circuit that adjusts the duty cycle of the clock signal CK. The duty cycle adjustment circuit 50 can also be described as a bias voltage adjustment circuit that adjusts the bias voltage VBS. For example, the duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK by supplying a bias voltage VBS, which is variably adjusted according to the adjustment data ADJ, to the first node N1. By adjusting the duty cycle of the clock signal CK, the following also applies: Figure 2 The duty cycle of the output clock signal CKQ of the circuit device 20. The duty cycle is also called the duty period. In this embodiment, the duty cycle is sometimes simply referred to as the duty cycle. For example, when the adjustment data ADJ is a first adjustment value, the duty cycle adjustment circuit 50 generates a bias voltage VBS corresponding to a first voltage value corresponding to the first adjustment value, and when the adjustment data ADJ is a second adjustment value, it generates a bias voltage VBS corresponding to a second voltage value corresponding to the second adjustment value. That is, the duty cycle adjustment circuit 50 supplies a bias voltage VBS whose voltage value is variably set according to the adjustment data ADJ to the first node N1.

[0030] The duty cycle adjustment circuit 50 supplies a bias voltage VBS to the first node N1, which serves as the output node of the oscillation signal XI, thereby making the oscillation signal XI an AC signal that varies around the bias voltage VBS. For example, the oscillation signal XI becomes an AC signal that is DC cut off by a capacitor (not shown), and the center voltage of this AC signal is set by the bias voltage VBS from the duty cycle adjustment circuit 50. Moreover, the oscillation signal XI with the bias voltage VBS set in this way is input to the waveform shaping circuit 40 and waveform shaping is performed, thereby generating a rectangular wave clock signal CK.

[0031] In this case, the adjustment data ADJ is set to an adjustment value such that the duty cycle of the clock signal CK is, for example, 50%. Furthermore, the duty cycle of the clock signal CK is also the duty cycle of the output clock signal CKQ. For example, in cases where variations in semiconductor manufacturing processes are typical, the adjustment data ADJ is set to an adjustment value such that the bias voltage VBS is set to approximately half the power supply voltage of the waveform shaping circuit 40. Moreover, even if the manufacturing process of the P-type or N-type transistors constituting the inverting circuit of the waveform shaping circuit 40 varies rapidly or slowly, the adjustment value of the adjustment data ADJ is set to 50% for the duty cycle of the clock signal CK. Thus, even in cases of manufacturing process variations, a clock signal CK with a duty cycle adjusted to 50% can be generated.

[0032] Figure 2A detailed structural example of the circuit device 20 in this embodiment is shown. For example... Figure 2 As shown, the circuit device 20, in addition to Figure 1 In addition to its structure, it may also include a processing circuit 60, a non-volatile memory 62, an output buffer circuit 70, a power supply circuit 90, a temperature compensation circuit 92, and a temperature sensor circuit 94.

[0033] The processing circuit 60 is a control circuit that performs various control processes, for example, implemented through logic circuits. For instance, the processing circuit 60 performs overall control of the circuit device 20, or controls the sequence of actions of the circuit device 20. Furthermore, the processing circuit 60 controls individual circuit modules of the circuit device 20, such as the oscillation circuit 30, the output buffer circuit 70, and the temperature compensation circuit 92. Additionally, the processing circuit 60 implements read / write control of the non-volatile memory 62. The processing circuit 60 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing, such as a gate array.

[0034] The non-volatile memory 62 stores various information used in the circuit device 20. The non-volatile memory 62 can be implemented, for example, by an EEPROM such as a FAMOS (Floating Gate Avalanche Injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited to these; it can also be an OTP (One Time Programmable) memory or a fuse-type ROM, etc.

[0035] 62 pairs of non-volatile memory Figure 1 The adjustment data ADJ is stored. Furthermore, the adjustment data ADJ read from the non-volatile memory 62 via the processing circuit 60 is input to the duty cycle adjustment circuit 50, which generates a bias voltage VBS that is variably set according to the adjustment data ADJ and supplies it to the first node N1. Thus, the circuit device 20 of this embodiment includes a non-volatile memory 62 that stores the adjustment data ADJ, and the duty cycle adjustment circuit 50 that generates a bias voltage VBS set according to the adjustment data ADJ stored in the non-volatile memory 62. Additionally, as described later, the non-volatile memory 62 also stores information for temperature compensation.

[0036] The output buffer circuit 70 buffers the clock signal CK from the waveform shaping circuit 40 and outputs it as the output clock signal CKQ. That is, the output buffer circuit 70 outputs the output clock signal CKQ based on the oscillation signal XI to the clock terminal TCK. Furthermore, this output clock signal CKQ is output from the clock terminal TCK to the outside via the external terminal of the oscillator 4. For example, the output buffer circuit 70 outputs the output clock signal CKQ in the form of a single-ended CMOS signal. For example, when the output enable signal input via the output enable terminal (not shown) is valid, the output buffer circuit 70 outputs the output clock signal CKQ. On the other hand, when the output enable signal is invalid, the output buffer circuit 70 sets the output clock signal CKQ to a fixed voltage level, such as a low level. Thus, the voltage level of the clock terminal TCK is set to a fixed voltage level. Furthermore, a valid signal is, for example, a high level in positive logic and a low level in negative logic. Conversely, an invalid signal is, for example, a low level in positive logic and a high level in negative logic. Moreover, in... Figure 2 In this circuit, the output buffer circuit 70 outputs one output clock signal CKQ, but it can also output multiple output clock signals by buffering the clock signal CK. In this case, the multiple output clock signals may include, for example, clock signals with different phases, specifically, clock signals with a phase difference of 180 degrees. Furthermore, the output buffer circuit 70 can also output the output clock signal CKQ in a signal format other than CMOS.

[0037] The power supply circuit 90 is supplied with a power supply voltage VDD from the power supply terminal TVDD and a ground voltage GND from the ground terminal TGND, supplying power supply voltages for each circuit block of the circuit device 20. For example, the power supply circuit 90 includes a regulator that provides an regulated power supply voltage generated based on the power supply voltage VDD to each circuit block of the circuit device 20. For example, the power supply circuit 90 supplies a first regulated power supply voltage to the oscillation circuit 30 and a second regulated power supply voltage different from the first regulated power supply voltage to the waveform shaping circuit 40 or the output buffer circuit 70. Furthermore, the power supply circuit 90 also supplies various regulated power supply voltages to the duty cycle adjustment circuit 50, the processing circuit 60, the non-volatile memory 62, the temperature compensation circuit 92, and the temperature sensor circuit 94. Additionally, the power supply circuit 90 includes a reference voltage generation circuit and a reference current generation circuit.

[0038] Temperature compensation circuit 92 performs temperature compensation for the oscillation frequency of oscillation circuit 30. Temperature compensation of the oscillation frequency refers to temperature compensation of the oscillation signals XI and XO of oscillation circuit 30. Specifically, temperature compensation circuit 92 performs temperature compensation based on temperature detection information from temperature sensor circuit 94. For example, temperature compensation circuit 92 generates a temperature compensation voltage based on the temperature detection voltage from temperature sensor circuit 94 and outputs the generated temperature compensation voltage to oscillation circuit 30, thereby performing temperature compensation for the oscillation frequency of oscillation circuit 30. For example, temperature compensation circuit 92 adjusts the capacitance of variable capacitor circuit 32 by outputting a temperature compensation voltage as a capacitor control voltage to the variable capacitor circuit 32 of oscillation circuit 30, thereby performing temperature compensation. In this case, the variable capacitor circuit 32 of oscillation circuit 30 is implemented using a variable capacitor element such as a varactor diode. Temperature compensation is a process that suppresses and compensates for oscillation frequency variations caused by temperature changes. For example, temperature compensation circuit 92 performs temperature compensation based on a polynomial approximation analog method. For example, when the temperature compensation voltage for compensating the frequency-temperature characteristics of the oscillator 10 is approximated by a polynomial, the temperature compensation circuit 92 performs analog temperature compensation based on the coefficient information of the polynomial. Analog temperature compensation is achieved, for example, by adding current and voltage signals, which are analog signals. Specifically, the coefficient information of the polynomial used for temperature compensation is stored in the non-volatile memory 62, and the processing circuit 60 reads this coefficient information from the non-volatile memory 62, for example, and sets it in the register of the temperature compensation circuit 92. Furthermore, the temperature compensation circuit 92 performs analog temperature compensation based on the coefficient information set in the register. Alternatively, the temperature compensation circuit 92 can also perform digital temperature compensation. In this case, the temperature compensation circuit 92 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information from the temperature sensor circuit 94. For example, the temperature compensation circuit 92 calculates frequency adjustment data based on the temperature detection data. Furthermore, by adjusting the capacitance value of the variable capacitor circuit 32 of the oscillation circuit 30 according to the calculated frequency adjustment data, temperature compensation processing of the oscillation frequency of the oscillation circuit 30 is achieved. In this case, the variable capacitor circuit of the oscillation circuit 30 is implemented by a capacitor array and a switch array having multiple capacitors weighted in a binary manner. Furthermore, the non-volatile memory 62 stores a lookup table representing the correspondence between temperature detection data and frequency adjustment data. The temperature compensation circuit 92 performs temperature compensation processing as follows: using the lookup table read from the non-volatile memory 62 by the processing circuit 60, the frequency adjustment data is calculated based on the temperature data.

[0039] Temperature sensor circuit 94 is a sensor circuit for detecting temperature. Specifically, temperature sensor circuit 94 outputs a temperature-dependent voltage that varies according to the ambient temperature as a temperature detection voltage. For example, temperature sensor circuit 94 uses temperature-dependent circuit elements to generate the temperature detection voltage. Specifically, temperature sensor circuit 94 outputs a temperature detection voltage whose voltage value varies with temperature by utilizing the temperature dependence of the forward voltage of a PN junction. The forward voltage of the PN junction can be, for example, the base-emitter voltage of a bipolar transistor. Furthermore, in the case of digital temperature compensation processing, temperature sensor circuit 94 measures the ambient temperature and other temperatures, and outputs the result as temperature detection data. The temperature detection data is data that increases or decreases monotonically relative to the temperature.

[0040] Furthermore, the duty cycle adjustment circuit 50 includes a voltage divider circuit 52 and a selection circuit 54. The voltage divider circuit 52 outputs multiple divided voltages by dividing the power supply voltage and the ground voltage. For example, the voltage divider circuit 52 has multiple resistors connected in series between the power supply node and the ground node, outputting multiple divided voltages obtained by dividing the voltage using these resistors. That is, the voltage divider circuit 52 is implemented using a resistor ladder circuit or the like. The power supply node is the node supplied with the power supply voltage, and the ground node is the node supplied with the ground voltage. Moreover, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages, as the bias voltage VBS. That is, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages, as the bias voltage VBS according to the adjustment data ADJ. Furthermore, the selection circuit 54 selects the second divided voltage, which is any one of the multiple divided voltages, as the reference voltage VREF, which will be described later.

[0041] Figure 3 A more detailed structural example of the circuit device 20 is shown. Figure 3 In the oscillation circuit 30, a current source IS, a bipolar transistor TR, a resistor RX, and a capacitor CX are included. The current source IS and the bipolar transistor TR are connected in series between the power supply node and the ground node of VRG1. These current sources IS and the bipolar transistor TR constitute the driving circuit of the oscillation circuit 30. The current source IS can be implemented, for example, by a CMOS transistor whose gate is biased by an input voltage. The resistor RX is located between the collector node and the base node of the bipolar transistor TR. The capacitor CX is located between the base node of the bipolar transistor TR and the first node N1.

[0042] In addition, Figure 3 In the oscillation circuit 30, variable capacitor elements CV1 and CV2 implemented by varactor diodes, etc., and fixed capacitors CF1 and CF2 with fixed capacitance values ​​are included as follows: Figure 2The variable capacitor circuit 32. Specifically, the oscillation circuit 30 includes: a fixed capacitor CF1, one end of which is connected to the first node N1; and a variable capacitor element CV1, one end of which is connected to the other end of the fixed capacitor CF1, with a variable capacitance value. Furthermore, the oscillation circuit 30 includes: a fixed capacitor CF2, one end of which is connected to the second node N2; and a variable capacitor element CV2, one end of which is connected to the other end of the fixed capacitor CF2, with a variable capacitance value. A capacitor CG is disposed between the other ends of the variable capacitor elements CV1 and CV2 and the ground node. Moreover, from... Figure 2 The temperature compensation voltage VCMP of the temperature compensation circuit 92 is supplied to one end of the variable capacitor elements CV1 and CV2 via resistor RCP. Furthermore, the reference voltage VREF is supplied to the other end of the variable capacitor elements CV1 and CV2 via resistor RRF. Thus, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREF is applied to the variable capacitor elements CV1 and CV2. Therefore, the variable capacitor elements CV1 and CV2 are set to the capacitance corresponding to the temperature compensation voltage VCMP, thereby achieving temperature compensation of the oscillation frequency of the oscillation circuit 30. Additionally, in Figure 3 In the circuit, the duty cycle adjustment circuit 50, which supplies the bias voltage VBS, also supplies the reference voltage VREF.

[0043] The duty cycle adjustment circuit 50 is implemented by a trapezoidal resistor circuit disposed between the power node and the ground node of VRG1, and outputs a bias voltage VBS as a voltage divider voltage generated by the trapezoidal resistor circuit. Furthermore, the duty cycle adjustment circuit 50 outputs a reference voltage VREF for temperature compensation as described above. Moreover, the bias voltage VBS is supplied to the first node N1 via a resistor RBS. Using this bias voltage VBS, the center voltage of the oscillation signal XI, which is an AC signal, is set, and the oscillation signal XI, for example a sine wave, varying around the bias voltage VBS, is input to the waveform shaping circuit 40.

[0044] The waveform shaping circuit 40 includes multiple inverting circuits IVA1 and IVA2 as buffer circuits. Inverting circuits IVA1 and IVA2 are respectively composed of a P-type transistor and an N-type transistor connected in series between the power supply node and the ground node of VREG2. Furthermore, an oscillation signal XI, whose bias point is set by a bias voltage VBS, is input as an input signal to the primary inverting circuit IVA1 of the waveform shaping circuit 40. That is, the oscillation signal XI is input to the gates of the P-type transistor and the N-type transistor constituting the inverting circuit IVA1. Moreover, the output signal of the inverting circuit IVA1 is input to the next-stage inverting circuit IVA2, which outputs a clock signal CK. Thus, the waveform shaping circuit 40 outputs a rectangular wave clock signal CK that has shaped the oscillation signal XI. Additionally, as an example, the temperature compensation voltage VCMP is, for example, a voltage centered at 0.9V that varies according to the temperature detection result. The reference voltage VREF is, for example, a voltage of approximately 0.3V to 0.4V. The power supply voltage of VREG1 is, for example, 1.2V, and the power supply voltage of VREG2 is, for example, 1.0V. The bias voltage VBS is, for example, a voltage adjusted within a range of ±0.1V with 0.5V as the center. 0.5V is about half of the power supply voltage of VREG2 of the waveform shaping circuit 40.

[0045] As described above, the circuit device 20 of this embodiment includes: an oscillation circuit 30 connected to a first node N1 and a second node N2 connected to the oscillator 10, generating oscillation signals XI and XO; a waveform shaping circuit 40 that receives the oscillation signal XI from the first node N1 and outputs a clock signal CK; and a duty cycle adjustment circuit 50 that supplies a bias voltage VBS, which is variably adjusted according to adjustment data ADJ, to the first node N1. Furthermore, the oscillation signal XI, which varies around the bias voltage VBS, which is variably adjusted according to the adjustment data ADJ, is input to the waveform shaping circuit 40 for waveform shaping, thereby adjusting the duty cycle of the clock signal CK. In this way, the duty cycle of the clock signal CK can be adjusted by taking into account process variations such as the threshold voltage of the P-type or N-type transistor constituting the waveform shaping circuit 40, distortion of the oscillation waveform, or deviations in the duty cycle in subsequent circuits. The duty cycle of the output clock signal CKQ from the circuit device 20 can also be adjusted. This allows the duty cycle to approach, for example, 50%, enabling high-precision duty cycle adjustment.

[0046] For example, Figure 4 A chart showing the relationship between the adjustment value and duty cycle of the adjusted data ADJ. Figure 4 For example, by using 5-bit adjustment data ADJ, a duty cycle adjustment of 50% ± 8% is performed in 32 stages, resulting in a duty cycle adjustment with a resolution of 0.4%.

[0047] Figure 5 This is a graph showing the angular simulation results of the duty cycle variation due to process changes, without duty cycle adjustment by the duty cycle adjustment circuit 50. Here, TYP represents the typical case. SF represents the case where the N-type transistor is slow and the P-type transistor is fast; FS represents the case where the N-type transistor is fast and the P-type transistor is slow; SS represents the case where both the N-type and P-type transistors are slow; and FF represents the case where both the N-type and P-type transistors are fast. (The last sentence appears to be a separate, unrelated statement.) Figure 5 As shown, due to variations in semiconductor manufacturing processes, the duty cycle varies within a range of approximately 50% ± 5%.

[0048] on the other hand, Figure 6 This is a graph showing the angular simulation results of the duty cycle variation under the condition that the duty cycle adjustment circuit 50 has been implemented. For example... Figure 6 As shown, the duty cycle adjustment circuit 50 supplies a bias voltage VBS that is variably set according to the adjustment data ADJ, thereby enabling high-precision duty cycle adjustment, for example, to allow the duty cycle variation to be within a range of 50% ± 1%.

[0049] Figure 7 The circuit arrangement 120 of the first comparative example of this embodiment is shown. In the oscillation circuit 130 of the circuit arrangement 120 of the first comparative example, in addition to the capacitor CX1 between the first node N1 and the base node of the bipolar transistor TR, a capacitor CX2 is also provided between the second node N2 and the collector node of the bipolar transistor TR. Furthermore, one end of the variable capacitor element CV1 is connected to the first node N1, and the other end is connected to the supply node of the temperature compensation voltage VCMP. One end of the variable capacitor element CV2 is connected to the second node N2, and the other end is connected to the supply node of the temperature compensation voltage VCMP. In addition, a reference voltage VREFB is supplied to the node of the oscillation signal XI, i.e., the first node N1, and a reference voltage VREFC is supplied to the node of the oscillation signal XO, i.e., the second node N2. Thus, the oscillation signal XI becomes an oscillation signal that varies around the reference voltage VREFB, and the oscillation signal XO becomes an oscillation signal that varies around the reference voltage VREFC. The reference voltage VREFB is, for example, 0.4V, and the reference voltage VREFC is, for example, 1.2V.

[0050] Moreover, in Figure 7In the first comparative example, a DC cutoff capacitor CB is provided between the first node N1 and the input node of the waveform shaping circuit 140. As a result, the DC component of the oscillation signal XI is cut off, and the AC component is input to the waveform shaping circuit 140. Furthermore, the waveform shaping circuit 140 includes inverting circuits IVB1 and IVB2, with a feedback resistor RB provided between the output node and the input node of the primary inverting circuit IVB1. By providing such a feedback resistor RB, the primary inverting circuit IVB1 sets its bias point through self-biasing.

[0051] Thus, in Figure 7 In the first comparative example, a temperature-compensated reference voltage VREFB is applied to the node N1 of the oscillation signal XI, i.e., the first node. The oscillation signal XI then becomes an oscillation signal that varies around the reference voltage VREFB. Here, the reference voltage VREFB is adjusted, for example, to optimize the sensitivity of the variable capacitor element CV1, and is inconsistent with the threshold voltage of the primary inverting circuit IVB1 of the waveform shaping circuit 140. As an example, in the first comparative example, a power supply voltage of VREG = 1.5V is supplied to the inverting circuit IVB1, therefore the threshold voltage of the inverting circuit IVB1 is approximately VREG / 2 = 0.75V. On the other hand, the reference voltage VREFB is adjusted, for example, to VREFB = 0.4V, to optimize the sensitivity of the variable capacitor element CV1, therefore the threshold voltage of the inverting circuit IVB1 is inconsistent with the reference voltage VREFB, which is the center voltage of the oscillation signal XI. Furthermore, the reference voltage VREFB is adjusted based on manufacturing deviations of the varactor diode, which is a variable capacitor element, rather than on manufacturing deviations of the P-type and N-type transistors that constitute the inverting circuit IVB1.

[0052] Therefore, in Figure 7 In the first comparative example, a capacitor CB for DC cutoff needs to be set at the input node of the inverting circuit IVB1 to cut off the DC component of the oscillation signal XI, allowing only the AC component of the oscillation signal XI to be input to the inverting circuit IVB1. Furthermore, in the primary inverting circuit IVB1, its output and input nodes are connected via a feedback resistor RB, thereby adjusting the bias point through self-biasing. However, in this self-biasing-based bias point adjustment, when nonlinear distortion occurs in the waveform of the oscillation signal XI, the duty cycle of the clock signal CK changes, resulting in a problem where high precision of the duty cycle cannot be achieved. For example, in… Figure 7In the first comparative example, the actual duty cycle deviation was approximately 50% ± 4%, which is insufficient to achieve a high duty cycle precision of, for example, within 50% ± 1%. For example, in applications where an external processing unit processes an output clock signal CKQ obtained by buffering the clock signal CK, this processing unit uses both the rising and falling edges of the output clock signal CKQ. In such applications, proper processing cannot be performed with a duty cycle of approximately 50% ± 4%, therefore, a high duty cycle precision of within 50% ± 1% is sometimes required. Figure 7 The first comparative example cannot meet such a requirement.

[0053] Regarding this point, Figure 3 In the circuit device 20 of this embodiment, a DC cutoff capacitor CF1 is provided between the first node N1 of the oscillation signal XI and the variable capacitor element CV1. Furthermore, a DC cutoff capacitor CF2 is also provided between the second node N2 of the oscillation signal XO and the variable capacitor element CV2. Therefore, the bias voltage VBS can be set independently of the temperature compensation reference voltage VREF, and the oscillation signal XI can be made into an oscillation signal that varies around the bias voltage VBS.

[0054] For example, by adjusting the reference voltage VREF, the variable capacitor elements CV1 and CV2 can be adjusted to their optimal sensitivity. In this case, the capacitance of node 1 N1 becomes the series capacitance of variable capacitor element CV1 and capacitor CF1, and the capacitance of node 2 N2 becomes the series capacitance of variable capacitor element CV2 and capacitor CF2. However, by making the capacitances of capacitors CF1 and CF2 sufficiently large, the capacitances of node 1 N1 and node 2 N2 can be adjusted to appropriate capacitances corresponding to the ambient temperature using variable capacitor elements CV1 and CV2.

[0055] Furthermore, in this embodiment, the bias voltage VBS can be adjusted using the adjustment data ADJ and the duty cycle adjustment circuit 50 to a suitable voltage that makes the duty cycle of the clock signal CK close to 50%, independent of the reference voltage VREF.

[0056] For example, suppose that due to process variations such as the threshold voltage of P-type or N-type transistors, Figure 3The threshold voltage of the primary inverter circuit IVA1 in the waveform shaping circuit 40 becomes lower than half the voltage of VREG2, which is the power supply voltage. For example, when there is a process variation such as N-type transistors becoming faster and P-type transistors becoming slower, the threshold voltage of the inverter circuit IVA1 becomes lower than half the voltage of VREG2. In this case, when the bias voltage VBS is always half the voltage of VREG2, the duty cycle of the clock signal CK will be greater than 50%. In this case, in this embodiment, the duty cycle adjustment circuit 50 also sets the bias voltage VBS to be lower than half the voltage of VREG2 according to the adjustment data ADJ. In this way, even when the threshold voltage of the inverter circuit IVA1 becomes low due to process variation, the bias voltage VBS, which is the center voltage of the oscillation signal XI, also becomes lower, so the duty cycle of the clock signal CK can be made close to 50%. Therefore, high-precision duty cycle adjustment with a duty cycle variation within 50% ± 1% can be achieved.

[0057] On the other hand, suppose that due to process variations such as the threshold voltages of P-type and N-type transistors, the threshold voltage of the primary inverter circuit IVA1 of the waveform shaping circuit 40 becomes higher than half the voltage of VREG2. For example, when there is a process variation such as P-type transistors becoming faster and N-type transistors becoming slower, the threshold voltage of the inverter circuit IVA1 becomes higher than half the voltage of VREG2. In this case, when the bias voltage VBS is always half the voltage of VREG2, the duty cycle of the clock signal CK will be less than 50%. In this case, in this embodiment, the duty cycle adjustment circuit 50 also sets the bias voltage VBS to be higher than half the voltage of VREG2 according to the adjustment data ADJ. In this way, even if the threshold voltage of the inverter circuit IVA1 becomes high due to process variations, the bias voltage VBS, which is the center voltage of the oscillation signal XI, also becomes higher, thus enabling the duty cycle of the clock signal CK to approach 50%. Therefore, it can achieve high-precision duty cycle adjustment with a duty cycle variation within 50% ± 1%.

[0058] In addition, Figure 3 In the middle, since it is not necessary to set it Figure 7 The DC cutoff capacitor CB provided in the first comparative example can suppress the attenuation of the oscillation amplitude caused by the voltage division between the DC cutoff capacitor CB and the input capacitor, thus achieving low noise floor. Furthermore, since it is not necessary to... Figure 7 The feedback resistor RB shown can thus prevent abnormal oscillations caused by the feedback resistor RB.

[0059] Figure 8The circuit arrangement 220 of the second comparative example of this embodiment is shown. This second comparative example corresponds to the circuit of Patent Document 1 and includes an oscillation circuit 230, a waveform shaping circuit 240, a bias circuit 250, and a constant current circuit 260. In this second comparative example, the bias circuit 250 is a replica of the waveform shaping circuit 240, and the bias voltage output by the bias circuit 250 depends on the supplied power supply voltage VDD. For example, the bias circuit 250 outputs a bias voltage of approximately half of VDD. However, the duty cycle of the clock signal CK varies not only due to a deviation of approximately ±0.1V in the threshold voltage of the P-type or N-type transistor in the primary inverter circuit, but also due to subsequent circuitry and distortion of the oscillation waveform. Therefore, in Figure 8 In the second comparative example, the following problem exists: it is impossible to achieve high-precision duty cycle adjustment that takes into account all these varying factors. Additionally, in Figure 8 In the second comparative example, the bias circuit 250 only outputs a bias voltage of about 1 / 2 of VDD, and there is no adjustment circuit that adjusts the bias voltage based on the adjustment data.

[0060] Regarding this, in the circuit device 20 of this embodiment, the bias voltage VBS can be variably adjusted according to the adjustment data ADJ. That is, a duty cycle adjustment circuit 50 is provided to adjust the bias voltage VBS according to the adjustment data ADJ. Therefore, in addition to, for example Figure 3 In addition to considering deviations such as the threshold voltage of the P-type or N-type transistor in the primary inverter circuit IVA1, the bias voltage VBS can also be adjusted by taking into account deviations in the duty cycle of subsequent circuits and distortion of the oscillation waveform, thereby adjusting the duty cycle of the clock signal CK. Figure 8 Compared to the second comparative example, it can achieve high-precision duty cycle adjustment.

[0061] For example, the circuit device 20 of this embodiment includes a non-volatile memory 62 that stores adjustment data ADJ, and a duty cycle adjustment circuit 50 that generates a bias voltage VBS set according to the adjustment data ADJ stored in the non-volatile memory 62. For example, when the adjustment data ADJ stored in the non-volatile memory 62 is a first adjustment value, the duty cycle adjustment circuit 50 generates a bias voltage VBS corresponding to the first adjustment value, and when the adjustment data ADJ is a second adjustment value, it generates a bias voltage VBS corresponding to the second adjustment value. Thus, by storing the adjustment data ADJ, which enables the setting of the optimal duty cycle, in the non-volatile memory 62, and supplying the bias voltage VBS corresponding to the adjustment data ADJ read from the non-volatile memory 62 by the duty cycle adjustment circuit 50 during actual operation of the circuit device 20, a high-precision duty cycle adjustment of, for example, 50% ± 1% can be achieved. Specifically, during the inspection process such as manufacturing the circuit device 20, the duty cycle of the output clock signal CKQ is measured, and adjustment data ADJ is determined based on the measurement result and written into the non-volatile memory 62. For example, the adjustment data ADJ is determined not only considering deviations such as transistor threshold voltage caused by process variations, but also considering nonlinear distortion of the oscillation waveform. Moreover, during the actual operation of the circuit device 20, by reading the adjustment data ADJ determined based on the measurement result from the non-volatile memory 62 and supplying a bias voltage VBS corresponding to the adjustment data ADJ by the duty cycle adjustment circuit 50, a high-precision duty cycle adjustment, such as within 50% ± 1%, can be achieved.

[0062] Furthermore, in this embodiment, Figure 3 The power supply voltage of the oscillation circuit 30, i.e., VRG1, becomes a voltage greater than or equal to the power supply voltage of the waveform shaping circuit 40, i.e., VREG2. That is, the relationship VREG1 ≥ VREG2 holds. As an example, VRG1 is 1.2V and VREG2 is 1V.

[0063] On the other hand, Figure 8 In the second comparative example, VREG, the power supply voltage of the oscillation circuit 230, is 1.2V, and VDD, the power supply voltage of the waveform shaping circuit 240 or the bias circuit 250, is 1.8 to 5V, thus the relationship VREG < VDD holds. Therefore, the amplitude voltage of the oscillation signal XI input to the waveform shaping circuit 240 is less than the power supply voltage VDD of the waveform shaping circuit 240, and the rising and falling waveforms of the output signal of the primary inverter circuit of the waveform shaping circuit 240 do not become steep, but become gentle waveforms. Moreover, when the output signal of the primary inverter circuit becomes a gentle waveform, the duty cycle will change due to deviations in the threshold voltages of the P-type or N-type transistors in the next stage inverter circuit.

[0064] In contrast, in this embodiment, VRG1, which serves as the power supply voltage for the oscillation circuit 30, becomes a voltage higher than or equal to VREG2, which serves as the power supply voltage for the waveform shaping circuit 40. Therefore, the amplitude of the oscillation signal XI input to the waveform shaping circuit 40 can be maximized within the driving voltage range of the waveform shaping circuit 40. That is, within the driving voltage range of the waveform shaping circuit 40 set by VREG2, a full-swing oscillation signal XI can be input to the primary inverter circuit IVA1 of the waveform shaping circuit 40. Therefore, the period during which both the P-type and N-type transistors of the primary inverter circuit IVA1 are turned on almost disappears, resulting in steeper rising and falling waveforms of the output signal of the inverter circuit IVA1. As a result, duty cycle deviation caused by deviations in the threshold voltages of the P-type or N-type transistors of the next-stage inverter circuit IVA2 can be reduced. Furthermore, AM noise caused by amplitude fluctuations in the oscillation signal XI is converted into PM noise, which is phase noise, through waveform shaping by the waveform shaping circuit 40. Regarding this point, if VREG1 is set to ≥ VREG2 as in this embodiment, and the amplitude of the oscillation signal XI is increased as much as possible within the driving voltage range of the waveform shaping circuit 40, the degree of conversion from AM noise to PM noise can be reduced, thereby improving the signal quality of the clock signal CK. Furthermore, the waveform shaping circuit 40 and the subsequent output buffer circuit 70 operate with the same VREG2 power supply voltage, but by making the power supply voltage of VREG2 lower than the power supply voltage of the oscillation circuit 30, i.e., VREG1, the power consumption in the output buffer circuit 70 can be reduced. For example, the output buffer circuit 70 consumes more power than other circuit modules because it drives a large external load, but by setting VREG2 to a voltage lower than VREG1, power consumption can be reduced accordingly.

[0065] In addition, such as Figure 3 As shown, in this embodiment, the oscillation circuit 30 includes: a fixed-capacitance capacitor CF1, one end of which is connected to the first node N1, and the capacitance value is fixed; and a variable-capacitance element CV1, one end of which is connected to the other end of the fixed-capacitance capacitor CF1, and the capacitance value is variable. Furthermore, a temperature compensation voltage VCMP is input to one end and the other end of the variable-capacitance element CV1, and a reference voltage VREF is input to the other end. For example, in... Figure 3In this configuration, a temperature compensation voltage VCMP is input to one end of the variable capacitor element CV1, and a reference voltage VREF is input to the other end. Alternatively, the temperature compensation voltage VCMP can be input to the other end of the variable capacitor element CV1, which serves as the ground node, and the reference voltage VREF can be input to one end of the variable capacitor element CV1, which serves as the capacitor CF1. Furthermore, the variable capacitor element CV2 has the same connection structure as the variable capacitor element CV1; detailed explanation is omitted here.

[0066] According to this structure, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREF can be applied to the variable capacitor element CV1. By changing the capacitance value of the variable capacitor element CV1 using the temperature compensation voltage VCMP with the reference voltage VREF as a reference, temperature compensation of the oscillation frequency of the oscillation circuit 30 can be achieved. Furthermore, by setting a capacitor CF1 with a fixed capacitance, the bias voltage VBS and the reference voltage VREF can be adjusted independently. That is, while adjusting the duty cycle by changing the bias voltage VBS, the reference voltage VREF of the variable capacitor element CV1, such as the varactor diode, can also be adjusted independently. For example, while adjusting the duty cycle of the bias voltage VBS by changing the duty cycle of the clock signal CK to approximately 50%, the reference voltage VREF can be adjusted so that the potential difference across the variable capacitor element CV1 is greater than 0V and the sensitivity is optimal.

[0067] Furthermore, in this embodiment, the duty cycle adjustment circuit 50 outputs a bias voltage to the first node N1 and outputs a reference voltage VREF to the other end of one end of the variable capacitor element CV1. For example, in Figure 3 In this circuit, a temperature compensation voltage VCMP is input to one end of the variable capacitor element CV1, and the duty cycle adjustment circuit 50 outputs a reference voltage VREF to the other end of the variable capacitor element CV1. Alternatively, the temperature compensation voltage VCMP can be input to the other end of the variable capacitor element CV1, and the duty cycle adjustment circuit 50 can output a reference voltage VREF to one end of the variable capacitor element CV1.

[0068] With this structure, a single duty cycle adjustment circuit 50 can be used to supply a bias voltage VBS to adjust the duty cycle of the clock signal CK, and a reference voltage VREF for temperature compensation can also be supplied to achieve temperature compensation of the oscillation frequency. In other words, the duty cycle adjustment circuit 50, which supplies the reference voltage VREF for temperature compensation, can effectively utilize the bias voltage VBS to adjust the duty cycle. This enables circuit commonality and miniaturization of the circuit device 20, and also achieves low power consumption of the circuit device 20.

[0069] Specifically, as will be discussed later. Figure 12 As detailed in the description, the duty cycle adjustment circuit 50 includes: a voltage divider circuit 52 having multiple resistors connected in series between the power supply node and the ground node, outputting multiple divided voltages obtained by dividing the voltages through the multiple resistors; and a selection circuit 54 that selects any one of the multiple divided voltages as the bias voltage VBS. That is, the voltage divider circuit 52 is implemented using a trapezoidal resistor circuit, and the selection circuit 54 selects the bias voltage VBS from the multiple divided voltages generated by the voltage divider circuit 52 (which is a trapezoidal resistor circuit) according to the input adjustment data ADJ, and supplies it to the first node N1. With this structure, for example, multiple divided voltages are generated between the power supply voltage of VREG1 and GND by the voltage divider circuit 52, and the voltage corresponding to the adjustment data ADJ is selected from the generated multiple divided voltages, thereby generating the bias voltage VBS as the center voltage of the oscillation signal XI.

[0070] Furthermore, in this embodiment, the selection circuit 54 selects a first voltage divider, which is any one of the multiple voltage dividers from the voltage divider circuit 52, as the bias voltage VBS, and selects a second voltage divider, which is any one of the multiple voltage dividers, as the reference voltage VREF. Thus, by supplying the first voltage divider selected by the selection circuit 54 from the multiple voltage dividers as the bias voltage VBS to the first node N1, the duty cycle of the clock signal CK can be adjusted. Moreover, by supplying the second voltage divider selected by the selection circuit 54 from the multiple voltage dividers as the reference voltage VREF, the variable capacitor element CV1 operates within an appropriate sensitivity range, thereby achieving temperature compensation of the oscillation frequency. Furthermore, to generate the bias voltage VBS and the reference voltage VREF, only one trapezoidal resistor circuit is needed as the voltage divider circuit 52. Therefore, compared to the case where a first trapezoidal resistor circuit for the bias voltage and a second trapezoidal resistor circuit for the reference voltage are provided, the circuit area of ​​the circuit device 20 can be reduced. Furthermore, compared to the case where a first trapezoidal resistor circuit and a second trapezoidal resistor circuit are provided, the current flowing from the power node to the ground node can be set to, for example, about 1 / 2, thus enabling the circuit device 20 to achieve low power consumption.

[0071] 2. Variations

[0072] The circuit device 20 of this embodiment is not limited to the structural example described above, and various modifications can be implemented. Hereinafter, various modifications of this embodiment will be described.

[0073] For example in Figure 9 In the modified example, the structure of the oscillating circuit 30 is the same as... Figure 3 Different. For example, in Figure 9 In, not set Figure 3Fixed capacitors CF1 and CF2 are used. One end of variable capacitor CV1 is connected to node 1 N1, and a temperature compensation voltage VCMP is supplied to the other end of variable capacitor CV1. Similarly, one end of variable capacitor CV2 is connected to node 2 N2, and a temperature compensation voltage VCMP is supplied to the other end of variable capacitor CV2. A reference voltage VREFB is supplied to node 1 N1 from the duty cycle adjustment circuit 50 via resistor RRFB, and a reference voltage VREFC is supplied to node 2 N2 from the duty cycle adjustment circuit 50 via resistor RRFC. Thus, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREFB is applied across variable capacitor CV1, and a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREFC is applied across variable capacitor CV2. Furthermore, the oscillation signal XI becomes an oscillation signal that varies around the reference voltage VREFB, and the oscillation signal XO becomes an oscillation signal that varies around the reference voltage VREFC. In addition, in Figure 9 In this circuit, a DC cutoff capacitor CX2 is provided between the first node N1 and the input node of the waveform shaping circuit 40. By providing such a capacitor CX2, the DC component of the oscillation signal XI is cut off, and only the AC component is transmitted to the waveform shaping circuit 40. Furthermore, for the AC component of the oscillation signal XI, the bias voltage VBS, which serves as the bias point, is set by the duty cycle adjustment circuit 50, thereby enabling the oscillation signal XI, which varies around the bias voltage VBS, to be input to the waveform shaping circuit 40.

[0074] exist Figure 10 , Figure 11 In this circuit, the circuit device 20 includes an output buffer circuit 70 that buffers the clock signal CK and outputs an output clock signal CKQ to the outside. The output buffer circuit 70, for example, has a buffer circuit with a higher drive capability than the waveform shaping circuit 40, and outputs the clock signal CKQ, which has been buffered by this high-drive-capability buffer circuit, to the outside of the circuit device 20. Therefore, even under a large external load, an output clock signal CKQ with an appropriate drive waveform can be supplied to the external load for driving.

[0075] In addition, Figure 10 In this circuit, when the temperature compensation voltage is set to VCMP and the reference voltage is set to VREF, the duty cycle adjustment circuit 50 supplies a reference voltage VREF where VCMP-VREF is greater than 0V. For example, the reference voltage VREF is supplied by applying a voltage greater than 0V to the variable capacitor element CV1. Similarly, the reference voltage VREF is supplied by applying a voltage greater than 0V to the variable capacitor element CV2.

[0076] exist Figure 10 In this circuit, the temperature compensation voltage VCMP is, for example, a voltage that varies with temperature in a three-fold manner, centered at 0.9V. Furthermore, the duty cycle adjustment circuit 50 ensures that VCMP-VREF is greater than 0V. Figure 10 A reference voltage VREF of, for example, 0.3V is supplied to the variable capacitor element CV1. This applies a voltage VCMP-VREF greater than 0V to the variable capacitor element CV1. Therefore, the capacitance of the variable capacitor element CV1 varies variablely within an appropriate sensitivity range according to the temperature compensation voltage VCMP. Similarly, a voltage VCMP-VREF greater than 0V is also applied to the variable capacitor element CV2, and the capacitance of the variable capacitor element CV2 varies variablely within an appropriate sensitivity range according to the temperature compensation voltage VCMP. Thus, the circuit device 20 can be used as a circuit device for a TCXO, and an oscillator for the TCXO can be realized.

[0077] On the other hand, Figure 11 In this circuit, the duty cycle adjustment circuit 50 supplies a reference voltage VREF that makes VCMP-VREF below 0V. For example, the reference voltage VREF is supplied by applying a voltage below 0V to the variable capacitor element CV1. Similarly, the reference voltage VREF is supplied by applying a voltage below 0V to the variable capacitor element CV2. Figure 11 In this process, a temperature compensation voltage VCMP of approximately 0.6V is supplied. Therefore, in Figure 11 In this circuit, the duty cycle adjustment circuit 50 supplies a reference voltage VREF of, for example, 0.9V to the variable capacitor element CV1, so that VCMP-VREF becomes 0V or less. Thus, a voltage VCMP-VREF of 0V or less is applied to the variable capacitor element CV1. Similarly, VCMP-VREF of 0V or less is also applied to the variable capacitor element CV2. Therefore, the circuit arrangement 20 can be used as a circuit arrangement for an SPXO, and an oscillator for the SPXO can be realized.

[0078] For example, the duty cycle adjustment circuit 50 supplies a voltage of approximately 0.5V ± 0.1V as the bias voltage VBS. Therefore, in implementing a TCXO... Figure 10 In the trapezoidal resistor circuit of voltage divider circuit 52, the voltage-divided tap of the output reference voltage VREF becomes the ground node-side tap compared to the voltage-divided tap of the output bias voltage VBS. On the other hand, in implementing SPXO... Figure 11In the trapezoidal resistor circuit of the voltage divider circuit 52, the voltage division tap of the output reference voltage VREF becomes the tap on the power node side of VREG1, compared to the voltage division tap of the output bias voltage VBS. Thus, according to this embodiment, by simply switching the position of the voltage division tap of the output bias voltage VBS in the trapezoidal resistor circuit of the voltage divider circuit 52, the same circuit arrangement 20 can be used... Figure 10 That way it can be used as a circuit device for a TCXO, or as... Figure 11 That is, it can be used as a circuit device for SPXO. Therefore, circuit device 20 can be shared in both TCXO and SPXO.

[0079] Figure 12 An example of the structure of the duty cycle adjustment circuit 50 is shown. The duty cycle adjustment circuit 50 includes a voltage divider circuit 52 and a selection circuit 54. The voltage divider circuit 52 has multiple resistors R1 to Rm connected in series between the power node and the ground node of VREG1, and outputs multiple divided voltages VR1 to VRm-1 obtained by dividing the voltages of the multiple resistors R1 to Rm. Then, the selection circuit 54 selects any one of the multiple divided voltages VR1 to VRm-1 as the bias voltage VBS according to the adjustment data ADJ. This selection circuit 54 can be implemented, for example, by multiple selection circuits that select voltages in a tournament manner. Specifically, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages VR1 to VRm-1, as the bias voltage VBS and outputs it, and selects the second divided voltage, which is any one of the multiple divided voltages VR1 to VRm-1, as the reference voltage VREF and outputs it. Therefore, a single duty cycle adjustment circuit 50 can be used to supply both the bias voltage VBS for duty cycle adjustment and the reference voltage VREF for temperature compensation, thus achieving circuit sharing.

[0080] 3. Oscillator

[0081] Figure 13 An example of the construction of the oscillator 4 according to this embodiment is shown. The oscillator 4 has an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 is formed of, for example, ceramic, and has a housing space inside, in which the oscillator 10 and the circuit device 20 are housed. The housing space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0082] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the cover and the base 16. The oscillator 10 is supported on a stepped portion provided inside the base 16 via terminal electrodes. The circuit device 20 is disposed on the inner bottom surface of the base 16. Specifically, the circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inner bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, through which the oscillator 10 and the circuit device 20 are electrically connected. Furthermore, the circuit device 20 is electrically connected to the external terminals 18 and 19 of the oscillator 4 via the bump BMP or the internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. Thus, clock signals can be output to external devices.

[0083] In addition, Figure 13 In this embodiment, the circuit device 20 is flip-mounted with its active surface facing downwards, but this embodiment is not limited to this mounting. For example, the circuit device 20 can also be mounted with its active surface facing upwards. That is, the circuit device 20 is mounted with its active surface facing the oscillator 10. Alternatively, the oscillator 4 can also be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes: a base having a semiconductor substrate and a through electrode penetrating between a first surface and a second surface of the semiconductor substrate; an oscillator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding member such as a metal bump; and an external terminal provided on the second surface side of the semiconductor substrate via an insulating layer such as a reconfigured wiring layer. Furthermore, an integrated circuit that becomes the circuit device 20 is formed on the first or second surface of the semiconductor substrate. In this case, the multiple substrates and multiple covers are joined by bonding a first semiconductor wafer having multiple bases configured with an oscillator 10 and an integrated circuit to a second semiconductor wafer having multiple covers, and then the oscillator 4 is monolithically produced using a dicing machine or the like. In this way, a wafer-level packaged oscillator 4 can be realized, and the oscillator 4 can be manufactured with high productivity and low cost.

[0084] As described above, the circuit arrangement of this embodiment includes: an oscillation circuit electrically connected to a first node electrically connected to one end of an oscillator and a second node electrically connected to the other end of the oscillator, generating an oscillation signal by oscillating the oscillator; and a waveform shaping circuit connected to the first node, receiving the oscillation signal from the first node and outputting a clock signal obtained by waveform shaping the oscillation signal. Furthermore, the circuit arrangement includes a duty cycle adjustment circuit that supplies a bias voltage, variably adjusted according to adjustment data, to the first node, thereby adjusting the duty cycle of the clock signal.

[0085] In this embodiment, the oscillation circuit causes an oscillator electrically connected via nodes 1 and 2 to oscillate, thereby generating an oscillation signal. The oscillation signal at node 1 is input to a waveform shaping circuit for waveform shaping to generate a clock signal. At this time, the duty cycle adjustment circuit supplies a bias voltage, which is variably adjusted according to adjustment data, to node 1. Thus, the oscillation signal at node 1 becomes an oscillation signal that varies around the bias voltage. Therefore, since the bias voltage of the oscillation signal can be adjusted according to the adjustment data in a way that achieves the optimal duty cycle with the clock signal, and this oscillation signal is input to the waveform shaping circuit, the duty cycle can be adjusted with high precision.

[0086] Alternatively, in this embodiment, a non-volatile memory may be included to store adjustment data, and the duty cycle adjustment circuit generates a bias voltage that is set according to the adjustment data stored in the non-volatile memory.

[0087] In this way, by storing the adjustment data that enables the optimal duty cycle adjustment in a non-volatile memory, and reading the adjustment data from the non-volatile memory when the circuit device is actually in operation, high-precision duty cycle adjustment can be achieved.

[0088] In addition, in this embodiment, the power supply voltage of the oscillation circuit can also be a voltage higher than the power supply voltage of the waveform shaping circuit.

[0089] This allows the amplitude of the oscillation signal input to the waveform shaping circuit to be as large as possible within the driving voltage range of the waveform shaping circuit, and makes the waveform of the shaped signal steeper, thus reducing the deviation of the duty cycle.

[0090] Alternatively, in this embodiment, the duty cycle adjustment circuit may also include: a voltage divider circuit having multiple resistors connected in series between the power supply node and the ground node, outputting multiple divided voltages obtained by voltage division by the multiple resistors; and a selection circuit that selects any one of the multiple divided voltages as a bias voltage.

[0091] In this way, multiple voltage dividers are generated between the power supply voltage and ground through the voltage divider circuit. The voltage corresponding to the adjustment data is selected from the multiple generated voltage dividers, thereby generating the bias voltage corresponding to the adjustment data.

[0092] In addition, in this embodiment, the oscillation circuit may include: a fixed capacitor, one end of which is connected to the first node and has a fixed capacitance value; and a variable capacitor element, one end of which is connected to the other end of the fixed capacitor and has a variable capacitance value, wherein a temperature compensation voltage is input to one end of the variable capacitor element and the other end is input to the other end, and a reference voltage is input to the other end.

[0093] In this way, by using a temperature compensation voltage based on a reference voltage to change the capacitance value of the variable capacitor element, temperature compensation of the oscillation frequency of the oscillation circuit can be achieved. Furthermore, by setting a fixed capacitor, the reference voltage and bias voltage can be adjusted independently, achieving temperature compensation and duty cycle adjustment of the oscillation signal.

[0094] In addition, in this embodiment, the duty cycle adjustment circuit can also output the bias voltage to the first node and output the reference voltage to the other.

[0095] Based on this structure, a bias voltage can be supplied using a duty cycle adjustment circuit to adjust the duty cycle of the clock signal, and a reference voltage for temperature compensation can also be supplied to achieve temperature compensation of the oscillation frequency.

[0096] In addition, in this embodiment, the duty cycle adjustment circuit may also include: a voltage divider circuit having multiple resistors connected in series between the power supply node and the ground node, outputting multiple voltage dividers obtained by voltage division by the multiple resistors; and a selection circuit that selects a first voltage divider, which is any one of the multiple voltage dividers, as a bias voltage, and selects a second voltage divider, which is any one of the multiple voltage dividers, as a reference voltage.

[0097] In this way, by supplying the first voltage divider selected from multiple voltage dividers as the bias voltage, the duty cycle of the clock signal can be adjusted, and by supplying the second voltage divider selected from multiple voltage dividers as the reference voltage, temperature compensation of the oscillation frequency can be achieved.

[0098] Alternatively, in this embodiment, when the temperature compensation voltage is set to VCMP and the reference voltage is set to VREF, the duty cycle adjustment circuit supplies a reference voltage greater than 0V to VCMP-VREF.

[0099] In this way, by applying a voltage greater than 0V, VCMP-VREF, to the variable capacitor element, the capacitance of the variable capacitor element changes variablely according to the temperature compensation voltage, thus enabling the realization of oscillators with temperature compensation functions.

[0100] Alternatively, in this embodiment, when the temperature compensation voltage is set to VCMP and the reference voltage is set to VREF, the duty cycle adjustment circuit supplies a reference voltage of 0V or less to VCMP-VREF.

[0101] In this way, by applying a voltage below 0V, VCMP-VREF, to the variable capacitor element, an oscillator without temperature compensation function can be realized.

[0102] Alternatively, this embodiment may include an output buffer circuit that buffers the clock signal and outputs the output clock signal to the outside.

[0103] In this way, even under a large external load, the output clock signal of the appropriate drive waveform can be supplied to the external load for driving.

[0104] Furthermore, this embodiment relates to an oscillator that includes the aforementioned circuitry and oscillator.

[0105] Furthermore, while this embodiment has been described in detail above, those skilled in the art should readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of circuit devices, oscillators, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, Include: An oscillating circuit is electrically connected to a first node electrically connected to one end of the oscillator and a second node electrically connected to the other end of the oscillator, and generates an oscillating signal by causing the oscillator to oscillate; A waveform shaping circuit is connected to the first node, receives the oscillation signal from the first node, and outputs a clock signal obtained by waveform shaping of the oscillation signal; as well as A duty cycle adjustment circuit supplies a bias voltage, which is variably adjusted according to adjustment data, to the first node, thereby adjusting the duty cycle of the clock signal. The oscillation circuit includes: A fixed capacitor, one end of which is connected to the first node, has a fixed capacitance value; and A variable capacitor element, one end of which is connected to the other end of the fixed capacitor, has a variable capacitance value. A temperature compensation voltage is input to one of the two ends of the variable capacitor element. The duty cycle adjustment circuit outputs a reference voltage to one end of the variable capacitor element and the other end of the variable capacitor element.

2. The circuit device according to claim 1, characterized in that, The duty cycle adjustment circuit includes: A voltage divider circuit has multiple resistors connected in series between a power node and a ground node, and outputs multiple voltage dividers obtained by dividing the voltages by the multiple resistors. as well as The selection circuit selects the first voltage divider, which is any one of the plurality of voltage dividers, as the bias voltage, and selects the second voltage divider, which is any one of the plurality of voltage dividers, as the reference voltage. When the temperature compensation voltage is set to VCMP and the reference voltage is set to VREF, the plurality of voltage dividers include voltages where VCMP-VREF is greater than 0V and voltages where VCMP-VREF is less than 0V.

3. The circuit device according to claim 1 or 2, characterized in that, The circuit device includes a non-volatile memory for storing the adjustment data. The duty cycle adjustment circuit generates a bias voltage based on the adjustment data stored in the non-volatile memory.

4. The circuit device according to claim 1 or 2, characterized in that, The power supply voltage of the oscillation circuit is a voltage higher than the power supply voltage of the waveform shaping circuit.

5. The circuit device according to claim 2, characterized in that, The duty cycle adjustment circuit supplies the reference voltage VCMP-VREF to be greater than 0V.

6. The circuit device according to claim 2, characterized in that, The duty cycle adjustment circuit supplies the reference voltage VCMP-VREF to be below 0V.

7. The circuit device according to claim 1 or 2, characterized in that, The circuit device includes an output buffer circuit that buffers the clock signal and outputs the clock signal to an external source.

8. An oscillator, characterized in that, The oscillator contains: The circuit device according to any one of claims 1 to 7; and The oscillator.

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