Comparator circuit and chip containing the same
By setting up input pairs of multiple interconnected PMOS tubes and NMOS tubes in the amplification circuit of the comparator circuit, the problem of small input voltage range in the comparator circuit in the prior art is solved, and the input voltage range is expanded and the accuracy is achieved. Improvement.
Patent Information
- Application Number
- CN202011573639.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-25
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2040-12-25
AI Technical Summary
The existing comparator circuit is connected to a transistor, resulting in a small input voltage range, and it is impossible to effectively compare the input voltage smaller than the transistor threshold voltage.
A comparator circuit is designed, using a combination of an amplifier circuit and a comparison circuit. By setting up a plurality of input pairs in the amplifier circuit, each input pair includes an interconnected PMOS tube and an NMOS tube, ensuring regardless of the value of the input voltage. How, there is always a transistor that conducts, thus expanding the input voltage range.
The input voltage range of the comparator circuit can be low to zero, the input voltage range of the comparator circuit is expanded, and the input voltage signal is amplified through gain amplification, thereby improving the accuracy of the comparator circuit.
Smart Images
Figure CN114696802B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a comparator circuit and a chip comprising the same. Background Art
[0002] The comparator circuit is an important module of the integrated circuit system and is widely used in various integrated circuit systems. In the existing comparator circuit, the input voltage of the comparator circuit is connected to a transistor. The input voltage of the comparator circuit must be greater than the threshold voltage of the transistor for the comparator circuit to output the comparison result normally. Therefore, the minimum value of the input voltage of the comparator circuit must be greater than the threshold voltage of the transistor. The input voltage less than the threshold voltage of the transistor cannot be compared, resulting in a smaller input voltage range of the comparator circuit. Summary of the invention
[0003] The technical problem to be solved by the present invention is to overcome the defect in the prior art that a comparator circuit is connected to a transistor, resulting in a smaller input voltage range of the comparator circuit, and provide a comparator circuit and a chip containing the same.
[0004] The present invention solves the above technical problems through the following technical solutions:
[0005] A comparator circuit comprises: an amplifier circuit and a comparison circuit;
[0006] The amplifier circuit includes a first input pair of transistors, a second input pair of transistors, a third input pair of transistors, a fourth input pair of transistors, a first amplifier sub-circuit and a second amplifier sub-circuit;
[0007] The first input pair of transistors, the second input pair of transistors, the third input pair of transistors and the fourth input pair of transistors each include a PMOS transistor and an NMOS transistor with gates connected to each other;
[0008] The gates of the NMOS tubes in the first input pair and the fourth input pair are used to connect to a first input voltage and output the first input voltage to the first amplifying sub-circuit and the second amplifying sub-circuit respectively, and the gates of the NMOS tubes in the second input pair and the third input pair are used to connect to a second input voltage and output the second input voltage to the first amplifying sub-circuit and the second amplifying sub-circuit respectively;
[0009] The first amplifying sub-circuit is used to perform gain amplification on the differential voltage between the first input voltage and the second input voltage and output a first amplified voltage;
[0010] The second amplifying sub-circuit is used to perform gain amplification on the differential voltage between the first input voltage and the second input voltage and output a second amplified voltage;
[0011] The comparison circuit is used for comparing the first amplified voltage with the second amplified voltage to obtain a comparison result corresponding to the first input voltage and the second input voltage.
[0012] Preferably, the first input pair of transistors includes a first PMOS transistor and a first NMOS transistor;
[0013] The second input pair of transistors includes a second PMOS transistor and a second NMOS transistor;
[0014] The first amplifying sub-circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first switch and a second switch;
[0015] The gate of the first NMOS tube is used to connect to the first input voltage, the gate of the second NMOS tube is used to connect to the second input voltage, the source of the first NMOS tube is connected to the source of the second NMOS tube and the drain of the third NMOS tube, and the drain of the first NMOS tube is connected to the drain of the fourth PMOS tube, the source of the sixth PMOS tube and the drain of the eighth PMOS tube;
[0016] The source of the first PMOS tube is connected to the source of the second PMOS tube and the drain of the third PMOS tube, and the drain of the first PMOS tube is connected to the drain of the fourth NMOS tube and the source of the sixth NMOS tube;
[0017] The drain of the second NMOS tube is connected to the source of the seventh PMOS tube, the drain of the ninth PMOS tube and the drain of the fifth PMOS tube;
[0018] The drain of the second PMOS tube is connected to the drain of the fifth NMOS tube and the source of the seventh NMOS tube;
[0019] The source of the third NMOS tube, the source of the fourth NMOS tube and the source of the fifth NMOS tube are all grounded, the gate of the third NMOS tube is connected to the fixed end of the second switch, and the movable end of the second switch is selectively connected to the external bias voltage or the ground according to the selection signal;
[0020] The gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the sixth NMOS tube and the drain of the sixth PMOS tube;
[0021] The gate of the sixth NMOS tube and the gate of the seventh NMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are all connected to an external bias voltage;
[0022] The drain of the seventh NMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the seventh NMOS tube is used to output the first amplified voltage;
[0023] The gate of the third PMOS tube, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube are all connected to an external bias voltage, and the source of the third PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are all connected to a power supply voltage;
[0024] The gate of the fourth PMOS tube and the gate of the fifth PMOS tube are both connected to the fixed end of the first switch, and the movable end of the first switch selects to connect to the external bias voltage or the power supply voltage based on the selection signal.
[0025] Preferably, the third input pair of transistors comprises: an eighth NMOS transistor and a seventeenth PMOS transistor;
[0026] The fourth input pair of transistors includes: a ninth NMOS transistor and an eighteenth PMOS transistor;
[0027] The second amplifying sub-circuit includes: a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube;
[0028] The gate of the eighth NMOS tube is connected to the second input voltage, the gate of the ninth NMOS tube is connected to the first input voltage, the source of the eighth NMOS tube is connected to the source of the ninth NMOS tube and the drain of the tenth NMOS tube, and the drain of the eighth NMOS tube is connected to the drain of the eleventh PMOS tube, the source of the thirteenth PMOS tube and the drain of the fifteenth PMOS tube;
[0029] The source of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube and the drain of the tenth PMOS tube, and the drain of the seventeenth PMOS tube is connected to the drain of the eleventh NMOS tube and the source of the thirteenth NMOS tube;
[0030] The drain of the ninth NMOS tube is connected to the source of the fourteenth PMOS tube, the drain of the sixteenth PMOS tube and the drain of the twelfth PMOS tube;
[0031] The drain of the eighteenth PMOS tube is connected to the drain of the twelfth NMOS tube and the source of the fourteenth NMOS tube;
[0032] The source of the tenth NMOS tube, the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are all grounded, and the gate of the tenth NMOS tube is connected to an external bias voltage;
[0033] The gate of the eleventh NMOS tube is connected to the gate of the twelfth NMOS tube, the drain of the thirteenth NMOS tube and the drain of the thirteenth PMOS tube;
[0034] The gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube, the gate of the thirteenth PMOS tube and the gate of the fourteenth PMOS tube are all connected to an external bias voltage;
[0035] The drain of the fourteenth NMOS tube is connected to the drain of the fourteenth PMOS tube, and the drain of the fourteenth NMOS tube is used to output the second amplified voltage;
[0036] The gate of the tenth PMOS tube, the gate of the fifteenth PMOS tube and the gate of the sixteenth PMOS tube are all connected to an external bias voltage, and the source of the tenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube are all connected to a power supply voltage;
[0037] The gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are both connected to an external bias voltage;
[0038] The gate of the tenth NMOS tube and the gate of the third NMOS tube are connected to the same bias voltage;
[0039] The gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are connected to the same bias voltage.
[0040] Preferably, the first input pair of transistors, the second input pair of transistors and the first amplifying sub-circuit form a first amplifying part;
[0041] The third input pair of transistors, the fourth input pair of transistors and the second amplifying sub-circuit constitute a second amplifying part;
[0042] The first amplifying part and the second amplifying part form a folded cascode structure.
[0043] Preferably, the comparison circuit comprises:
[0044] A thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube and a first inverter;
[0045] The gate of the thirty-fifth NMOS tube is connected to an external clock, the source of the thirty-fifth NMOS tube is grounded, the drain of the thirty-fifth NMOS tube is respectively connected to the source of the thirty-third NMOS tube and the source of the thirty-fourth NMOS tube, the gate of the thirty-third NMOS tube is connected to the second amplified voltage, the gate of the thirty-fourth NMOS tube is connected to the first amplified voltage, the drain of the thirty-third NMOS tube is connected to the source of the thirty-first NMOS tube, the drain of the thirty-fourth NMOS tube is connected to the source of the thirty-second NMOS tube, the thirty-first PMOS tube, the thirty-second PMOS tube, the thirty-third PMOS tube and the thirty-third NMOS tube are connected to the source of the thirty-third NMOS tube. The sources of the thirty-fourth PMOS tube are all connected to the power supply voltage, the gates of the thirty-first PMOS tube and the thirty-fourth PMOS tube are all connected to the external clock, the drain of the thirty-first PMOS tube is respectively connected to the drain of the thirty-second PMOS tube, the drain of the thirty-first NMOS tube, the gate of the thirty-second NMOS tube and the gate of the thirty-third PMOS tube, the gate of the thirty-second PMOS tube is respectively connected to the gate of the thirty-first NMOS tube, the drain of the thirty-third PMOS tube, the drain of the thirty-second NMOS tube and the input end of the first inverter, and the drain of the thirty-fourth PMOS tube is connected to the input end of the first inverter;
[0046] The output terminal of the first inverter is used to output the comparison result.
[0047] Preferably, the comparator circuit further comprises a selection signal generating circuit;
[0048] A first input terminal of the selection signal generating circuit is connected to a common mode voltage of the first input voltage and the second input voltage, and a second input terminal of the selection signal generating circuit is connected to a fixed voltage;
[0049] The output end of the selection signal generating circuit is connected to the input end of the amplifying circuit;
[0050] The selection signal generating circuit is used for outputting the selection signal to the amplifying circuit.
[0051] Preferably, the selection signal generating circuit includes: a fifty-third NMOS tube, a fifty-fourth NMOS tube, a fifty-fifth NMOS tube, a fifty-sixth NMOS tube, a fifty-seventh NMOS tube, a fifty-eighth NMOS tube, a fifty-first PMOS tube, a fifty-second PMOS tube, a fifty-third PMOS tube, a fifty-fourth PMOS tube, a fifty-fifth PMOS tube, a fifty-sixth PMOS tube and a second inverter;
[0052] The gate of the fifty-third NMOS tube is connected to the common mode voltage, the gate of the fifty-fourth NMOS tube is connected to the fixed voltage, the sources of the fifty-third NMOS tube, the fifty-fourth NMOS tube, the fifty-fifth NMOS tube and the fifty-sixth NMOS tube are all grounded, the sources of the fifty-first PMOS tube, the fifty-second PMOS tube, the fifty-third PMOS tube, the fifty-fourth PMOS tube, the fifty-fifth PMOS tube and the fifty-sixth PMOS tube are all connected to the power supply voltage, the drain of the fifty-third NMOS tube is respectively connected to the drain of the fifty-first PMOS tube, the gate of the fifty-first PMOS tube, the drain of the fifty-second PMOS tube, the gate of the fifty-third PMOS tube and the gate of the fifty-sixth NMOS tube, and the fifty-third PMOS tube is connected to the gate of the fifty-fourth PMOS tube. The drain of the fourteenth NMOS tube is respectively connected to the drain of the fifty-fourth PMOS tube, the gate of the fifty-fourth PMOS tube, the drain of the fifty-third PMOS tube, and the gate of the fifty-second PMOS tube, the drain of the fifty-fifth NMOS tube is connected to the source of the fifty-seventh NMOS tube, the drain of the fifty-sixth NMOS tube is connected to the source of the fifty-eighth NMOS tube, the drain of the fifty-seventh NMOS tube is respectively connected to the drain of the fifty-fifth PMOS tube, the gate of the fifty-eighth NMOS tube, and the gate of the fifty-sixth PMOS tube, and the gate of the fifty-seventh NMOS tube is respectively connected to the gate of the fifty-fifth PMOS tube, the drain of the fifty-sixth PMOS tube, the drain of the fifty-eighth NMOS tube, and the input end of the second inverter;
[0053] The output terminal of the second inverter is used to output the selection signal.
[0054] Preferably, the selection signal generating circuit further includes: a fifty-first NMOS tube and a fifty-second NMOS tube;
[0055] The gate of the fifty-first NMOS tube and the gate of the fifty-second NMOS tube are connected to an external bias voltage, the source of the fifty-first NMOS tube and the source of the fifty-second NMOS tube are connected to the ground, the drain of the fifty-first NMOS tube is respectively connected to the source of the fifty-third NMOS tube and the fifty-fourth NMOS tube, and the drain of the fifty-second NMOS tube is respectively connected to the source of the fifty-fifth NMOS tube and the fifty-sixth NMOS tube.
[0056] Preferably, the value of the fixed voltage is greater than a threshold value of the NMOS transistor.
[0057] A chip comprises any one of the comparator circuits described above.
[0058] The positive and progressive effect of the present invention is that: the present invention arranges a first input pair of tubes, a second input pair of tubes, a third input pair of tubes, and a fourth input pair of tubes in an amplifier circuit, and the first input pair of tubes, the second input pair of tubes, the third input pair of tubes, and the fourth input pair of tubes all include a PMOS tube and an NMOS tube whose gates are connected to each other, and the gates of the PMOS tubes and the NMOS tubes in the first input pair of tubes and the fourth input pair of tubes are both connected to a first input voltage, and the gates of the PMOS tubes and the NMOS tubes in the second input pair of tubes and the third input pair of tubes are both connected to a second input voltage. No matter what the voltage value of the comparator input is, it can always be ensured that one transistor in the input pair of tubes is turned on, so that the input voltage range of the comparator circuit can be as low as zero, thereby expanding the input voltage range of the comparator circuit, and at the same time, the first amplifying sub-circuit and the second amplifying sub-circuit perform gain amplification on the input voltage signal, thereby improving the accuracy of the comparator circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0059] Figure 1 Schematic diagram of the structure of the comparator circuit of embodiment 1 of the present invention.
[0060] Figure 2 4 is a circuit diagram of an amplifier circuit according to Embodiment 2 of the present invention.
[0061] Figure 3 4 is a circuit diagram of a comparison circuit according to Embodiment 2 of the present invention.
[0062] Figure 4 FIG. 4 is a circuit diagram of a selection signal generating circuit according to Embodiment 2 of the present invention. DETAILED DESCRIPTION
[0063] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.
[0064] Example 1
[0065] This embodiment provides a comparator circuit, such as Figure 1 As shown, it includes: an amplifier circuit 1 and a comparison circuit 2.
[0066] The amplifier circuit 1 comprises a first input pair of transistors 11 , a second input pair of transistors 12 , a third input pair of transistors 13 , a fourth input pair of transistors 14 , a first amplifier sub-circuit 15 and a second amplifier sub-circuit 16 .
[0067] The first input pair of transistors 11 , the second input pair of transistors 12 , the third input pair of transistors 13 and the fourth input pair of transistors 14 each include a PMOS transistor and an NMOS transistor whose gates are connected to each other.
[0068] The output end of the first input pair tube 11 is connected to the first input end of the first amplifier sub-circuit 15, the output end of the second input pair tube 12 is connected to the second input end of the first amplifier sub-circuit 15, the output end of the third input pair tube 13 is connected to the first input end of the second amplifier sub-circuit 16, the output end of the fourth input pair tube 14 is connected to the second input end of the second amplifier sub-circuit 16, the output end of the first amplifier sub-circuit 15 is connected to the first input end of the comparison circuit 2, and the output end of the second amplifier sub-circuit 16 is connected to the second input end of the comparison circuit 2.
[0069] The gates of the PMOS transistors and the NMOS transistors in the first input pair 11 and the fourth input pair 14 are both used to connect to the first input voltage inp, and the gates of the PMOS transistors and the NMOS transistors in the second input pair 12 and the third input pair 13 are both used to connect to the second input voltage inn;
[0070] The first input pair transistor 11 and the fourth input pair transistor 14 are used to turn on the PMOS transistor and output the first input voltage inp to the first amplifier sub-circuit 15 and the second amplifier sub-circuit 16 respectively when the first input voltage inp is lower than the NMOS transistor threshold, and turn on the NMOS transistor and output the first input voltage inp to the first amplifier sub-circuit 15 and the second amplifier sub-circuit 16 respectively when the first input voltage inp is higher than the NMOS transistor threshold;
[0071] The second input pair of transistors 12 and the third input pair of transistors 13 are used to turn on the PMOS transistor and output the second input voltage inn to the first amplifying sub-circuit 15 and the second amplifying sub-circuit 16 respectively when the second input voltage inn is lower than the NMOS transistor threshold, and to turn on the NMOS transistor and output the second input voltage inn to the first amplifying sub-circuit 15 and the second amplifying sub-circuit 16 respectively when the second input voltage inn is higher than the NMOS transistor threshold;
[0072] The first amplifier sub-circuit 15 is used to perform gain amplification on the differential voltage between the first input voltage inp and the second input voltage inn and output a first amplified voltage op_outp;
[0073] The second amplifying sub-circuit is used for performing gain amplification on the differential voltage between the first input voltage inp and the second input voltage inn and outputting a second amplified voltage op_outn;
[0074] The comparison circuit 2 is used for comparing the first amplified voltage op_outp with the second amplified voltage op_outn to obtain a comparison result cmpout corresponding to the first input voltage inp and the second input voltage inn.
[0075] The comparison amplifier circuit of this embodiment is provided with a first input pair of transistors, a second input pair of transistors, a third input pair of transistors and a fourth input pair of transistors composed of PMOS transistors and NMOS transistors whose gates are connected to each other at the input end. No matter what the values of the first input voltage and the second input voltage are, there is always a transistor that can be turned on, so that the input voltage range of the comparator can be (0, Vdd), where Vdd is the power supply voltage, thereby expanding the input voltage range of the comparator circuit. At the same time, the comparator circuit can improve the accuracy of the comparator circuit because it uses the first amplifier sub-circuit and the second amplifier sub-circuit for gain amplification.
[0076] Example 2
[0077] A comparator circuit provided in this embodiment is a further improvement on embodiment 1. Figure 2 As shown, the amplifier circuit 1 in the comparator circuit of this embodiment includes a first amplifier part 101 and a second amplifier part 102. The first amplifier part 101 includes a first input pair of transistors 11, a second input pair of transistors 12 and a first amplifier sub-circuit 15. The second amplifier part 102 includes a third input pair of transistors 13, a fourth input pair of transistors 14 and a second amplifier sub-circuit 16.
[0078] The first input pair of transistors 11 includes a first PMOS transistor Mp1 and a first NMOS transistor Mn1.
[0079] The second input pair of transistors 12 includes a second PMOS transistor Mp2 and a second NMOS transistor Mn2.
[0080] The first amplifying sub-circuit 15 includes a third NMOS transistor Mn3, a fourth NMOS transistor Mn4, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a seventh NMOS transistor Mn7, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a fifth PMOS transistor Mp5, a sixth PMOS transistor Mp6, a seventh PMOS transistor Mp7, an eighth PMOS transistor Mp8, a ninth PMOS transistor M9, a first switch K1 and a second switch K2.
[0081] The gate of the first NMOS tube Mn1 is used to connect the first input voltage inp, the gate of the second NMOS tube Mn2 is used to connect the second input voltage inn, the source of the first NMOS tube Mn1 is connected to the source of the second NMOS tube Mn2 and the drain of the third NMOS tube Mn3, and the drain of the first NMOS tube Mn1 is connected to the drain of the fourth PMOS tube Mp4, the source of the sixth PMOS tube Mp6 and the drain of the eighth PMOS tube Mp8.
[0082] The source of the first PMOS transistor Mp1 is connected to the source of the second PMOS transistor Mp2 and the drain of the third PMOS transistor Mp3 , and the drain of the first PMOS transistor Mp1 is connected to the drain of the fourth NMOS transistor Mn4 and the source of the sixth NMOS transistor Mn6 .
[0083] The drain of the second NMOS tube Mn2 is connected to the source of the seventh PMOS tube Mp7, the drain of the ninth PMOS tube Mp9 and the drain of the fifth PMOS tube Mp5.
[0084] The drain of the second PMOS transistor Mp2 is connected to the drain of the fifth NMOS transistor Mn5 and the source of the seventh NMOS transistor Mn7.
[0085] The source of the third NMOS transistor Mn3, the source of the fourth NMOS transistor Mn4 and the source of the fifth NMOS transistor Mn5 are all connected to the ground Vss, the gate of the third NMOS transistor Mn3 is connected to the fixed end of the second switch K2, the movable end of the second switch K2 is connected to the bias voltage vbnc, and the bias voltage vbnc is selected to be connected to the external bias voltage vbn or the ground Vss according to the selection signal Sw_ctl.
[0086] The gate of the fourth NMOS transistor Mn4 is connected to the gate of the fifth NMOS transistor Mn5, the drain of the sixth NMOS transistor Mn6, and the drain of the sixth PMOS transistor Mp6.
[0087] The gate of the sixth NMOS transistor Mn6 and the gate of the seventh NMOS transistor Mn7 are both connected to the external bias voltage vbncs, and the gate of the sixth PMOS transistor Mp6 and the gate of the seventh PMOS transistor Mp7 are both connected to the external bias voltage vbpcs.
[0088] The drain of the seventh NMOS transistor Mn7 is connected to the drain of the seventh PMOS transistor Mp7 , and the drain of the seventh NMOS transistor Mn7 is used to output the first amplified voltage op_outp.
[0089] The gate of the third PMOS tube Mp3, the gate of the eighth PMOS tube Mp8 and the gate of the ninth PMOS tube Mp9 are all connected to the external bias voltage vbp, and the source of the third PMOS tube Mp3, the source of the eighth PMOS tube Mp8 and the source of the ninth PMOS tube Mp9 are all connected to the power supply voltage Vdd.
[0090] The gates of the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 are both connected to the fixed end of the first switch K1. The movable end of the first switch K1 is connected to the bias voltage vbpc. The bias voltage vbpc selects to connect to the external bias voltage vbp or the power supply voltage Vdd based on the selection signal Sw_ctl.
[0091] In this embodiment, the first input pair 11 and the second input pair 12 use both NMOS and PMOS transistors to ensure that the first input pair 11 and the second input pair 12 can always be turned on regardless of the first input voltage inp and the second input voltage inn of the comparator circuit. The first switch K1 is used to control the gate of the fourth PMOS transistor Mp4 and the gate of the fifth PMOS transistor Mp5 to connect to the bias voltage vbp or the power supply voltage Vdd based on the selection signal Sw_ctl, and the second switch K2 is used to control the gate of the third NMOS transistor to connect to the bias voltage vbn or the ground Vss based on the selection signal Sw_ctl.
[0092] When the input voltage of the comparator is high, for example: the first input voltage inp=2v, the second input voltage inn=2v, and the selection signal Sw_ctl=0, the first NMOS tube Mn1 and the second NMOS tube Mn2 are turned on, the movable terminal bias voltage vpb of the first switch K1 turns on the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5, and the movable terminal bias voltage vpn of the second switch K2 turns on the third NMOS tube Mn3. At this time, the current of the third transistor Mn3 is turned on, and the current of the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 is also turned on. The sixth NMOS tube Mn6 and the seventh NMOS tube Mn7 are both connected to the external bias voltage vbncs and turned on, the sixth PMOS tube Mp6 and the seventh PMOS tube Mp7 are both connected to the external bias voltage vbpcs and turned on, and the drain of the seventh NMOS tube Mn7 outputs the amplified first amplified voltage op_outp.
[0093] When the input voltage of the comparator is low, for example: the first input voltage inp=0.2v, the second input voltage inn=0.2v, when the selection signal Sw_ctl=1, the first NMOS tube Mn1 and the second NMOS tube Mn2 are turned off, the gate of the third PMOS tube Mp3, the gate of the eighth PMOS tube Mp8 and the gate of the ninth PMOS tube Mp9 are connected to the bias voltage vbp and turned on, the first PMOS tube Mp1 and the second PMOS tube Mp2 are turned on, the movable end of the first switch K1 is connected to the power supply voltage Vdd to turn off the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5, the movable end of the second switch K2 is connected to the ground Vss to turn off the third transistor Mn3, at this time the current of the third transistor Mn3 is turned off, and the current of the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 is also turned off. The sixth NMOS tube Mn6 and the seventh NMOS tube Mn7 are both connected to the external bias voltage vbncs and turned on, the sixth PMOS tube Mp6 and the seventh PMOS tube Mp7 are both connected to the external bias voltage vbpcs and turned on, and the drain of the seventh NMOS tube Mn7 outputs the amplified first amplified voltage op_outp.
[0094] The circuit of the first amplifying part 101 of the present embodiment ensures that the cascode tube current of the common source and common gate stage is independent of the first input level inp or the second input voltage inn of the amplifier 1, that is, whether the input pair tube is turned on or off, the working state of the cascode tube remains unchanged, thereby ensuring the gain of the amplifier 1 and reducing the design difficulty. The cascode tube is composed of a sixth NMOS tube Mn6, a seventh NMOS tube Mn7, a sixth PMOS tube Mp6, and a seventh PMOS tube Mp7.
[0095] The third input pair of transistors 13 in the second amplifying part 102 of this embodiment includes: an eighth NMOS transistor Mn8 and a seventeenth PMOS transistor Mp17;
[0096] The fourth input pair of transistors 14 includes: a ninth NMOS transistor Mn9 and an eighteenth PMOS transistor Mp18;
[0097] The second amplifying sub-circuit 16 includes: a tenth NMOS tube Mn10, an eleventh NMOS tube Mn11, a twelfth NMOS tube Mn12, a thirteenth NMOS tube Mn13, a fourteenth NMOS tube Mn14, a tenth PMOS tube Mp10, an eleventh PMOS tube Mp11, a twelfth PMOS tube Mp12, a thirteenth PMOS tube Mp13, a fourteenth PMOS tube Mp14, a fifteenth PMOS tube Mp15 and a sixteenth PMOS tube Mp16;
[0098] The gate of the eighth NMOS tube Mn8 is connected to the second input voltage inn, the gate of the ninth NMOS tube Mn9 is connected to the first input voltage inp, the source of the eighth NMOS tube Mn8 is connected to the source of the ninth NMOS tube Mn9 and the drain of the tenth NMOS tube Mn10, and the drain of the eighth NMOS tube Mn8 is connected to the drain of the eleventh PMOS tube Mp11, the source of the thirteenth PMOS tube Mp13 and the drain of the fifteenth PMOS tube Mp15;
[0099] The source of the seventeenth PMOS tube Mp17 is connected to the source of the eighteenth PMOS tube Mp18 and the drain of the tenth PMOS tube Mp10, and the drain of the seventeenth PMOS tube Mp17 is connected to the drain of the eleventh NMOS tube Mn11 and the source of the thirteenth NMOS tube Mn13;
[0100] The drain of the ninth NMOS tube Mn9 is connected to the source of the fourteenth PMOS tube Mp14, the drain of the sixteenth PMOS tube Mp16 and the drain of the twelfth PMOS tube Mp12;
[0101] The drain of the eighteenth PMOS tube Mp18 is connected to the drain of the twelfth NMOS tube Mn12 and the source of the fourteenth NMOS tube Mn14;
[0102] The source of the tenth NMOS tube Mn10, the source of the eleventh NMOS tube Mn11 and the source of the twelfth NMOS tube Mn12 are all connected to the ground Vss, and the gate of the tenth NMOS tube Mn10 is connected to the external bias voltage vbnc;
[0103] The gate of the eleventh NMOS transistor Mn11 is connected to the gate of the twelfth NMOS transistor Mn12, the drain of the thirteenth NMOS transistor Mn13, and the drain of the thirteenth PMOS transistor Mp13.
[0104] The gate of the thirteenth NMOS tube Mn13 and the gate of the fourteenth NMOS tube Mn14 are connected to the external bias voltage vbncs, and the gate of the thirteenth PMOS tube Mp13 and the gate of the fourteenth PMOS tube Mp14 are both connected to the external bias voltage vbpcs.
[0105] The drain of the fourteenth NMOS tube Mn14 is connected to the drain of the fourteenth PMOS tube Mp14, and the drain of the fourteenth NMOS tube Mn14 is used to output the second amplified voltage op_outn.
[0106] The gate of the tenth PMOS tube Mp10, the gate of the fifteenth PMOS tube Mp15 and the gate of the sixteenth PMOS tube Mp16 are all connected to the external bias voltage vbp, and the source of the tenth PMOS tube Mp10, the source of the fifteenth PMOS tube Mp15 and the source of the sixteenth PMOS tube Mp16 are all connected to the power supply voltage Vdd.
[0107] The gate of the eleventh PMOS tube Mp11 and the gate of the twelfth PMOS tube Mp12 are both connected to the external bias voltage vbpc;
[0108] The gate of the tenth NMOS transistor Mn10 and the gate of the third NMOS transistor Mn3 are connected to the same bias voltage vbnc;
[0109] The gate of the fourth PMOS transistor Mp4 , the gate of the fifth PMOS transistor Mp5 , the gate of the eleventh PMOS transistor Mp11 , and the gate of the twelfth PMOS transistor Mp12 are connected to the same bias voltage vbpc.
[0110] In this embodiment, the third input pair transistor 13 and the fourth input pair transistor 14 use both NMOS transistors and PMOS transistors to ensure that the third input pair transistor 13 and the fourth input pair transistor 14 can always be turned on regardless of the first input voltage inp and the second input voltage inn of the comparator circuit. When the input voltage of the comparator is high, for example: the first input voltage inp=2v, the second input voltage inn=2v, the eighth NMOS tube Mn8 and the ninth NMOS tube Mn9 are turned on, the gate of the tenth PMOS tube Mp10, the gate of the fifteenth PMOS tube Mp15 and the gate of the sixteenth PMOS tube Mp16 are all connected to the bias voltage vbp and turned on, the gate of the eleventh PMOS tube Mp11 and the gate of the twelfth PMOS tube Mp12 are connected to the bias voltage vbpc connected to the bias voltage vbp, so the eleventh PMOS tube Mp11 and the twelfth PMOS tube Mp12 are turned on, the gate of the tenth NMOS tube Mn10 is connected to the bias voltage vbnc connected to the bias voltage vbn, so the tenth NMOS tube Mn10 is turned on, at this time, the current of the tenth transistor Mn10 is turned on, and the current of the eleventh PMOS tube Mp11 and the twelfth PMOS tube Mp12 are also turned on. The thirteenth NMOS tube Mn13 and the fourteenth NMOS tube Mn4 are both connected to the external bias voltage vbncs and turned on, the thirteenth PMOS tube Mp13 and the fourteenth PMOS tube Mp14 are both connected to the external bias voltage vbpcs and turned on, and the drain of the fourteenth NMOS tube Mn14 outputs the amplified second amplified voltage op_outn.
[0111] When the input voltage of the comparator is low, for example: the first input voltage inp=0.2v, the second input voltage inn=0.2v, the eighth NMOS tube Mn8 and the ninth NMOS tube Mn9 are turned off, the seventeenth PMOS tube Mp17 and the eighteenth PMOS tube Mp18 are turned on, the gate of the tenth PMOS tube Mp10, the gate of the fifteenth PMOS tube Mp15 and the gate of the sixteenth PMOS tube Mp16 are all connected to the bias voltage vbp and turned on, and the eleventh PMOS tube Mp11 The bias voltage vbpc connected to the gate of the twelfth PMOS tube Mp12 is connected to the power supply voltage Vdd, so the eleventh PMOS tube Mp11 and the twelfth PMOS tube Mp12 are turned off, and the bias voltage vbnc connected to the gate of the tenth NMOS tube Mn10 is connected to the ground Vss, so the tenth NMOS tube Mn10 is turned off. At this time, the current of the tenth transistor Mn10 is turned off, and the current of the eleventh PMOS tube Mp11 and the twelfth PMOS tube Mp12 is also turned off. The thirteenth NMOS tube Mn13 and the fourteenth NMOS tube Mn4 are both connected to the external bias voltage vbncs and turned on, the thirteenth PMOS tube Mp13 and the fourteenth PMOS tube Mp14 are both connected to the external bias voltage vbpcs and turned on, and the drain of the fourteenth NMOS tube Mn14 outputs the amplified second amplified voltage op_outn.
[0112] The circuit of the second amplifying part 102 of the present embodiment ensures that the cascode tube current of the common source and common gate stage is independent of the first input level inp or the second input voltage inn of the amplifier 1, that is, whether the input pair tube is turned on or off, the working state of the cascode tube remains unchanged, thereby ensuring the gain of the amplifier 1 and reducing the design difficulty. The cascode tube is composed of a thirteenth NMOS tube Mn13, a fourteenth NMOS tube Mn14, a thirteenth PMOS tube Mp13, and a fourteenth PMOS tube Mp14.
[0113] In the amplifier circuit of this embodiment, the first amplifying part 101 and the second amplifying part 102 form a folded common source and common gate structure, so that the amplifier circuit 1 can obtain a larger gain.
[0114] like Figure 3 As shown, the comparison circuit 2 of this embodiment includes: a thirty-first NMOS tube Mn31, a thirty-second NMOS tube Mn32, a thirty-third NMOS tube Mn33, a thirty-fourth NMOS tube Mn34, a thirty-fifth NMOS tube Mn35, a thirty-first PMOS tube Mp31, a thirty-second PMOS tube Mp32, a thirty-third PMOS tube Mp33, a thirty-fourth PMOS tube Mp34 and a first inverter Inv1;
[0115] The gate of the thirty-fifth NMOS tube Mn35 is connected to the external clock clk, the source of the thirty-fifth NMOS tube Mn35 is grounded Vss, the drain of the thirty-fifth NMOS tube Mn35 is respectively connected to the source of the thirty-third NMOS tube Mn33 and the source of the thirty-fourth NMOS tube Mn34, the gate of the thirty-third NMOS tube Mn33 is used to connect the second amplified voltage op_outn, the gate of the thirty-fourth NMOS tube Mn34 is used to connect the first amplified voltage op_outp, the drain of the thirty-third NMOS tube Mn33 is connected to the source of the thirty-first NMOS tube Mn31, the drain of the thirty-fourth NMOS tube Mn34 is connected to the source of the thirty-second NMOS tube Mn32, the thirty-first PMOS tube Mp31, the thirty-second PMOS tube Mp32, and the thirty-third PMOS tube Mp34 are connected to the source of the thirty-third NMOS tube Mn31. 3 and the thirty-fourth PMOS tube Mp34 are both connected to the power supply voltage Vdd, the gate of the thirty-first PMOS tube Mp31 and the gate of the thirty-fourth PMOS tube Mp34 are both connected to the external clock clk, the drain of the thirty-first PMOS tube Mp31 is respectively connected to the drain of the thirty-second PMOS tube Mp32, the drain of the thirty-first NMOS tube Mn31, the gate of the thirty-second NMOS tube Mn32 and the gate of the thirty-third PMOS tube Mp33, the gate of the thirty-second PMOS tube Mp32 is respectively connected to the gate of the thirty-first NMOS tube Mn31, the drain of the thirty-third PMOS tube Mp33, the drain of the thirty-second NMOS tube Mn32 and the input end of the first inverter Inv1, and the drain of the thirty-fourth PMOS tube Mp34 is connected to the input end of the first inverter Inv1;
[0116] The output terminal of the first inverter Inv1 is used to output the comparison result cmpout.
[0117] At the rising edge of the clock signal clk, the thirty-fifth NMOS tube Mn35, the thirty-first PMOS tube Mp31 and the thirty-fourth PMOS tube Mp34 are turned on, when the first input voltage inp is greater than the second input voltage inn, the corresponding comparison circuit's 2-input voltage first amplified voltage op_outp is greater than the second amplified voltage op_outn, the gate of the thirty-third NMOS tube Mn33 connected to the amplified second amplified voltage op_outn is turned on, the gate of the thirty-fourth NMOS tube Mn34 connected to the amplified first amplified voltage op_outp is turned on, the thirty-first NMOS tube Mn31, the thirty-second NMOS tube Mn32, the thirty-first PMOS tube Mp31, the thirty-second PMOS tube Mp32, the thirty-third PMOS tube Mp33 and the thirty-fourth PMOS tube Mp34 constitute a comparator, when the first amplified voltage op_outp is greater than the second amplified voltage op_outn, the value of the comparison result cmpout output by the first inverter Inv1 is 1. At the same time, at the rising edge of the clock signal clk, the first comparison circuit Cmp1 is also used to quickly latch the comparison result cmpout of the comparator circuit. When the clock signal clk=0, the first comparison circuit Cmp1 performs a reset operation.
[0118] Similarly, when the first input voltage inp is less than the second input voltage inn, the corresponding first amplified voltage op_outp of the comparison circuit is less than the second amplified voltage op_outn, and the comparison result cmpout output by the first inverter Inv1 has a value of 0.
[0119] In another optional implementation, the comparator circuit further includes a selection signal generating circuit; Figure 4 As shown, the first input terminal of the selection signal generating circuit is connected to the common mode voltage incm of the first input voltage inp and the second input voltage inn, and the second input terminal of the selection signal generating circuit is connected to the fixed voltage Vth_amp. The value of the fixed voltage Vth_amp is slightly larger than the threshold value of the NMOS transistor in the selection signal generating circuit so that when the average value of the first input voltage inp and the second input voltage inn is larger than the threshold value of the NMOS transistor, the corresponding transistor current is turned on. At this time, Vth_amp, as the selection signal Sw_ctl, should be equivalent to the threshold voltage of the NMOS transistor.
[0120] The output terminal of the selection signal generating circuit is connected to the input terminal of the amplifying circuit 1 .
[0121] The selection signal generating circuit is used for outputting the selection signal Sw_ctl to the amplifying circuit 1 .
[0122] The selection signal generating circuit of this embodiment includes: a fifty-first NMOS tube Mn51, a fifty-second NMOS tube Mn52, a fifty-third NMOS tube Mn53, a fifty-fourth NMOS tube Mn54, a fifty-fifth NMOS tube Mn55, a fifty-sixth NMOS tube Mn56, a fifty-seventh NMOS tube Mn57, a fifty-eighth NMOS tube Mn58, a fifty-first PMOS tube Mp51, a fifty-second PMOS tube Mp52, a fifty-third PMOS tube Mp53, a fifty-fourth PMOS tube Mp54, a fifty-fifth PMOS tube Mp55, a fifty-sixth PMOS tube Mp56 and a second inverter Inv2;
[0123] The gate of the fifty-first NMOS tube Mn51 and the gate of the fifty-second NMOS tube Mn52 are connected to the external bias voltage vbn, the source of the fifty-first NMOS tube Mn51 and the source of the fifty-second NMOS tube Mn52 are connected to the ground, the drain of the fifty-first NMOS tube Mn51 is connected to the source of the fifty-third NMOS tube Mn53 and the fifty-fourth NMOS tube Mn54, respectively, the drain of the fifty-second NMOS tube Mn52 is connected to the source of the fifty-fifth NMOS tube Mn55 and the fifty-sixth NMOS tube Mn56, respectively; the fifty-third NMOS tube Mn53 and the fifty-fourth NMOS tube Mn54 are connected to the drain of the fifty-second NMOS tube Mn52; The gate of the fifty-fourth NMOS tube Mn54 is connected to the common mode voltage incm, the gate of the fifty-first NMOS tube Mn54 is connected to the fixed voltage Vth_amp, the sources of the fifty-first PMOS tube Mp51, the fifty-second PMOS tube Mp52, the fifty-third PMOS tube Mp53, the fifty-fourth PMOS tube Mp54, the fifty-fifth PMOS tube Mp55 and the fifty-sixth PMOS tube Mp56 are all connected to the power supply voltage Vdd, and the drain of the fifty-third NMOS tube Mn53 is connected to the drain of the fifty-first PMOS tube Mp51, the gate of the fifty-first PMOS tube Mp51, the fifty-second PMOS tube Mp56, the fifty-third PMOS tube Mp57 and the fifty-third PMOS tube Mp58 respectively. The drain of the PMOS tube Mp52, the gate of the fifty-third PMOS tube Mp53 and the gate of the fifty-sixth NMOS tube Mn56 are all connected; the drain of the fifty-fourth NMOS tube Mn54 is respectively connected to the drain of the fifty-fourth PMOS tube Mp54, the gate of the fifty-fourth PMOS tube Mp54, the drain of the fifty-third PMOS tube Mp53 and the gate of the fifty-second PMOS tube Mp52; the drain of the fifty-fifth NMOS tube Mn55 is connected to the source of the fifty-seventh NMOS tube Mn57; the drain of the fifty-sixth NMOS tube Mn56 is connected to the source of the fifty-eighth NMOS tube Mn58; The source of the fifty-seventh NMOS tube Mn57 is connected to the drain of the fifty-fifth PMOS tube Mp55, the gate of the fifty-eighth NMOS tube Mn58 and the gate of the fifty-sixth PMOS tube Mp56 respectively, the gate of the fifty-seventh NMOS tube Mn57 is connected to the gate of the fifty-fifth PMOS tube Mp55, the drain of the fifty-sixth PMOS tube Mp56, the drain of the fifty-eighth NMOS tube Mn58 and the input end of the second inverter Inv2 respectively; the output end of the second inverter Inv2 is used to output the selection signal Sw_ctl.
[0124] In the selection signal generating circuit of this embodiment, the gate of the fifty-fourth NMOS tube Mn54 is connected to a fixed voltage Vth_amp, and the fixed voltage Vth_amp is close to and slightly greater than the threshold voltage of the NMOS tube, and the fifty-fourth NMOS tube Mn54 is always turned on. When the first input voltage inp and the second input voltage inn are low voltages, such as the first input voltage inp=0.2v, the second input voltage inn=0.2v, the common mode voltage incm=(inp+inn) / 2=0.2v, assuming that the threshold voltage of the NMOS tube is 0.5v, the selected value of Vth_amp is 0.55V. Since the common mode voltage incm is less than Vth_amp, at this time, the fifty-third NMOS tube Mn53 is turned off, and the fifty-first NMOS tube Mn51 and the fifty-second NMOS tube Mn52 are connected to the external bias voltage Vbn and turned on. Since the fifty-third NMOS tube Mn53 is turned off, the selection signal generating circuit outputs a high level signal as the selection signal Sw_ctl.
[0125] When the first input voltage inp and the second input voltage inn are high voltages, such as the first input voltage inp=2v, the second input voltage inn=2v, the common mode voltage incm=(inp+inn) / 2=2v, assuming that the threshold voltage of the NMOS tube is 0.5v, and the selected value of Vth_amp is 0.55V, since the common mode voltage incm is greater than Vth_amp, at this time, the fifty-third NMOS tube Mn53 is turned on, and the fifty-first NMOS tube Mn51 and the fifty-second NMOS tube Mn52 are connected to the external bias voltage Vbn and turned on. Since the fifty-third NMOS tube Mn53 is turned on, the selection signal generating circuit outputs a low level signal as the selection signal Sw_ctl.
[0126] The working principle of the comparator circuit of this embodiment is: when the first input voltage inp and the second input voltage inn are high voltages, the first NMOS transistor Mn1, the second NMOS transistor Mn2, the eighth NMOS transistor Mn8 and the ninth NMOS transistor Mn9 are turned on, the selection signal generating circuit outputs a low level signal as the selection signal Sw_ctl=0, the movable terminal bias voltage vpb of the first switch K1 in the amplifier circuit 1 turns on the fourth PMOS transistor Mp4, the fifth PMOS transistor Mp5, the eleventh PMOS transistor Mp11 and the twelfth PMOS transistor Mp12, the movable terminal bias voltage vpn of the second switch K2 turns on the third NMOS transistor Mn3 and the tenth NMOS transistor Mn10, the drain of the seventh NMOS transistor Mn7 outputs the amplified second amplified voltage op_outn, and the drain of the fourteenth NMOS transistor Mn14 outputs the amplified second amplified voltage op_outn.
[0127] When the first input voltage inp and the second input voltage inn are low voltages, the first PMOS tube Mp1, the second PMOS tube Mp2, the eighth PMOS tube Mp8 and the ninth PMOS tube Mp9 are turned on, the selection signal generating circuit outputs a high level signal as the selection signal Sw_ctl=1, the movable end of the first switch K1 is connected to the power supply voltage Vdd so that the fourth PMOS tube Mp4, the fifth PMOS tube Mp5, the eleventh PMOS tube Mp11 and the twelfth PMOS tube Mp12 are turned off, and the movable end of the second switch K2 is grounded to Vss so that the third transistor Mn3 and the tenth transistor Mn10 are turned off. The drain of the seventh NMOS tube Mn7 outputs the amplified first amplified voltage op_outp. The drain of the fourteenth NMOS tube Mn14 outputs the amplified second amplified voltage op_outn.
[0128] The comparator circuit of this embodiment generates a selection signal to the discharge circuit according to the common-mode voltage of the first input voltage and the second input voltage through the selection signal generating circuit, and controls the first switch and the second switch in the amplifier circuit to turn on the corresponding transistors, so that the cascode tube current of the common-source and common-gate stage in the amplifier circuit is independent of the first input level or the second input voltage of the amplifier, and the working state of the cascode tube remains unchanged, thereby ensuring the gain of the amplifier and reducing the design difficulty.
[0129] Example 3
[0130] This embodiment provides a chip, which includes the comparator circuit in Embodiment 1 or Embodiment 2.
[0131] The comparator amplifier circuit is provided with a first input pair of tubes, a second input pair of tubes, a third input pair of tubes and a fourth input pair of tubes in the amplifier circuit. The first input pair of tubes, the second input pair of tubes, the third input pair of tubes and the fourth input pair of tubes all include a PMOS tube and an NMOS tube whose gates are connected to each other. The gates of the PMOS tubes and the NMOS tubes in the first input pair of tubes and the fourth input pair of tubes are both connected to a first input voltage. The gates of the PMOS tubes and the NMOS tubes in the second input pair of tubes and the third input pair of tubes are both connected to a second input voltage. No matter how much the voltage value of the comparator input is, it is always ensured that one transistor in the input pair of tubes is turned on, so that the input voltage range of the comparator circuit can be as low as zero, thereby expanding the input voltage range of the comparator circuit. At the same time, the first amplifier sub-circuit and the second amplifier sub-circuit perform gain amplification on the input voltage signal, thereby improving the accuracy of the comparator circuit.
[0132] The chip of this embodiment has an input voltage range as low as zero, which expands the range of the input voltage. At the same time, the input voltage signal is gain-amplified, which can improve the accuracy of the chip.
[0133] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.
Claims
1. A comparator circuit, characterized in that: include: Amplifier circuit and comparison circuit; The amplifier circuit includes a first input pair of transistors, a second input pair of transistors, a third input pair of transistors, a fourth input pair of transistors, a first amplifier sub-circuit and a second amplifier sub-circuit; The first input pair of transistors, the second input pair of transistors, the third input pair of transistors and the fourth input pair of transistors each include a PMOS transistor and an NMOS transistor with gates connected to each other; The gates of the NMOS tubes in the first input pair and the fourth input pair are used to connect to a first input voltage and output the first input voltage to the first amplifying sub-circuit and the second amplifying sub-circuit respectively, and the gates of the NMOS tubes in the second input pair and the third input pair are used to connect to a second input voltage and output the second input voltage to the first amplifying sub-circuit and the second amplifying sub-circuit respectively; The first amplifying sub-circuit is used to perform gain amplification on the differential voltage between the first input voltage and the second input voltage and output a first amplified voltage; The second amplifying sub-circuit is used to perform gain amplification on the differential voltage between the first input voltage and the second input voltage and output a second amplified voltage; The comparison circuit is used for comparing the first amplified voltage with the second amplified voltage to obtain a comparison result corresponding to the first input voltage and the second input voltage; The comparison circuit includes: a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube and a first inverter; The gate of the thirty-fifth NMOS tube is connected to an external clock, the source of the thirty-fifth NMOS tube is grounded, the drain of the thirty-fifth NMOS tube is respectively connected to the source of the thirty-third NMOS tube and the source of the thirty-fourth NMOS tube, the gate of the thirty-third NMOS tube is connected to the second amplified voltage, the gate of the thirty-fourth NMOS tube is connected to the first amplified voltage, the drain of the thirty-third NMOS tube is connected to the source of the thirty-first NMOS tube, the drain of the thirty-fourth NMOS tube is connected to the source of the thirty-second NMOS tube, the thirty-first PMOS tube, the thirty-second PMOS tube, the thirty-third PMOS tube and the thirty-third NMOS tube are connected to the source of the thirty-third NMOS tube. The sources of the thirty-fourth PMOS tube are all connected to the power supply voltage, the gates of the thirty-first PMOS tube and the thirty-fourth PMOS tube are all connected to the external clock, the drain of the thirty-first PMOS tube is respectively connected to the drain of the thirty-second PMOS tube, the drain of the thirty-first NMOS tube, the gate of the thirty-second NMOS tube and the gate of the thirty-third PMOS tube, the gate of the thirty-second PMOS tube is respectively connected to the gate of the thirty-first NMOS tube, the drain of the thirty-third PMOS tube, the drain of the thirty-second NMOS tube and the input end of the first inverter, and the drain of the thirty-fourth PMOS tube is connected to the input end of the first inverter; The output terminal of the first inverter is used to output the comparison result.
2. The comparator circuit according to claim 1, wherein: The first input pair of transistors includes a first PMOS transistor and a first NMOS transistor; The second input pair of transistors includes a second PMOS transistor and a second NMOS transistor; The first amplifying sub-circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first switch and a second switch; The gate of the first NMOS tube is used to connect to the first input voltage, the gate of the second NMOS tube is used to connect to the second input voltage, the source of the first NMOS tube is connected to the source of the second NMOS tube and the drain of the third NMOS tube, and the drain of the first NMOS tube is connected to the drain of the fourth PMOS tube, the source of the sixth PMOS tube and the drain of the eighth PMOS tube; The source of the first PMOS tube is connected to the source of the second PMOS tube and the drain of the third PMOS tube, and the drain of the first PMOS tube is connected to the drain of the fourth NMOS tube and the source of the sixth NMOS tube; The drain of the second NMOS tube is connected to the source of the seventh PMOS tube, the drain of the ninth PMOS tube and the drain of the fifth PMOS tube; The drain of the second PMOS tube is connected to the drain of the fifth NMOS tube and the source of the seventh NMOS tube; The source of the third NMOS tube, the source of the fourth NMOS tube and the source of the fifth NMOS tube are all grounded, the gate of the third NMOS tube is connected to the fixed end of the second switch, and the movable end of the second switch is selectively connected to the external bias voltage or the ground according to the selection signal; The gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the sixth NMOS tube and the drain of the sixth PMOS tube; The gate of the sixth NMOS tube and the gate of the seventh NMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are all connected to an external bias voltage; The drain of the seventh NMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the seventh NMOS tube is used to output the first amplified voltage; The gate of the third PMOS tube, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube are all connected to an external bias voltage, and the source of the third PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are all connected to a power supply voltage; The gate of the fourth PMOS tube and the gate of the fifth PMOS tube are both connected to the fixed end of the first switch, and the movable end of the first switch selects to connect to the external bias voltage or the power supply voltage based on the selection signal.
3. The comparator circuit according to claim 2, wherein: The third input pair of transistors includes: an eighth NMOS transistor and a seventeenth PMOS transistor; The fourth input pair of transistors includes: a ninth NMOS transistor and an eighteenth PMOS transistor; The second amplifying sub-circuit includes: a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube; The gate of the eighth NMOS tube is connected to the second input voltage, the gate of the ninth NMOS tube is connected to the first input voltage, the source of the eighth NMOS tube is connected to the source of the ninth NMOS tube and the drain of the tenth NMOS tube, and the drain of the eighth NMOS tube is connected to the drain of the eleventh PMOS tube, the source of the thirteenth PMOS tube and the drain of the fifteenth PMOS tube; The source of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube and the drain of the tenth PMOS tube, and the drain of the seventeenth PMOS tube is connected to the drain of the eleventh NMOS tube and the source of the thirteenth NMOS tube; The drain of the ninth NMOS tube is connected to the source of the fourteenth PMOS tube, the drain of the sixteenth PMOS tube and the drain of the twelfth PMOS tube; The drain of the eighteenth PMOS tube is connected to the drain of the twelfth NMOS tube and the source of the fourteenth NMOS tube; The source of the tenth NMOS tube, the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are all grounded, and the gate of the tenth NMOS tube is connected to an external bias voltage; The gate of the eleventh NMOS tube is connected to the gate of the twelfth NMOS tube, the drain of the thirteenth NMOS tube and the drain of the thirteenth PMOS tube; The gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube, the gate of the thirteenth PMOS tube and the gate of the fourteenth PMOS tube are all connected to an external bias voltage; The drain of the fourteenth NMOS tube is connected to the drain of the fourteenth PMOS tube, and the drain of the fourteenth NMOS tube is used to output the second amplified voltage; The gate of the tenth PMOS tube, the gate of the fifteenth PMOS tube and the gate of the sixteenth PMOS tube are all connected to an external bias voltage, and the source of the tenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube are all connected to a power supply voltage; The gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are both connected to an external bias voltage; The gate of the tenth NMOS tube and the gate of the third NMOS tube are connected to the same bias voltage; The gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are connected to the same bias voltage.
4. The comparator circuit according to claim 3, characterized in that The first input pair of transistors, the second input pair of transistors and the first amplifying sub-circuit constitute a first amplifying part; The third input pair of transistors, the fourth input pair of transistors and the second amplifying sub-circuit constitute a second amplifying part; The first amplifying part and the second amplifying part form a folded cascode structure.
5. The comparator circuit according to claim 1, wherein: The comparator circuit also includes a selection signal generating circuit; A first input terminal of the selection signal generating circuit is connected to a common mode voltage of the first input voltage and the second input voltage, and a second input terminal of the selection signal generating circuit is connected to a fixed voltage; The output end of the selection signal generating circuit is connected to the input end of the amplifying circuit; The selection signal generating circuit is used for outputting the selection signal to the amplifying circuit.
6. The comparator circuit according to claim 5, characterized in that The selection signal generating circuit includes: a fifty-third NMOS tube, a fifty-fourth NMOS tube, a fifty-fifth NMOS tube, a fifty-sixth NMOS tube, a fifty-seventh NMOS tube, a fifty-eighth NMOS tube, a fifty-first PMOS tube, a fifty-second PMOS tube, a fifty-third PMOS tube, a fifty-fourth PMOS tube, a fifty-fifth PMOS tube, a fifty-sixth PMOS tube and a second inverter; The gate of the fifty-third NMOS tube is connected to the common mode voltage, the gate of the fifty-fourth NMOS tube is connected to the fixed voltage, the sources of the fifty-third NMOS tube, the fifty-fourth NMOS tube, the fifty-fifth NMOS tube and the fifty-sixth NMOS tube are all grounded, the sources of the fifty-first PMOS tube, the fifty-second PMOS tube, the fifty-third PMOS tube, the fifty-fourth PMOS tube, the fifty-fifth PMOS tube and the fifty-sixth PMOS tube are all connected to the power supply voltage, the drain of the fifty-third NMOS tube is respectively connected to the drain of the fifty-first PMOS tube, the gate of the fifty-first PMOS tube, the drain of the fifty-second PMOS tube, the gate of the fifty-third PMOS tube and the gate of the fifty-sixth NMOS tube, and the fifty-third PMOS tube is connected to the gate of the fifty-fourth PMOS tube. The drain of the fourteenth NMOS tube is respectively connected to the drain of the fifty-fourth PMOS tube, the gate of the fifty-fourth PMOS tube, the drain of the fifty-third PMOS tube, and the gate of the fifty-second PMOS tube, the drain of the fifty-fifth NMOS tube is connected to the source of the fifty-seventh NMOS tube, the drain of the fifty-sixth NMOS tube is connected to the source of the fifty-eighth NMOS tube, the drain of the fifty-seventh NMOS tube is respectively connected to the drain of the fifty-fifth PMOS tube, the gate of the fifty-eighth NMOS tube, and the gate of the fifty-sixth PMOS tube, and the gate of the fifty-seventh NMOS tube is respectively connected to the gate of the fifty-fifth PMOS tube, the drain of the fifty-sixth PMOS tube, the drain of the fifty-eighth NMOS tube, and the input end of the second inverter; The output terminal of the second inverter is used to output the selection signal.
7. The comparator circuit according to claim 6, wherein: The selection signal generating circuit further includes: a fifty-first NMOS tube and a fifty-second NMOS tube; The gate of the fifty-first NMOS tube and the gate of the fifty-second NMOS tube are connected to an external bias voltage, the source of the fifty-first NMOS tube and the source of the fifty-second NMOS tube are connected to the ground, the drain of the fifty-first NMOS tube is respectively connected to the source of the fifty-third NMOS tube and the fifty-fourth NMOS tube, and the drain of the fifty-second NMOS tube is respectively connected to the source of the fifty-fifth NMOS tube and the fifty-sixth NMOS tube.
8. The comparator circuit according to claim 5, characterized in that The fixed voltage has a value greater than a threshold value of the NMOS transistor.
9. A chip, characterized in that: Comprising a comparator circuit as claimed in any one of claims 1 to 8.
Citation Information
Patent Citations
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