Light detection device

Abstract

The present invention relates to a light detection device comprising: a plurality of pixels arranged in rows and columns, the plurality of pixels comprising a first group of pixels optically shielded from light and a second group of pixels configured to receive light; a plurality of signal lines comprising a first signal line connected to a first pixel of the first group of pixels, a second signal line connected to a second pixel of the second group of pixels and a third signal line connected to a third pixel of the first group of pixels; and a plurality of AD converters comprising a first AD converter configured to receive a first signal via the first signal line, a second AD converter configured to receive a second signal via the second signal line and a third AD converter configured to receive a third signal via the third signal line; wherein the first group of pixels is located at an edge of the second group of pixels and the first pixel and the second pixel are in a first column, and wherein the second signal is corrected based on the first signal and the third signal.

Description

[0001] This application is a divisional application of patent application No. 201780077796.2, filed on October 27, 2017, entitled "Solid-state camera device, electronic device and method for controlling solid-state camera device". Technical Field

[0002] This technology relates to solid-state imaging devices, electronic devices, and methods for controlling solid-state imaging devices. More specifically, this technology relates to solid-state imaging devices and electronic devices configured to correct pixel data, and methods for controlling the solid-state imaging device. Background Technology

[0003] Traditionally, solid-state imaging devices, such as complementary MOS (CMOS) or charge-coupled devices (CCD), are used to generate image data in imaging devices. In these solid-state imaging devices, differences in the characteristics of individual pixels and voltage fluctuations can sometimes lead to uneven brightness. In particular, this rib-like uneven brightness is called a stripe. To suppress these stripes, a solid-state imaging device has been proposed in which, when the horizontal direction is defined as the left-right direction, optical black (OPB) pixels are arranged on the left and right sides of the pixel array of effective pixels (see, for example, Patent Document 1).

[0004] Reference List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-111641 Summary of the Invention

[0007] The problem to be solved by the present invention

[0008] In the aforementioned known techniques, solid-state imaging devices can suppress stripes by correcting the pixel data of effective pixels using the pixel data of OPB pixels. However, arranging OPB pixels on the left and right sides of the effective pixel array increases the size of the solid-state imaging device in the left-right direction. On the other hand, although the solid-state imaging device can be reduced in size by decreasing the number of OPB pixels, this may lead to inaccurate correction values, making it difficult to correct stripes with high precision. Thus, the aforementioned known techniques struggle to achieve high-precision correction of uneven brightness (stripes) while suppressing the increase in the size of the solid-state imaging device.

[0009] This technology was developed in view of the above situation, and its purpose is to correct uneven brightness with high precision while suppressing the increase in the size of solid-state imaging devices.

[0010] Technical solutions to the problem

[0011] This technology has been developed to solve the aforementioned problems, and a first aspect of this technology is a solid-state imaging device and a method for controlling the solid-state imaging device, the solid-state imaging device comprising: a pixel array section including a plurality of rows, each row including a predetermined number of pixels arranged along a predetermined direction; an analog-to-digital converter section having more than the predetermined number of analog-to-digital converters arranged thereon for converting analog signals into digital signals; a scanning circuit that performs control to sequentially select the plurality of rows, and whenever a row is selected, the scanning circuit outputs more than the predetermined number of analog signals to the analog-to-digital converter section; and a correction section that performs black level correction processing on the digital signals. This will produce the effect that an analog signal exceeding the number of pixels in the row can be output.

[0012] Furthermore, in the first aspect, the analog signal includes an effective pixel signal and a reference signal representing a black level, and the analog-to-digital conversion unit may include: an effective pixel signal conversion unit that converts the effective pixel signal into a digital signal and outputs the digital signal as effective pixel data; and a reference signal conversion unit that converts the reference signal into a digital signal and outputs the digital signal as reference data. Moreover, the correction unit may perform processing to calculate the difference between the effective pixel data and the reference data as the black level correction processing. This will have the following effect: the difference between the effective pixel data and the reference data can be calculated.

[0013] Furthermore, in the first aspect, it is permissible to further include a dummy circuit for generating the reference signal, wherein each time a row is selected, the scanning circuit can drive each pixel in the selected row, causing that pixel to output the valid pixel signal, and the dummy circuit can also output the reference signal. This will have the effect of correcting the valid pixel data based on reference data obtained by converting the reference signal from the dummy circuit.

[0014] Furthermore, in the first aspect, the analog-to-digital conversion unit includes a plurality of reference signal conversion units and a plurality of effective pixel signal conversion units, and each of the reference signal conversion units may be distributed among the effective pixel signal conversion units. This will produce the following effect: the effective pixel data is corrected based on reference data obtained by converting reference signals from the distributed reference signal conversion units.

[0015] Furthermore, in the first aspect, the pixel array may include: effective pixels for generating the effective pixel signal and light-shielding pixels for generating the reference signal, both of which are arranged as pixels. This will have the effect of correcting the effective pixel data based on reference data obtained by converting the reference signal from the light-shielding pixels.

[0016] Furthermore, in the first aspect, the plurality of rows may include: a plurality of effective pixel rows, in which the predetermined number of effective pixels are arranged along a predetermined direction; and a light-shielding pixel row, in which the predetermined number of light-shielding pixels are arranged along the predetermined direction. Moreover, the scanning circuit can simultaneously select one effective pixel row and the light-shielding pixel row from the plurality of effective pixel rows, and can control the selected effective pixel row and the light-shielding pixel row to output the effective pixel signal and the reference signal respectively. This will produce the following effect: simultaneous selection of any row from the plurality of effective pixel rows and the light-shielding pixel row.

[0017] Furthermore, in the first aspect, each of the plurality of rows may include the effective pixels and the light-blocking pixels, and the scanning circuit may perform control to output an effective pixel signal equal in number to the number of effective pixels in the selected row, and the scanning circuit may perform control to output a reference signal greater in number than the number of light-blocking pixels in the selected row. This will produce the following effect: outputting an effective pixel signal equal in number to the number of effective pixels, and outputting a reference signal greater in number than the number of light-blocking pixels in the selected row.

[0018] Furthermore, in the first aspect, the analog-to-digital converter and the correction unit can be arranged on a predetermined substrate, and the pixel array unit and the scanning circuit can be arranged on a substrate stacked on the predetermined substrate. This will result in the following effect: an analog signal is output from the pixel array unit arranged on the stacked substrate.

[0019] Furthermore, in the first aspect, the analog-to-digital converter (ADC) may include a first ADC and a second ADC, and the scanning circuit may simultaneously select the first and second rows from the plurality of rows. The scanning circuit may also execute control to output the analog signal corresponding to the first row to the first ADC and control to output the analog signal corresponding to the second row to the second ADC. This will produce the effect of simultaneously outputting analog signals from both the first and second rows.

[0020] Furthermore, in the first aspect, the black level correction process may include: multiplying the digital signal by a correction coefficient set for each row. This will have the following effect: multiplying the digital signal by the correction coefficient for each row.

[0021] Furthermore, a second aspect of this technology is an electronic device comprising: a pixel array unit including a plurality of rows, each row including a predetermined number of pixels arranged along a predetermined direction; an analog-to-digital converter unit having more than the predetermined number of analog-to-digital converters for converting analog signals into digital signals; a scanning circuit that performs control to sequentially select the plurality of rows, and whenever a row is selected, the scanning circuit outputs more than the predetermined number of analog signals to the analog-to-digital converter unit; a correction unit that performs black-level correction processing on the digital signals; and a signal processing unit that processes the digital signals after the black-level correction processing. This will produce the following effect: analog signals exceeding the number of pixels in a row are converted into digital signals and processed.

[0022] Effects of the present invention

[0023] According to this technology, the following excellent effects can be achieved: precise correction of uneven brightness can be obtained while suppressing the increase in the size of solid-state imaging devices. Note that the effects described herein are necessarily non-limiting. The effects of this invention can be any of those described in this disclosure. Attached Figure Description

[0024] Figure 1 This is a block diagram illustrating a construction example of an electronic device according to a first embodiment of the present technology.

[0025] Figure 2 This is a block diagram illustrating a construction example of a solid-state camera device according to a first embodiment of the present technology.

[0026] Figure 3 This is a block diagram illustrating a construction example of a pixel array section and a column analog-to-digital converter (ADC) according to a first embodiment of the present technology.

[0027] Figure 4 This is a circuit diagram illustrating a construction example of effective pixels and OPB pixels according to a first embodiment of the present technology.

[0028] Figure 5 This is a block diagram illustrating a construction example of a logic circuit according to a first embodiment of the present technology.

[0029] Figure 6 This is a graph illustrating an example of the order in which rows are accessed in a first embodiment of this technology.

[0030] Figure 7 This is a timing diagram illustrating an operational example of a scanning circuit according to a first embodiment of the present technology.

[0031] Figure 8 This is a flowchart illustrating an operational example of a solid-state camera device according to a first embodiment of the present technology.

[0032] Figure 9 This is a block diagram illustrating a construction example of a column ADC according to a first variation of the first embodiment of the present technology.

[0033] Figure 10 This is a graph illustrating an example of effective pixel data before and after correction in a first variation of a first embodiment of the present technology.

[0034] Figure 11 This is a block diagram illustrating a construction example of a solid-state imaging device according to a second variation of the first embodiment of the present technology.

[0035] Figure 12 This is a block diagram illustrating a construction example of the pixel array section and column ADC in a third variation of the first embodiment of the present technology.

[0036] Figure 13 This is a block diagram illustrating a construction example of a logic circuit of a fourth variation of the first embodiment of the present technology.

[0037] Figure 14 This is a block diagram illustrating a construction example of the lower logic circuit of a fifth variation of the first embodiment of the present technology.

[0038] Figure 15 This is a block diagram illustrating a construction example of the pixel array section, dummy circuit, and column ADC according to a second embodiment of the present technology.

[0039] Figure 16 This is a circuit diagram illustrating a construction example of a dummy circuit according to a second embodiment of the present technology.

[0040] Figure 17 This is a view showing an example of the arrangement of a dummy circuit according to a second embodiment of the present technology.

[0041] Figure 18 This is a block diagram illustrating a construction example of the pixel array section and column ADC in a third embodiment of the present technology.

[0042] Figure 19 This is a plan view showing a construction example of the OPB region according to a third embodiment of the present technology.

[0043] Figure 20 This is a graph illustrating an example of the order of accessing rows in a third embodiment of the present technology.

[0044] Figure 21 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0045] Figure 22 This is an explanatory diagram showing an example of the installation location of the vehicle exterior information detection unit and the camera unit. Detailed Implementation

[0046] The following will describe embodiments of the present technology (hereinafter referred to as embodiments). The description will be given in the following order.

[0047] 1. First embodiment (example of correction using signals from OPB pixel rows)

[0048] 2. Second embodiment (example of correction using signals from a dummy circuit)

[0049] 3. Third embodiment (example of correction using signals from the OPB column)

[0050] 4. Examples of applications of moving bodies

[0051] <1. First Embodiment>

[0052] [Exemplary Construction of Electronic Devices]

[0053] Figure 1 This is a block diagram illustrating a construction example of an electronic device 100 according to a first embodiment of the present technology. The electronic device 100 is an electronic device with a camera function, and includes a camera lens 110, a solid-state camera device 200, an image processing unit 120, a camera control unit 130, and a recording unit 140. Examples of applications for the electronic device 100 include digital cameras, smartphones, and personal computers.

[0054] The camera lens 110 gathers light from the subject and directs the gathered light to the solid-state camera device 200.

[0055] The solid-state imaging device 200 acquires image data synchronously with the vertical synchronization signal VSYNC from the camera control unit 130. Here, the vertical synchronization signal VSYNC is a timing signal indicating the moment of image capture. For example, a periodic signal of 30 Hz or 60 Hz is used as the vertical synchronization signal VSYNC. The solid-state imaging device 200 provides the image data to the image processing unit 120 via signal line 209.

[0056] The camera control unit 130 controls the solid-state camera device 200. The camera control unit 130 provides the solid-state camera device 200 with a vertical synchronization signal VSYNC or a signal for controlling exposure time via signal line 139. In addition, for example, the camera control unit 130 starts supplying the vertical synchronization signal VSYNC in response to a camera start operation (e.g., pressing the shutter button).

[0057] The image processing unit 120 performs various types of image processing on the image data, such as depigmentation and white balance processing. The image processing unit 120 provides the processed image data to the recording unit 140 via signal line 129. The recording unit 140 records the image data. Note that the image processing unit 120 is an example of the signal processing unit described in the claims.

[0058] (Exemplary construction of a solid-state camera device)

[0059] Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device 200 according to a first embodiment of the present technology. The solid-state imaging device 200 includes a semiconductor substrate 201. The semiconductor substrate 201 includes a scanning circuit 210, a pixel array section 300, a column ADC 220, a logic circuit 250, and a timing control section 280.

[0060] The pixel array section 300 includes a plurality of pixels arranged in a two-dimensional grid pattern. Hereinafter, a set of pixels arranged along a predetermined direction will be referred to as a "row," and a set of pixels arranged in a direction perpendicular to the rows will be referred to as a "column." Furthermore, the pixel array section 300 includes unshielded effective pixels and shielded OPB pixels, which serve as array pixels. The respective arrangement positions of the effective pixels and OPB pixels will be explained later.

[0061] The timing control unit 280 controls the operation timing of the scanning circuit 210, the column ADC 220 and the logic circuit 250 synchronously with the vertical synchronization signal VSYNC.

[0062] The scanning circuit 210 selects rows sequentially and drives the pixels in the selected rows. Each driven pixel provides an analog pixel signal to the column ADC 220.

[0063] The ADC 220 converts each pixel signal into a digital signal and outputs the digital signal as pixel data to the logic circuit 250.

[0064] Logic circuit 250 performs black level correction processing for each pixel data to suppress stripes. Logic circuit 250 provides image data including the processed pixel data to image processing unit 120. Note that logic circuit 250 is an example of the correction unit described in the claims.

[0065] Figure 3 This is a block diagram illustrating a construction example of the pixel array section 300 and the column ADC 220 in the first embodiment of the present technology. The pixel array section 300 is divided into an effective pixel region 310 and an OPB region 350.

[0066] The effective pixel region 310 includes a plurality of effective pixels 320 arranged in a two-dimensional grid pattern. The effective pixels 320 include M (M is an integer) rows and N (N is an integer) columns. Furthermore, the effective pixel region 310 includes vertical signal lines 308-n (n is an integer from 0 to N-1)v arranged for each column. Each effective pixel 320 in the nth column is connected to the vertical signal line 308-nv.

[0067] When the column direction of the effective pixel region 310 is defined as the vertical direction, the OPB region 350 is arranged adjacent to the upper or lower side of the effective pixel region 310. For example, when the column ADC220 side is defined as the lower side, the OPB region 350 is arranged below the effective pixel region 310. The OPB region 350 includes N OPB pixels 360 arranged along the row direction. Furthermore, the OPB region 350 is connected to the vertical signal line 309-nv of each column. The OPB pixel 360 of the nth column is connected to the vertical signal line 309-nv. Note that the OPB pixel 360 is an example of a light-shielding pixel as described in the claims.

[0068] The column ADC 220 includes two OPB column conversion units 221 and an effective pixel column conversion unit 223. When the row direction is defined as the left-right direction, the OPB column conversion units 221 are arranged to the left and right of the effective pixel column conversion units 223. Furthermore, each OPB column conversion unit 221 includes N / 2 ADCs 222 arranged along the row direction. The effective pixel column conversion unit 223 includes N ADCs 222 arranged along the row direction. That is, the column ADC 220 includes an array of N×2 ADCs 222. Note that the column ADC 220 is an example of the analog-to-digital converter described in the claims. Furthermore, the OPB column conversion unit 221 is an example of the reference signal converter described in the claims. The effective pixel column conversion unit 223 is an example of the effective pixel signal converter described in the claims.

[0069] The nth column of the OPB column conversion section 221 on the left L The ADC 222 in the column is connected via vertical signal line 309-n L v connects to the nth L The OPB in the column is 360 pixels. Here, n L It is an integer from 0 to (N / 2-1). The nth term in the OPB column transformation section 221 on the right... R The ADC 222 in the column is connected via vertical signal line 309-nR v connects to the nth R The OPB in the column is 360 pixels. Here, n R It is an integer from N / 2 to N-1.

[0070] The nth column ADC 222 in the effective pixel column conversion unit 223 is connected to the nth column effective pixel 320 via the vertical signal line 308-nv.

[0071] Each ADC 222 converts the analog pixel signal from the corresponding vertical signal line into digital pixel data. Hereinafter, the pixel signal from the effective pixel 320 is referred to as the "effective pixel signal," and the pixel signal from the OPB pixel 360 is referred to as the "OPB pixel signal." This OPB pixel signal serves as a reference signal representing the black level during stripe correction. Furthermore, hereinafter, the pixel data corresponding to the effective pixel signal is referred to as "effective pixel data," and the pixel data corresponding to the OPB pixel signal is referred to as "OPB pixel data." Note that the OPB pixel signal is an example of the reference signal described in the claims, and the OPB pixel data is an example of the reference data described in the claims.

[0072] The scanning circuit 210 sequentially selects a row of valid pixels 320 (hereinafter referred to as the "valid pixel row"), and whenever a valid pixel row is selected, the scanning circuit 210 simultaneously selects a row of OPB pixels 360 (hereinafter referred to as the "OPB pixel row"). Therefore, whenever a valid pixel row is selected, the selected valid pixel row outputs N valid pixel signals, and the OPB pixel row outputs N OPB pixel signals. Next, the column ADC 220 converts the pixel signals into N×2 pixel data and outputs this data to the logic circuit 250.

[0073] Typically, rib-like components (stripes) may appear due to voltage fluctuations, differences in characteristics between the pixel array section 300 and the column ADC 220. Even when voltage fluctuations occur in individual effective pixel rows, since both effective pixel rows and OPB pixel rows are driven simultaneously, the signal from the OPB pixel row under the same voltage conditions will be used to perform correction, thereby suppressing stripes caused by voltage fluctuations.

[0074] Furthermore, since the process conditions and temperature conditions are the same in the effective pixel row and the OPB pixel row, correction using the signal from the OPB pixel row can suppress stripes caused by the characteristic differences of the pixel array section 300.

[0075] Furthermore, since the process conditions and temperature conditions in the OPB column conversion unit 221 and the effective pixel column conversion unit 223 are the same, correction using OPB pixel data can suppress stripes caused by differences in the characteristics of the column ADC 220.

[0076] Furthermore, since the OPB region 350 is arranged below the effective pixel region 310, the size of the pixel array section 300 can be reduced in the left-right direction (row direction) compared to the case where the OPB region 350 is arranged on the left or right side.

[0077] [Example of pixel array construction]

[0078] Figure 4 This is a circuit diagram illustrating a construction example of an effective pixel 320 and an OPB pixel 360 according to a first embodiment of the present technology. Each effective pixel 320 includes a reset transistor 321, a transmission transistor 322, a photodiode 323, an amplification transistor 324, a floating diffusion layer 325, and a selection transistor 326.

[0079] Photodiode 323 performs photoelectric conversion to generate charge from light. Transmission transistor 322 transfers the charge generated by photodiode 323 to floating diffusion layer 325 according to transmission signal TRG_M (M is an integer from 0 to M).

[0080] The floating diffusion layer 325 accumulates the transferred charge and generates a voltage corresponding to the amount of charge. The reset transistor 321 initializes the charge of the floating diffusion layer 325 according to the reset signal RST_M.

[0081] Amplifying transistor 324 amplifies the voltage of floating diffusion layer 325. Selecting transistor 326 outputs the amplified voltage signal as an effective pixel signal to effective pixel column conversion unit 223 via vertical signal line 308-nv according to the selection signal SEL_M.

[0082] The scanning circuit 210 provides a selection signal SEL_M to the selected row. Furthermore, at the start of exposure for the selected row, the scanning circuit 210 sends a transfer signal TRG_M and a reset signal RST_M, and initializes the voltage. Subsequently, at the end of exposure for the selected row, the scanning circuit 210 sends the transfer signal TRG_M to transfer charge.

[0083] Each OPB pixel 360 includes a reset transistor 361, a transmission transistor 362, a photodiode 363, an amplification transistor 364, a floating diffusion layer 365, and a selection transistor 366. These components function similarly to those in the effective pixel 320.

[0084] Note that the circuitry for effective pixels 320 and the circuitry for OPB pixels 360 are not limited to... Figure 4 The circuit shown. For example, this construction can use a floating diffusion layer shared by multiple pixels.

[0085] [Example of logic circuit construction]

[0086] Figure 5 This is a block diagram illustrating a construction example of a logic circuit 250 according to a first embodiment of the present technology. The logic circuit 250 includes a correction value calculation unit 251 and a black level correction unit 252. The black level correction unit 252 includes N subtractors 253.

[0087] Whenever a valid pixel row is selected, the correction value calculation unit 251 calculates the average value of N OPB pixel data as the correction value. The correction value calculation unit 251 provides the correction value to the black level correction unit 252. Note that although the correction value calculation unit 251 calculates the average value as the correction value, it can also calculate a statistical value other than the average value (such as the median value) as the correction value.

[0088] Subtractor 253 calculates the difference between the effective pixel data of the corresponding column and the correction value. Subtractor 253 of the nth column subtracts the correction value from the effective pixel data of the nth column. Subtractor 253 outputs the calculated difference as the OPB-corrected effective pixel data to the image processing unit 120.

[0089] Note that, in addition to using OPB pixel data for black level correction, logic circuit 250 can also perform signal processing such as correlated double sampling (CDS) processing.

[0090] Figure 6 This is a graph illustrating an example of the order of accessing rows in a first embodiment of the present technology. In this graph, the vertical axis represents the address (vertical address) of the row (line / row) that is the access destination, and the horizontal axis represents time. V_0 represents the vertical address of the OPB pixel row, and V_1 to V_M represent the vertical addresses of the valid pixel rows.

[0091] At time T_1 within the period of the vertical synchronization signal VSYNC, the scanning circuit 210 simultaneously accesses the addresses of V_0 and V_1. This operation simultaneously drives the OPB pixel row and the first valid pixel row.

[0092] Subsequently, at the next time step T_2, the scan circuit 210 simultaneously accesses the addresses of V_0 and V_2. This operation simultaneously drives the OPB pixel row and the second valid pixel row. Thereafter, similarly, the scan circuit 210 repeatedly performs the process of simultaneously accessing the addresses of V_0 and V_3 or their subsequent addresses.

[0093] Subsequently, at time T_M, the scan circuit 210 simultaneously accesses the addresses of V_0 and V_M. This operation simultaneously drives the OPB pixel row and the last valid pixel row. In this way, one of multiple valid pixel rows and the OPB pixel row are driven simultaneously. Using this construction, N×2 pixel signals are output whenever a valid pixel row is selected.

[0094] The above series of processes generates image data. Similar processes are used to generate image data during each cycle of the vertical synchronization signal VSYNC.

[0095] Here, it is assumed that the OPB region 350 is arranged on the left and right sides of the effective pixel region 310. In this case, in order to output N×2 pixel signals whenever an effective pixel row is selected, a total of N columns of OPB pixels must be arranged on the left and right sides. Compared with the case of only effective pixels, arranging up to N columns of OPB pixels will double the size of the pixel array section 300 in the left-right direction. Similarly, the area of ​​the pixel array section 300 is also doubled, making it difficult to miniaturize the solid-state imaging device 200.

[0096] Conversely, the solid-state imaging device 200 arranges the OPB pixel row below the effective pixel area 310. Therefore, the size of the pixel array section 300 in the left-right direction can be as small as in the case of a structure with only effective pixels. Furthermore, since the OPB pixel row is a single row, the size of the pixel array section 300 in the vertical direction can be as small as (M+1) / M times, and the area is also as small as (M+1) / M times.

[0097] Meanwhile, even when the OPB region 350 is arranged to the left and right of the effective pixel region 310, the increase in size can be suppressed by reducing the number of columns of OPB pixels. However, on the other hand, the number of OPB pixel signals in each row will be reduced, making it difficult to perform correction with high precision.

[0098] Conversely, the solid-state camera 200 outputs a number of OPB pixel signals for each effective pixel row that are the same as the number of columns N in that row, thus enabling high-precision correction.

[0099] Figure 7 This is a timing diagram illustrating an operational example of the scanning circuit 210 according to a first embodiment of the present technology. It is assumed that the period of the vertical synchronization signal corresponds to a 1V period. During the period from time T_1 to T_M within the 1V period, the scanning circuit 210 outputs a selection signal SEL_0 to drive the OPB pixel row. Furthermore, at time T_1, the scanning circuit 210 outputs a selection signal SEL_1 to drive the first valid pixel row.

[0100] At the next time point T_2, the scanning circuit 210 outputs a selection signal SEL_2 to drive the second valid pixel row, and at time T_3, it outputs a selection signal SEL_3 to drive the third valid pixel row. Thereafter, the valid pixel rows are driven sequentially in a similar manner.

[0101] [Operational Example of a Solid-State Camera Device]

[0102] Figure 8 This is a flowchart illustrating an operational example of a solid-state camera device according to a first embodiment of the present technology. For example, the operation is initiated in response to an action to start recording.

[0103] The solid-state camera device 200 sets the initial value "1" to m (step S901). Next, the solid-state camera device 200 simultaneously drives the m-th row (effective pixel row) and the 0th row (OPB pixel row) to read out the pixel data (step S902).

[0104] The solid-state camera device 200 calculates the average value of the OPB pixel data as a correction value (step S903), and corrects the effective pixel data using this correction value (step S904). The solid-state camera device 200 increases m by an increment (step S905), and determines whether m is greater than M (i.e., determines whether this is the last row) (step S906).

[0105] If m is less than or equal to M (step S906: No), the solid-state camera device 200 repeats step S902 and subsequent steps. Conversely, if m is greater than M (step S906: Yes), the solid-state camera device 200 performs image processing on the image data (step S907) and determines whether the camera control unit 130 has indicated the end of recording (step S908).

[0106] If no indication is given that the recording has ended (step S908: No), the solid-state camera device 200 repeats the processing of step S901 and its subsequent steps. Conversely, if an indication is given that the recording has ended (step S908: Yes), the solid-state camera device 200 completes the recording operation.

[0107] In this manner, according to the first embodiment of the present technology, the scanning circuit 210 outputs the effective pixel signal and the OPB pixel signal to each of 2N ADCs 222, which are more numerous than the number of columns N of the effective pixel rows, thereby enabling stripe correction using the OPB pixel signal. Furthermore, since the number of columns of the effective pixels is less than the number of ADCs 222 (2N), the size of the solid-state imaging device 200 can be reduced compared to the case where the number of columns is 2N.

[0108] [First Variation]

[0109] In the first embodiment described above, in the column ADC 220, the OPB column conversion unit 221 is arranged to the left and right of the effective pixel column conversion unit 223. However, this arrangement may not be able to adequately correct uneven brightness when uneven brightness occurs in each column. The uneven brightness occurring in each column is referred to as the horizontal shadow component. The solid-state imaging device 200 of the first variant of the first embodiment differs from the solid-state imaging device 200 of the first embodiment in that it further corrects the horizontal shadow component.

[0110] Figure 9 This is a block diagram illustrating a construction example of a column ADC 220 according to a first variation of the first embodiment of the present technology. The column ADC 220 of the first variation of the first embodiment includes a plurality of OPB column conversion units 221 and a plurality of effective pixel column conversion units 223. Furthermore, the OPB column conversion units 221 are distributed at both ends and in portions between each of the effective pixel column conversion units 223. For example, in the case where three effective pixel column conversion units 223 and four OPB column conversion units 221 are arranged, two of the OPB column conversion units 221 are arranged at both ends. Furthermore, the remaining two OPB column conversion units 221 are respectively arranged between the three effective pixel column conversion units 223.

[0111] The black level correction unit 252 corrects the effective pixel data of the effective pixel column conversion unit 223 by using OPB pixel data from the OPB column conversion unit 221 adjacent to each effective pixel column conversion unit 223. For example, the effective pixel data of the leftmost effective pixel column conversion unit 223 is corrected by averaging the OPB pixel data from the leftmost OPB column conversion unit 221 and the OPB pixel data from the second OPB column conversion unit 221 counting from the leftmost.

[0112] Figure 10 This is a graph showing examples of effective pixel data before and after correction in a first variation of the first embodiment of the present technology. In this graph, a is a graph showing examples of effective pixel data for each column before black level correction, and b is a graph showing examples of effective pixel data for each column after black level correction. Furthermore, in this graph, the vertical axis represents the brightness value of the effective pixel data, and the horizontal axis represents the horizontal address as the column address. The values ​​on the dashed lines represent the actual black level. Additionally, the hollow circles represent the average value (correction value) of the OPB pixel data of the OPB column conversion unit 221. The solid lines represent the brightness values ​​of the effective pixel data.

[0113] like Figure 10As shown in Figure a, before black level correction, the average value of the OPB pixel data in the left column is relatively higher than the average value in the right column. Therefore, overall, the brightness of the left column is higher than that of the right column. In other words, there is a horizontal shadow component representing uneven brightness in each column. As shown in Figure b, this horizontal shadow component can be corrected by performing correction using the correction values ​​(hollow circles) of the dispersed OPB column conversion units 221.

[0114] In this way, in a first variation of the first embodiment of the present technology, the OPB column conversion unit 221 is distributed in a dispersed manner, so that the solid-state imaging device 200 can correct the horizontal shadow component by using the correction value of the OPB column conversion unit 221.

[0115] [Second variation]

[0116] In the first embodiment described above, the pixel array 300 and the column ADC 220 are arranged on a semiconductor substrate 201. However, if the area of ​​the semiconductor substrate 201 is fixed, it is necessary to further miniaturize the pixels while increasing the number of pixels. This miniaturization will reduce the area of ​​the photodiode of each pixel, making it difficult to maintain pixel characteristics such as sensitivity. To solve this problem, by dispersing the pixel array 300 and the like on multiple stacked substrates, it is possible to suppress the degradation of pixel characteristics (sensitivity, etc.) caused by miniaturization. The solid-state imaging device 200 of the second variation of the first embodiment differs from the solid-state imaging device 200 of the first embodiment in that the pixel array 300 and the column ADC 220 are dispersedly arranged on multiple stacked semiconductor substrates.

[0117] Figure 11 This is a block diagram illustrating a construction example of a solid-state imaging device 200 according to a second modification of the first embodiment of the present technology. The solid-state imaging device 200 according to the second modification of the first embodiment includes an upper substrate 202 and a lower substrate 203. These two substrates are stacked together.

[0118] For example, the upper substrate 202 includes a scanning circuit 210 and a pixel array section 300. For example, the lower substrate 203 includes a column ADC 220, a logic circuit 250, and a timing control section 280.

[0119] Note that although the scanning circuit 210 and the pixel array section 300 are arranged on the upper substrate 202, and the rest are arranged on the lower substrate 203, the present invention is not limited to this configuration. For example, it is also permissible to arrange the pixel array section 300 separately on the upper substrate 202 and arrange the rest on the lower substrate 203.

[0120] In this way, in the second variation of the first embodiment of the present technology, the pixel array portion 300 and the column ADC 220 are distributed on multiple stacked substrates, thereby suppressing the degradation of pixel characteristics due to miniaturization.

[0121] [Third Variation]

[0122] In the first embodiment described above, the ADC 222 is arranged for one row of valid pixels and performs row-by-row readout. However, this method increases the time required to read out all rows as the number of rows increases. The solid-state camera 200 of the third variation of the first embodiment differs from the solid-state camera 200 of the first embodiment in that it reduces the time required to read out all rows.

[0123] Figure 12 This is a block diagram illustrating a construction example of the pixel array section 300 and the column ADC in a third variation of the first embodiment of the present technology. The pixel array section 300 of the third variation of the first embodiment includes an upper OPB region 370 and a lower OPB region 380, replacing the OPB region 350. Furthermore, the solid-state imaging device 200 of the third variation includes an upper column ADC 230 and a lower column ADC 240, replacing the column ADC 220. Note that the upper column ADC 230 is an example of the first analog-to-digital converter described in the claims, and the lower column ADC 240 is an example of the second analog-to-digital converter described in the claims.

[0124] The upper OPB region 370 and the lower OPB region 380 each include N OPB pixels arranged along the row direction. Furthermore, when the column direction is defined as the vertical direction, the upper OPB region 370 is arranged above the effective pixel region 310, and the lower OPB region 380 is arranged below the effective pixel region 310.

[0125] The scanning circuit 210 simultaneously selects two rows (e.g., an odd-numbered row and an even-numbered row) of the effective pixel region 310, as well as the upper OPB pixel row and the lower OPB pixel row. The selected odd-numbered row and the upper OPB pixel row within the effective pixel region 310 output N effective pixel signals and N OPB pixel signals, respectively, to the upper column ADC 230. Furthermore, the selected even-numbered row and the lower OPB pixel row within the effective pixel region 310 output N effective pixel signals and N OPB pixel signals, respectively, to the lower column ADC 240.

[0126] The upper column ADC 230 and the lower column ADC 240 each include N×2 ADCs, which are arranged similarly to the column ADC 220 in the first embodiment. The upper column ADC 230 and the lower column ADC 240 each convert the input N×2 pixel signals (effective pixel signals and OPB pixel signals) into digital signals.

[0127] Note that although the solid-state camera 200 reads two rows of the effective pixel area 310 simultaneously, it is also possible to read three or more rows simultaneously. For example, to read four rows simultaneously, setting four column ADCs and four OPB pixel rows is sufficient.

[0128] In this way, according to the third variation of the first embodiment of the present technology, since two rows of the effective pixel area 310 are read out simultaneously, the time required to read out all rows can be reduced compared to reading out one row at a time.

[0129] [Fourth variation]

[0130] In the first embodiment described above, the solid-state imaging device 200 corrects the effective pixel data using the average value (correction value) of the OPB pixel data read simultaneously with the effective pixel data. However, if an offset component is generated in addition to the correction value of the OPB pixel data due to differences in the characteristics of the effective pixels, it will be difficult to correct the offset component using only the correction value. For example, if offset components appear in each row, uneven brightness will occur in each row, and this component is called the vertical shadow component. The solid-state imaging device 200 according to the fourth variation of the first embodiment differs from the first embodiment in that it further corrects the vertical shadow component.

[0131] Figure 13 This is a block diagram illustrating a construction example of the logic circuit 250 of a fourth variation of the first embodiment of the present technology. The logic circuit 250 of the fourth variation of the first embodiment differs from that of the first embodiment in that it further includes a per-row correction coefficient holding section 254 and a vertical shading correction section 255.

[0132] The line correction coefficient holding unit 254 stores correction coefficients for each valid pixel line used to correct offset components. For example, these correction coefficients are calculated and pre-stored during testing at the time of shipment. In addition, whenever a valid pixel line is selected, the vertical shadow correction unit 255 reads the correction coefficient corresponding to that line.

[0133] The vertical shadow correction unit 255 includes N multipliers 256. The multiplier 256 in the nth column (n is an integer from 0 to N-1) multiplies the effective pixel data after OPB correction in the nth column by the correction coefficient corresponding to the effective pixel row. Next, the multiplier 256 provides the multiplied data as the vertical shadow corrected pixel data to the image processing unit 120.

[0134] Note that although the vertical shadow correction unit 255 uses pre-saved correction coefficients, the vertical shadow correction unit 255 can also calculate the correction coefficients from the average value of the effective pixel rows during shooting.

[0135] In this way, in the fourth variation of the first embodiment of the present technology, the vertical shadow component can be corrected by multiplying the OPB-corrected pixel data by the corresponding correction coefficient for each effective pixel row.

[0136] [Fifth Variation]

[0137] In the fourth variation of the first embodiment described above, the ADC 222 is arranged row by row for each effective pixel and read out line by line, thereby correcting the vertical shading component. However, this method increases the time required to read out all rows as the number of rows increases. The solid-state imaging device 200 of the fifth variation of the first embodiment differs from the solid-state imaging device 200 of the fourth variation in that it reduces the time required to read out all rows.

[0138] Figure 14 This is a block diagram illustrating a construction example of the lower logic circuit 270 in a fifth modification of the first embodiment of the present technology. The solid-state imaging device 200 of the fifth modification of the first embodiment includes an upper logic circuit 260 and a lower logic circuit 270, which replace the logic circuit 250.

[0139] The lower logic circuit 270 includes a correction value calculation unit 271, a black level correction unit 272, a correction coefficient holding unit for each row 274, and a vertical shadow correction unit 275. The black level correction unit 272 includes N subtractors 273. The black level correction unit 272 corrects the effective pixel data of each column by using the average value of the OPB pixel data, and outputs the corrected data as the lower OPB corrected pixel data to the vertical shadow correction unit 275.

[0140] The correction coefficient holding section 274 stores the correction coefficients for each valid pixel row.

[0141] The vertical shadow correction unit 275 includes N×2 multipliers 276 and N adders 277.

[0142] The even-numbered multiplier 276 multiplies the lower OPB-corrected pixel data of the nth column by the corresponding correction coefficient for that even-numbered row, and provides the multiplied value to the nth adder 277. The odd-numbered multiplier 276 multiplies the upper OPB-corrected pixel data of the nth column by the corresponding correction coefficient for that odd-numbered row, and provides the multiplied value to the nth adder 277. The nth adder 277 adds the multiplication values ​​from the corresponding two multipliers 276, and provides the sum as the vertically shading-corrected pixel data to the image processing unit 120.

[0143] The upper logic circuit 260 is constructed similarly to the lower logic circuit 270.

[0144] In this way, the fifth variation of the first embodiment of the present technology simultaneously reads out two rows of the effective pixel area 310 and multiplies the data by a correction factor, thereby correcting the vertical shadow component while reducing the time required to read out all rows.

[0145] <2. Second Embodiment>

[0146] In the first embodiment described above, in addition to the effective pixels 320, an OPB pixel 360 having the same structure as the effective pixels is added to the pixel array section 300. However, the addition of the OPB pixel 360 increases the size of the pixel array section 300. The solid-state imaging device 200 according to the second embodiment differs from the first embodiment in that the size of the pixel array section 300 is further reduced.

[0147] Figure 15 This is a block diagram illustrating a construction example of the pixel array section 300, dummy circuit 290, and column ADC 220 according to a second embodiment of the present technology. The solid-state imaging device 200 of the second embodiment includes two dummy circuits 290. Furthermore, the pixel array section 300 of the second embodiment only includes the effective pixel region 310, and does not have an OPB region 350.

[0148] Furthermore, the column ADC 220 of the second embodiment includes two reference signal conversion units 224, replacing the two OPB column conversion units 221. The reference signal conversion units 224 are arranged to the left and right of the effective pixel column conversion units 223. Two dummy circuits 290 are arranged between the pixel array unit 300 and the column ADC 220. One of these dummy circuits 290 is connected to the reference signal conversion unit 224 on the left, while the other dummy circuit 290 is connected to the reference signal conversion unit 224 on the right.

[0149] Under the control of the scanning circuit 210, each dummy circuit 290 outputs C predetermined reference signals to the corresponding reference signal conversion unit 224. These reference signals are used as a reference in black level correction. For example, a signal with correlated noise sufficiently suppressed to approximately 10 μVrms (root mean square) is used as the reference signal.

[0150] Each of the two reference signal conversion units 224 is provided with C (C is an integer) ADCs 222. The effective pixel column conversion unit 223 is provided with N ADCs 222, similar to the first embodiment. That is, a total of (N+2C) ADCs 222 are provided in the column ADCs 220. The reference signal conversion unit 224 converts each of the C reference signals into a digital signal and outputs the signal as reference data to the logic circuit 250. Thereafter, the logic circuit 250 corrects the effective pixel data by using the reference data to replace the OPB pixel data.

[0151] Figure 16 This is a circuit diagram illustrating a construction example of a dummy circuit 290 according to a second embodiment of the present technology. The dummy circuit 290 includes an amplifying transistor 291 and a selecting transistor 292. The construction of the amplifying transistor 291 and the selecting transistor 292 is similar to the construction of the amplifying transistor 324 and the selecting transistor 326 in the effective pixel 320. However, the vertical signal line connected to the selecting transistor 292 is branched into C lines, and C reference signals are output.

[0152] The scanning circuit 210 generates a drive signal DMY with a constant voltage amplitude through a source follower, etc., and inputs the generated signal to the gate of the amplifying transistor 291.

[0153] As described above, since the OPB region 350 is not provided in the pixel array section 300, the solid-state imaging device 200 has difficulty correcting stripes caused by the process conditions or temperature conditions of the pixel array section 300. However, similar to the first embodiment, stripes caused by voltage fluctuations and differences in the column ADC 220 can be corrected. Furthermore, since there is no OPB region 350, the size of the pixel array section 300 can be reduced, thus minimizing the size occupied by the OPB region 350.

[0154] Note that although the dummy circuit 290 is arranged between the column ADC 220 and the pixel array section 300, the location of the dummy circuit 290 is not limited to this location. Figure 17 As shown, the dummy circuit 290 can be placed below the column ADC 230.

[0155] Furthermore, the first to fifth modifications described above can all be applied to the solid-state imaging device 200 of the second embodiment. For example, in the case of the second modification using a stacked structure, the dummy circuit 290 is arranged on the lower substrate 203. Furthermore, in the case of the third modification using an upper column ADC 230 and a lower column ADC 240, these column ADCs can share a single dummy circuit 290.

[0156] In this manner, in the second embodiment of the present technology, the scanning circuit 210 outputs the effective pixel signal and the reference signal to each of N+2C ADCs 222, which are more numerous than the number of columns N of the effective pixel rows, thereby allowing stripes to be corrected using the reference signal. Furthermore, since the number of columns of the effective pixels is less than the number of ADCs 222 (N+2C), the size of the solid-state imaging device 200 can be reduced by that amount of size.

[0157] <3. Third Embodiment>

[0158] In the first embodiment described above, whenever a valid pixel row is selected, the scanning circuit 210 selects and reads out the OPB pixel rows. However, this scanning method doubles the number of rows to be read compared to selecting only valid pixel rows, resulting in increased power consumption of the solid-state camera 200. Therefore, from the perspective of reducing power consumption, it is desirable to reduce the number of rows to be read. The solid-state camera 200 according to the third embodiment differs from the first embodiment in that it reduces the number of rows to be read.

[0159] Figure 18 This is a block diagram illustrating a construction example of the pixel array section 300 and the column ADC 220 in the third embodiment of the present technology. In the pixel array section 300 of the third embodiment, the OPB region 350 is not provided on the lower side of the effective pixel region 310. Instead, the OPB region 390 is provided on the left and right sides of the effective pixel region 310.

[0160] Each OPB region 390 includes an OPB pixel array of M rows × B columns (where B is an integer less than C). Furthermore, whenever a valid pixel row is selected, the OPB region 390 generates a pixel addition signal of C pixels and provides this signal to the OPB column conversion unit 221. Here, the pixel addition signal is the sum of the B OPB pixel signals.

[0161] The OPB column conversion unit 221 in the third embodiment each includes an array of C ADCs 222. Similar to the first embodiment, the effective pixel column conversion unit 223 is provided with N ADCs 222. That is, a total of (N+2C) ADCs 222 are provided in the column ADCs 220. The OPB column conversion unit 221 converts each of the C pixel summed signals into a digital signal and outputs the signal as pixel summed data to the logic circuit 250.

[0162] Subsequently, the logic circuit 250 of the third embodiment calculates the value obtained by dividing the sum of the data of 2C pixels by (B×2C) as a correction value, and uses the correction value to correct the effective pixel data.

[0163] Figure 19 This is a plan view illustrating a construction example of the OPB region 390 according to a third embodiment of the present technology. The OPB region 390 includes an array of M rows × B columns of OPB pixels 391. Each column of the OPB pixels 391 is connected to a vertical signal line. All these vertical signal lines are connected. Therefore, whenever a row is selected, B OPB pixel signals are added in an analog manner. Furthermore, the vertical signal lines are branched into C roots, and the sum of the C pixel signals is output to the OPB column conversion unit 221.

[0164] Figure 20 This is a graph illustrating an example of the order of accessing rows in a third embodiment of the present technology. In this graph, the vertical axis represents the address (vertical address) of the row (line / row) that is the access destination, and the horizontal axis represents time. V_1 to V_M represent the vertical address of the row.

[0165] At time T_1, scan circuit 210 accesses address V_1. This operation simultaneously drives the valid pixels and OPB pixels in that row. At this time, N+2C more pixel signals than the number of columns N+2B ​​are output. Subsequently, scan circuit 210 accesses address V_2 and subsequent addresses sequentially in a similar manner. In the first embodiment, the OPB pixel row is accessed N times, but in the third embodiment, this access is not performed, resulting in the number of rows as access destinations being halved.

[0166] Note that each of the first to fifth modifications described above can be applied to the solid-state camera device 200 of the third embodiment.

[0167] In this way, in the third embodiment of the present technology, the scanning circuit 210 outputs pixel signals to each of (N+2C) ADCs 222, which is more numerous than the number of columns (N+2B). This allows for higher precision in stripe correction compared to the case where the number of pixel signals is N+2B. Furthermore, since the number of columns is less than the number of ADCs 222 (N+2C), the size of the solid-state imaging device 200 can be reduced compared to the case where the number of columns is N+2C.

[0168] <4. Examples of applications of moving bodies>

[0169] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body, such as: automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots, etc.

[0170] Figure 21 This is a block diagram illustrating a schematic example of the construction of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure is applicable.

[0171] The vehicle control system 12000 includes multiple electronic control units connected together via a communication network 12001. Figure 21 In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0172] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: drive force generating devices such as internal combustion engines or drive motors that generate drive force for the vehicle; drive force transmission mechanisms that transmit drive force to the wheels; steering mechanisms that adjust the vehicle's steering angle; and braking devices that generate braking force for the vehicle.

[0173] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for devices such as: keyless entry systems; smart key systems; power windows; or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive inputs such as radio waves transmitted from a portable device to replace a key, or signals from various switches. The body system control unit 12020 receives these radio wave or signal inputs and controls the vehicle's door locks, power windows, and lights, etc.

[0174] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing for objects such as pedestrians, vehicles, obstacles, signs, or text on the road surface.

[0175] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0176] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detector 12041 for detecting the driver's state. For example, the driver state detector 12041 may include a camera for capturing images of the driver. Based on the detection information input from the driver state detector 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0177] Based on the vehicle's external / internal information acquired by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can calculate the control target values ​​for the drive force generating device, steering mechanism, or braking device, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for implementing various functions of an advanced driver assistance system (ADAS), including: collision avoidance or impact mitigation, distance-based following, cruise control, collision warning, or lane departure warning, etc.

[0178] Furthermore, based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can control the drive force generating device, steering mechanism, or braking device, thereby performing cooperative control aimed at achieving autonomous driving and other functions that do not rely on the driver's operation.

[0179] Furthermore, based on the vehicle external information acquired by the external information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicle sensed by the external information detection unit 12030, thereby performing coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0180] The audio-visual output unit 12052 sends an output signal of at least one of sound or image to an output device, which is capable of visually or audibly notifying passengers in the vehicle or the outside of the vehicle of information. Figure 21 In the example, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as exemplary output devices. For example, the display unit 12062 may include at least one of an on-board display or a head-up display.

[0181] Figure 22 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0182] exist Figure 22 In the middle, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104, and 12105.

[0183] For example, cameras 12101, 12102, 12103, 12104, and 12105 are installed in the following locations on vehicle 12100: including the front nose, side mirrors, rear bumper, trunk lid, and the upper part of the windshield inside the passenger compartment. Camera 12101 installed at the front nose and camera 12105 installed at the upper part of the windshield inside the passenger compartment primarily acquire images of the front of vehicle 12100. Cameras 12102 and 12103 installed at the side mirrors primarily acquire images of the sides of vehicle 12100. Camera 12104 installed at the rear bumper or trunk lid primarily acquires images of the rear of vehicle 12100. Camera 12105 installed at the upper part of the windshield inside the passenger compartment is mainly used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, or lanes.

[0184] Figure 22 An example of the shooting range of camera units 12101 to 12104 is shown. Camera range 12111 represents the shooting range of camera unit 12101 located at the front nose, camera ranges 12112 and 12113 each represent the shooting range of camera units 12102 and 12103 located at the side mirrors, and camera range 12114 represents the shooting range of camera unit 12104 located at the rear bumper or trunk lid. For example, by superimposing the image data captured by camera units 12101 to 12104, a top-down view of vehicle 12100 is generated.

[0185] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple imaging devices, or may be an imaging device having pixels for phase difference detection.

[0186] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111 to 12114 and how that distance changes over time (relative speed to vehicle 12100). This allows it to identify three-dimensional objects traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), particularly those closest to vehicle 12100 on its path, as preceding vehicles. Furthermore, microcomputer 12051 can set a pre-defined distance between vehicles to ensure a preceding distance and can execute automatic braking control (including follow-stop control) and automatic acceleration control (including follow-push control). In this way, cooperative control aimed at achieving autonomous driving without driver intervention can be implemented.

[0187] For example, based on distance information obtained from cameras 12101-12104, microcomputer 12051 can extract three-dimensional data about a three-dimensional object while classifying it into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles. Microcomputer 12051 can then use the extracted data to automatically avoid obstacles. For instance, microcomputer 12051 identifies obstacles near vehicle 12100 as obstacles with high visibility to the driver of vehicle 12100 and obstacles with low visibility to the driver. Then, microcomputer 12051 determines the collision risk, which represents the degree of danger of colliding with each obstacle. When the collision risk is greater than or equal to a set value and a collision is possible, microcomputer 12051 can output an alarm to the driver via audio speaker 12061 and display unit 12062, and can execute forced deceleration and evasive steering via drive system control unit 12010, thereby achieving driving assistance for collision avoidance.

[0188] At least one of the camera units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, this pedestrian identification is performed by: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and identifying whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 to overlay a rectangular outline for emphasis on the identified pedestrian. Furthermore, the sound image output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0189] Examples of vehicle control systems to which the technology according to this disclosure is applicable have been described above. For example, the technology according to this disclosure can be applied to the camera unit 12101 in the above-described configuration. By applying the technology according to this disclosure to the camera unit 12101, it is possible to suppress the increase in the size of the camera unit 12101 while suppressing stripes in the image data.

[0190] Note that the above embodiments illustrate examples for implementing the present technology, and each aspect of each embodiment corresponds to each aspect of the invention as included in the appended claims. Similarly, each aspect of the invention as included in the appended claims corresponds to each aspect having the same name in the embodiments of the present technology. However, the present technology is not limited to the above embodiments, and various modifications can be made to the above embodiments without departing from the scope of the present technology.

[0191] Furthermore, the processing procedures in the above embodiments can be considered as methods including this series of procedures, and can be considered as programs that enable a computer to execute this series of procedures or as recording media storing the program. For example, the recording medium can be a compact disc (CD), a mini disc (MD), a digital versatile disc (DVD), a memory card, a Blu-ray disc, etc.

[0192] Note that the effects described in this specification are provided for illustrative purposes only and are not intended to be limiting. Other effects may also be considered.

[0193] Note that this technology can also achieve the following technical solutions.

[0194] (1) A solid-state imaging device, comprising:

[0195] A pixel array section comprising multiple rows, each row comprising a predetermined number of pixels arranged along a predetermined direction;

[0196] An analog-to-digital converter unit is provided with more than the predetermined number of analog-to-digital converters, which are used to convert analog signals into digital signals;

[0197] A scanning circuit, which performs control to sequentially select the plurality of rows, and each time a row is selected, the scanning circuit outputs more than the predetermined number of analog signals to the analog-to-digital converter; and

[0198] The correction unit performs black level correction processing on the digital signal.

[0199] (2) The solid-state camera device according to (1), wherein,

[0200] The analog signal includes effective pixel signals and a reference signal representing black level.

[0201] The analog-to-digital converter includes:

[0202] An effective pixel signal conversion unit converts the effective pixel signal into a digital signal and outputs the digital signal as effective pixel data; and

[0203] The reference signal conversion unit converts the reference signal into a digital signal and outputs the digital signal as reference data.

[0204] The correction unit performs a process to calculate the difference between the effective pixel data and the reference data as the black level correction process.

[0205] (3) The solid-state camera device according to (2) further includes

[0206] A dummy circuit is used to generate the reference signal.

[0207] Whenever a row is selected, the scanning circuit drives each pixel in the selected row, causing these pixels to output the valid pixel signal and the dummy circuit to output the reference signal.

[0208] (4) The solid-state camera device according to (2) or (3),

[0209] The analog-to-digital converter includes multiple reference signal conversion units and multiple effective pixel signal conversion units.

[0210] Each of the reference signal conversion sections is distributed among the effective pixel signal conversion sections.

[0211] (5) The solid-state camera device according to any one of (2) to (4),

[0212] The pixel array includes: effective pixels for generating the effective pixel signal and light-shielding pixels for generating the reference signal, wherein the effective pixels and the light-shielding pixels are arranged as pixels.

[0213] (6) The solid-state camera device according to (5),

[0214] The plurality of rows includes a plurality of effective pixel rows and a plurality of light-blocking pixel rows. In the effective pixel rows, a predetermined number of effective pixels are arranged in the predetermined direction. In the light-blocking pixel rows, a predetermined number of light-blocking pixels are arranged in the predetermined direction.

[0215] The scanning circuit simultaneously selects one effective pixel row and the light-blocking pixel row from the plurality of effective pixel rows, and controls the selected effective pixel row and the light-blocking pixel row to output the effective pixel signal and the reference signal respectively.

[0216] (7) The solid-state camera device according to (5),

[0217] Each of the plurality of rows includes the effective pixels and the light-blocking pixels, and

[0218] The scanning circuit performs control to output the effective pixel signal in a quantity equal to the number of effective pixels in the selected row, and the scanning circuit performs control to output the reference signal in a quantity greater than the number of light-blocking pixels in the selected row.

[0219] (8) The solid-state imaging device according to any one of (1) to (7),

[0220] The analog-to-digital converter and the correction unit are arranged on a predetermined substrate, and

[0221] The pixel array and the scanning circuit are arranged on a substrate stacked on the predetermined substrate.

[0222] (9) The solid-state imaging device according to any one of (1) to (8),

[0223] The analog-to-digital converter includes a first analog-to-digital converter and a second analog-to-digital converter, and

[0224] The scanning circuit simultaneously selects the first row and the second row from the plurality of rows, and executes control to output the analog signal corresponding to the first row to the first analog-to-digital converter, and executes control to output the analog signal corresponding to the second row to the second analog-to-digital converter.

[0225] (10) The solid-state imaging device according to any one of (1) to (9),

[0226] The black level correction process includes multiplying the digital signal by a correction coefficient set for each row.

[0227] (11) An electronic device, comprising:

[0228] A pixel array section comprising multiple rows, each row comprising a predetermined number of pixels arranged along a predetermined direction;

[0229] An analog-to-digital converter unit is provided with more than the predetermined number of analog-to-digital converters, which are used to convert analog signals into digital signals;

[0230] A scanning circuit that performs control to select the plurality of rows in sequence, and whenever a row is selected, the scanning circuit outputs more than the predetermined number of analog signals to the analog-to-digital converter.

[0231] The correction unit performs black level correction processing on the digital signal; and

[0232] The signal processing unit performs signal processing on the digital signal that has undergone the black level correction process.

[0233] (12) A method for controlling a solid-state camera device, the solid-state camera device having a pixel array portion comprising a plurality of rows, each row comprising a predetermined number of pixels arranged along a predetermined direction, the method comprising:

[0234] Scanning process: In the pixel array section, control is executed to sequentially select the plurality of rows, and each time a row is selected, an analog signal exceeding the predetermined number is output to an analog-to-digital converter section equipped with an analog-to-digital converter exceeding the predetermined number; and

[0235] Correction process: Perform black level correction processing on the digital signal.

[0236] Explanation of reference numerals in the attached figures

[0237] 100: Electronic devices

[0238] 110: Camera lens

[0239] 120: Image Processing Department

[0240] 130: Camera Control Department

[0241] 140: Recording Department

[0242] 200: Solid-state camera device

[0243] 201: Semiconductor substrate

[0244] 202: Upper substrate

[0245] 203: Lower substrate

[0246] 210: Scanning Circuit

[0247] 220: ADC

[0248] 221: OPB Column Conversion Section

[0249] 222: ADC

[0250] 223: Effective pixel column conversion section

[0251] 224: Reference Signal Conversion Unit

[0252] 230: Top-side ADC

[0253] 240: Lower column ADC

[0254] 250: Logic Circuits

[0255] 251, 271: Correction value calculation section

[0256] 252, 272: Black Level Correction Section

[0257] 253, 273: Subtractors

[0258] 254, 274: Correction coefficient holding section for each row

[0259] 255, 275: Vertical shadow correction section

[0260] 256, 276: Multipliers

[0261] 270: Lower logic circuit

[0262] 277: Adder

[0263] 280: Timing Control Department

[0264] 290: Dummy Circuit

[0265] 300: Pixel array section

[0266] 310: Effective pixel area

[0267] 320: Effective pixels

[0268] 321, 361: Reset transistors

[0269] 322, 362: Transmission transistors

[0270] 323, 363: Photodiodes

[0271] 324, 364, 291: Amplifying transistors

[0272] 325, 365: Floating diffusion layer

[0273] 326, 366, 292: Select transistors

[0274] 350, 390: OPB area

[0275] 360, 391: OPB pixels

[0276] 370: Upper OPB area

[0277] 380: Lower OPB area

[0278] 12101: Camera Department

Claims

1. A light detection device, comprising: Multiple pixels, arranged in rows and columns, including a first group of pixels and a second group of pixels, wherein the first group of pixels is optically shielded and the second group of pixels is configured to receive light; Multiple signal lines, including a first signal line, a second signal line, and a third signal line, wherein the first signal line is connected to a first pixel of a first group of pixels, the second signal line is connected to a second pixel of a second group of pixels, and the third signal line is connected to a third pixel of the first group of pixels; as well as A plurality of AD converters, including a first AD converter, a second AD converter and a third AD converter, wherein the first AD converter is configured to receive a first signal via a first signal line, the second AD converter is configured to receive a second signal via a second signal line, and the third AD converter is configured to receive a third signal via a third signal line; Wherein, the first group of pixels is located at the edge of the second group of pixels, and the first pixel and the second pixel are in the first column, and The second signal is corrected based on the first signal and the third signal.

2. The optical detection device according to claim 1, wherein... The second AD converter is located between the first AD converter and the third AD converter.

3. The optical detection device according to claim 2, wherein... The plurality of signal lines further includes a fourth signal line, which is connected to the fourth pixel of the second group of pixels, and The plurality of AD converters also includes a fourth AD converter configured to receive a fourth signal via the fourth signal line.

4. The optical detection device according to claim 3, wherein... The third AD converter is located between the second AD converter and the fourth AD converter.

5. The optical detection device according to claim 1, wherein... The number of columns in the second group of pixels is less than the number of AD converters in the plurality of AD converters.

6. The optical detection device according to claim 1, wherein... The first group of pixels is located above and below the second group of pixels, and The plurality of AD converters includes a first plurality of AD converters and a second plurality of AD converters, the first plurality of AD converters being configured to receive signals from the first group of pixels on the upper side, and the second plurality of AD converters being configured to receive signals from the first group of pixels on the lower side.

7. The optical detection device according to claim 1, wherein... The first group of pixels and the second group of pixels simultaneously output the same predetermined number of signals.

8. A light detection device, comprising: A first substrate, the first substrate comprising: Multiple pixels, arranged in rows and columns, comprising a first group of pixels and a second group of pixels, the first group of pixels being optically shielded and the second group of pixels being configured to receive light; and Multiple signal lines, including a first signal line and a second signal line, wherein the first signal line is connected to a first pixel of the first group of pixels, and the second signal line is connected to a second pixel of the second group of pixels; and A second substrate is stacked on the first substrate. The second substrate includes a plurality of AD converters, including a first AD converter and a second AD converter. The first AD converter is configured to receive a first signal via the first signal line, and the second AD converter is configured to receive a second signal via the second signal line. Wherein, the first group of pixels is located at the edge of the second group of pixels, and the first pixel and the second pixel are in the first column. The plurality of signal lines further includes a third signal line, which is connected to the third pixel of the first group of pixels, and The plurality of AD converters further includes a third AD converter configured to receive a third signal via the third signal line, and The second signal is corrected based on the first signal and the third signal.

9. The optical detection device according to claim 8, further comprising: A dummy circuit is configured to generate a reference signal for correcting the signal output from the second group of pixels.

10. The optical detection device according to claim 9, wherein... The dummy circuit is located on the second substrate.

11. The optical detection device according to claim 8, wherein... The second AD converter is located between the first AD converter and the third AD converter.

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