Schottky diode and method for preparing the same

Abstract

The present application relates to a Schottky diode and a method for fabricating a Schottky diode. The Schottky diode comprises an epitaxial layer, a first oxide layer, a barrier layer, a first metal layer, and a second metal layer. The epitaxial layer is provided with a PN junction, which divides the epitaxial layer into a P region and an N region along the thickness of the epitaxial layer. The epitaxial layer is also provided with an annular groove, the open end of which is provided in the P region. The first oxide layer is provided on the side of the P region away from the N region and is located outside the annular shape of the annular groove. The barrier layer is provided on the side of the P region away from the N region and is located inside the annular shape of the annular groove. The first metal layer is provided on the side of the first oxide layer away from the epitaxial layer. The second metal layer is provided on the side of the barrier layer away from the epitaxial layer. A filling structure is provided within the groove of the annular groove. By providing the PN junction and the annular groove, the present application further improves the reverse breakdown voltage, effectively reduces reverse leakage current, and improves the reliability of high-temperature reverse bias.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a Schottky diode and a method for preparing the Schottky diode. Background Art

[0002] A Schottky diode is a hot carrier diode made using the principle of a metal-semiconductor junction formed by the contact between metal and semiconductor. It is also called a metal-semiconductor (contact) diode or a surface barrier diode.

[0003] Currently, Schottky diodes produced in wafer fabs experience premature device breakdown due to the steep electric field at the edge of the Schottky barrier, which creates a strong electric field in the depletion region. To address this issue, a P+ guard ring is often used for protection. However, the presence of the P+ guard ring requires the device to sacrifice some barrier area. Summary of the Invention

[0004] The purpose of the present application is to provide a Schottky diode and a method for preparing a Schottky diode, wherein the Schottky diode can increase the reverse breakdown voltage under the same epitaxial parameters.

[0005] To this end, in a first aspect, an embodiment of the present application provides a Schottky diode, comprising: an epitaxial layer, provided with a PN junction, the PN junction dividing the epitaxial layer into a P region and an N region along the thickness direction of the epitaxial layer, the epitaxial layer further provided with an annular groove, the open end of the annular groove being provided in the P region; a first oxide layer, provided on a side of the P region away from the N region, and located outside the annular shape of the annular groove; a barrier layer, provided on a side of the P region away from the N region, and located inside the annular shape of the annular groove; a first metal layer, provided on a side of the first oxide layer away from the epitaxial layer; a second metal layer, provided on a side of the barrier layer away from the epitaxial layer; and a filling structure, provided in the groove of the annular groove.

[0006] In a possible implementation, the depth of the annular groove is greater than the thickness of the P region.

[0007] In a possible implementation, the annular groove is rectangular, and the length of the annular groove is 600 μm-640 μm, and the width of the annular groove is 600 μm-640 μm.

[0008] In a possible implementation, the depth of the annular groove is 1.2 μm-1.8 μm, and the width of the inner cavity of the annular groove is 15 μm-30 μm.

[0009] In a possible implementation, the filling structure includes: a second oxide layer disposed on an inner cavity wall of the annular groove; and a third metal layer disposed in the annular groove, wherein the third metal layer is located on a surface of the second oxide layer.

[0010] In a possible implementation, the thickness of the second oxide layer is 3000 Å-5000 Å, and the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0011] In a possible implementation, the first metal layer, the second metal layer, and the third metal layer have the same thickness.

[0012] In a second aspect, an embodiment of the present application provides a method for preparing a Schottky diode, comprising the following steps: PN junction preparation, wherein P-type ions are implanted throughout the epitaxial layer by diffusion or ion implantation to form a PN junction, wherein the PN junction divides the epitaxial layer into a P region and an N region along the thickness direction of the epitaxial layer; preliminary oxidation, wherein the P region of the epitaxial layer is oxidized on the side away from the N region to form a primary thin film; slotting, wherein an annular groove is formed in the epitaxial layer; secondary oxidation, wherein the slotted epitaxial layer is subjected to secondary oxidation to form a secondary thin film located outside the annular groove. The primary thin film and the secondary thin film are stacked to form a first oxide layer, and the secondary thin film located in the inner cavity of the annular groove is a second oxide layer; photolithography, an alloy layer is formed on the surface of the epitaxial layer in the annular ring of the annular groove after photolithography, and a barrier layer is formed at a high temperature; sputtering barrier, a barrier layer is formed on the surface of the epitaxial layer in the annular ring of the annular groove after photolithography; electrode plating, a first metal layer is formed on the side of the first oxide layer away from the epitaxial layer, a second metal layer is formed on the side of the barrier layer away from the epitaxial layer, and a third metal layer is formed on the surface of the second oxide layer.

[0013] In a possible implementation, P-type ions are implanted or diffused at low temperature in vacuum, and the position of the PN junction is controlled at a high temperature of 1050° C. to 1100° C.

[0014] In a possible implementation, the depth of the annular groove is greater than the thickness of the P region.

[0015] According to an embodiment of the present application, a Schottky diode is provided, comprising an epitaxial layer, a first oxide layer, a barrier layer, a first metal layer, and a second metal layer. The epitaxial layer is provided with a PN junction, which divides the epitaxial layer into a P region and an N region along the thickness direction of the epitaxial layer. The epitaxial layer is also provided with an annular groove, the opening of which is provided in the P region. The first oxide layer is provided on the side of the P region away from the N region and is located outside the annular shape of the annular groove. The barrier layer is provided on the side of the P region away from the N region and is located inside the annular shape of the annular groove. The first metal layer is provided on the side of the first oxide layer away from the epitaxial layer. The second metal layer is provided on the side of the barrier layer away from the epitaxial layer. A filling structure is provided within the groove of the annular groove. The provision of the PN junction in this Schottky diode reduces the use of photolithography, thereby reducing production costs. Furthermore, the provision of the annular groove can change the electric field distribution of the barrier layer of the Schottky diode, weakening the effect of the metal field plate, thereby reducing the size of the metal field plate, increasing the barrier area, and reducing the forward conduction voltage. The present application further improves the reverse breakdown voltage by setting the PN junction and the annular groove, and at the same time can effectively reduce the reverse leakage current and improve the reliability of high-temperature reverse bias. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In addition, in the drawings, the same reference numerals are used for the same components, and the drawings are not drawn according to the actual scale.

[0017] Figure 1 A top view of a trench Schottky diode provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic structural diagram of a trench Schottky diode provided in an embodiment of the present application is shown;

[0019] Figure 3 A diagram showing simulation data of a reverse breakdown voltage test of a Schottky diode in the prior art of this application is shown;

[0020] Figure 4 A diagram showing simulation data of a reverse breakdown voltage test of a trench Schottky diode provided in an embodiment of the present application is shown;

[0021] Figure 5 A flow chart of a trench Schottky diode provided in an embodiment of the present application is shown.

[0022] Description of reference numerals:

[0023] 1. Epitaxial layer; 11. P region; 12. N region; 13. Annular groove; 2. First oxide layer; 3. Barrier layer; 4. First metal layer; 5. Second metal layer; 6. Filling structure; 61. Second oxide layer; 62. Third metal layer. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] like Figure 1 、 Figure 2 As shown, Figure 1 FIG. 1 shows a top view of a trench Schottky diode provided in an embodiment of the present application. Figure 2 The present invention provides a trench Schottky diode, comprising an epitaxial layer 1, a first oxide layer 2, a barrier layer 3, a first metal layer 4, a second metal layer 5, and a filling structure 6.

[0026] A semiconductor substrate layer is provided, and an N-type epitaxial layer 1 is formed on the surface of the semiconductor substrate layer. The substrate layer refers to a commercially available substrate wafer, such as single-crystal silicon. Epitaxial layer 1 refers to a single-crystalline thin film grown epitaxially on the commercially available substrate wafer. P-type ions, such as boron and / or indium, are then implanted or diffused through the thickness of epitaxial layer 1, thereby forming a PN junction through the thickness of epitaxial layer 1. The PN junction is formed by close contact between an N-type doped region and a P-type doped region. This contact interface is called a metallurgical junction interface. The PN junction divides epitaxial layer 1 into a P region 11 and an N region 12 along the thickness direction.

[0027] Reference Figure 1 、 Figure 2 The epitaxial layer 1 is further provided with an annular groove 13, which is open and has an open end located in the P region 11. The annular groove 13 divides the P region 11 into two regions, namely a first region and a second region. The first region is located inside the annular ring of the annular groove 13, and the second region is located outside the annular ring of the annular groove 13.

[0028] The first oxide layer 2 is arranged on the side of the P region 11 away from the N region 12, and is located outside the ring shape of the annular groove 13; the barrier layer 3 is arranged on the side of the P region 11 away from the N region 12, and is located inside the ring shape of the annular groove 13; the first metal layer 4 is arranged on the side of the first oxide layer 2 away from the epitaxial layer 1; the second metal layer 5 is arranged on the side of the barrier layer 3 away from the epitaxial layer 1; and the filling structure 6 is arranged in the groove of the annular groove 13.

[0029] The material of the first oxide layer 2 includes silicon dioxide, and the material of the first metal layer 4 includes aluminum used as an electrode. The first oxide layer 2 is arranged on the side of the P region 11 away from the N region 12, and is located outside the ring of the annular groove 13, that is, it is arranged in the second area of ​​the P region 11. The first metal layer 4 is arranged on the side of the first oxide layer 2 away from the epitaxial layer 1. The first metal layer 4, the first oxide layer 2 and the epitaxial layer 1 are stacked in sequence in the second area.

[0030] The barrier layer 3 includes metal silicide, which is formed by heating the metal and the epitaxial layer. The material of the second metal layer 5 includes aluminum used as an electrode. The barrier layer 3 is arranged on the side of the P region 11 away from the N region 12, and is located in the ring of the annular groove 13, that is, it is arranged in the first area of ​​the P region 11. The second metal layer 5 is arranged on the side of the barrier layer 3 away from the epitaxial layer 1. The second metal layer 5, the barrier layer 3 and the epitaxial layer 1 are stacked in sequence in the first area.

[0031] The present application forms a PN junction by implanting P-type ions across the entire surface. During the preparation process, the use of photomasks is reduced compared to the preparation of existing P+ rings, thereby reducing production costs. The provision of the annular groove 13 can change the electric field distribution of the Schottky diode barrier layer 3, weakening the effect of the metal field plate, thereby reducing the size of the metal field plate, increasing the barrier area, and reducing the forward conduction voltage. The present application further improves the reverse breakdown voltage through the provision of the PN junction and the annular groove 13, and at the same time can effectively reduce the reverse leakage current and improve the reliability of high-temperature reverse bias.

[0032] Furthermore, the depth of the annular groove 13 is greater than the thickness of the P region 11, that is, a portion of the annular groove 13 extends into the N region 12, so that part of the annular groove 13 is located in the P region 11 and part of it is located in the N region 12. If the depth of the annular groove 13 is not greater than the thickness of the P region 11, the effect of improving the reverse breakdown voltage is not significant and cannot meet the required product requirements.

[0033] In an alternative example, refer to Figure 1 、 Figure 2The annular groove 13 is rectangular, with a length of 600 μm to 640 μm and a width of 600 μm to 640 μm. The annular groove 13 can be rectangular or square in top view. In a single-cell chip, such as a conventional 28 mil chip, the length and width of the annular groove 13 are equal, i.e., a square configuration, and the circumferential angles of the annular groove 13 are arc angles. In one embodiment, in a dual-cell chip, the length and width of the annular groove 13 are unequal, i.e., a rectangular parallelepiped configuration.

[0034] The length of the annular groove 13 is 600μm-640μm, and the width of the annular groove 13 is 600μm-640μm, that is, the distance between the annular groove 13 and the two sides is between 600μm-640μm. However, the first area enclosed by the annular groove 13 is the active area. The area of ​​the active area of ​​the present application is larger than that of the existing active area. Therefore, the present application increases the area of ​​the active area without increasing the conventional chip size of 28mil, and reduces the forward conduction voltage without reducing the reverse breakdown voltage.

[0035] If the length and / or width of the annular groove 13 is less than 600 μm, the area of ​​the active region increases less than the existing area of ​​the active region, affecting the improvement of the reverse breakdown voltage. If the length and / or width of the annular groove 13 is greater than 640 μm, the position of the annular groove 13 will be partially located in the dicing path, causing chip performance failure.

[0036] In one example, the depth of the annular groove 13 is 1.2 μm to 1.8 μm, and the width of the inner cavity of the annular groove 13 is 15 μm to 30 μm. When the depth of the annular groove 13 is less than 1.2 μm, that is, the depth of the annular groove 13 is not greater than the thickness of the P region 11, the effect of improving the breakdown voltage is affected. When the depth of the annular groove 13 is greater than 1.8 μm, the filling and preparation of the filling structure 6 is affected, making the preparation of the filling structure 6 more difficult.

[0037] Furthermore, the filling structure 6 includes a second oxide layer 61 and a third metal layer 62 . The second oxide layer 61 is disposed on the inner wall of the annular groove 13 , and the third metal layer 62 is disposed on the surface of the third metal layer 62 .

[0038] The second oxide layer 61 is made of silicon dioxide, and the third metal layer 62 is made of aluminum. The second oxide layer 61 is disposed on the inner wall of the annular groove 13, that is, the second oxide layer 61 covers the bottom wall and side walls of the annular groove 13, and the second oxide layer 61 is connected to the first oxide layer 2. The third metal layer 62 is disposed in the annular groove 13, that is, the third metal layer 62 is located on the inner wall of the second oxide layer 61 facing away from the annular groove 13. The third metal layer 62 is connected to the first metal layer 4 and the second metal layer 5, respectively, and the thickness of the third metal layer 62, the first metal layer 4, and the second metal layer 5 are equal.

[0039] Reference Figure 3-Figure 4 , Figure 3 The figure shows the reverse breakdown voltage test simulation data of the Schottky diode in the prior art of this application. Figure 4 A reverse breakdown voltage test simulation data diagram of a trench Schottky diode provided in an embodiment of the present application is shown. Figure 3 The reverse breakdown voltage of the Schottky diode in the prior art is 48.5V. Figure 4 The reverse breakdown voltage of a Schottky diode in the embodiment of the present application is shown to be 62.4 V. The present application increases the reverse breakdown voltage by 13 V by providing a PN junction and providing a filling structure 6 in the annular groove 13, greatly improving the reverse breakdown voltage and improving the performance of the Schottky diode.

[0040] Furthermore, the thickness of the second oxide layer 61 is 3000A-5000A, and the thickness of the first oxide layer 2 is greater than the thickness of the second oxide layer 61. The second oxide layer 61 is provided with two opposite ends along its thickness, and the PN junction is located between the opposite ends of the second oxide layer 61. The thickness of the second oxide layer 61 is between 3000A-5000A. Compared with the existing oxide layer thickness of 300A-500A, the thickness of the second oxide layer 61 of the present application is increased tenfold. Because the epitaxial layer 1 is provided with the P region 11 and the N region 12, the PN junction is easily broken down. Therefore, the thickness of the second oxide layer 61 is between 3000A-5000A to prevent the PN junction from being broken down prematurely.

[0041] Refer to the figure, Figure 5 A flow chart of a trench Schottky diode provided in an embodiment of the present application is shown. The method for preparing the Schottky diode includes the following steps:

[0042] S1. Preparation of PN junction: P-type ions are implanted into the entire surface of the epitaxial layer 1 by diffusion or ion implantation to form a PN junction. The PN junction divides the epitaxial layer 1 into a P region 11 and an N region 12 along the thickness direction of the epitaxial layer 1.

[0043] S2, preliminary oxidation, oxidizing the side of the P region 11 of the epitaxial layer 1 away from the N region 12 to form a primary thin film;

[0044] S3, groove setting, forming an annular groove 13 on the epitaxial layer 1;

[0045] S4, secondary oxidation, performing secondary oxidation on the grooved epitaxial layer 1 to form a secondary thin film. The primary thin film and the secondary thin film located outside the annular groove 13 are stacked to form a first oxide layer 2, and the secondary thin film located in the inner cavity of the annular groove 13 is a second oxide layer 61;

[0046] S5, photolithography, removing the primary thin film and the secondary thin film at the epitaxial layer 1 located in the ring of the annular groove 13;

[0047] S6, sputtering a potential barrier to form an alloy layer on the surface of the epitaxial layer in the annular portion of the photoetched annular groove 13, thereby forming a potential barrier layer 3 at a high temperature;

[0048] S7, stripping the barrier, removing excess alloy at the barrier layer 3 by acidic solution;

[0049] S8. Electrode plating, forming a first metal layer 4 on the side of the first oxide layer 2 away from the epitaxial layer 1, forming a second metal layer 5 on the side of the barrier layer 3 away from the epitaxial layer 1, and forming a third metal layer 62 on the surface of the second oxide layer 61.

[0050] Specifically, before step S1, there is a small amount of oxide layer on the surface of the epitaxial layer 1. Before step S1, the small amount of oxide layer on the surface of the epitaxial layer 1 needs to be removed. In step S1, under vacuum and low temperature, P-type ions are injected or diffused along the thickness direction of the epitaxial layer 1. The P-type ions can be boron and / or indium. The injection or diffusion method at this time adopts the method of full-surface injection or diffusion. Compared with the traditional P+ ring setting, the present application reduces the use of photomasks.

[0051] The implantation of P-type ions divides the N-type epitaxial layer 1 into a P region 11 and an N region 12, forming a PN junction at the close contact between the P region 11 and the N region 12. However, the diffusion or implantation distance of the P-type ions can be controlled by using high temperatures. In this case, the high temperature is 1050°C-1100°C, which controls the specific location of the PN junction. During the initial oxidation process, the temperature is kept between 1050°C and 1100°C, allowing the location of the PN junction to be controlled simultaneously.

[0052] In step S2, preliminary oxidation is performed at a temperature of 1050°C-1100°C to oxidize a primary thin film on the surface of the epitaxial layer 1. The primary thin film is located on the side of the P region 11 away from the N region 12 and is made of silicon dioxide.

[0053] In step S3, the grooves are first cut out in the P region 11 of the epitaxial layer 1 to define the location of the annular groove 13. Then, the annular groove 13 is formed. The annular groove 13 is rectangular, and the circumference of the annular groove 13 is formed in the shape of a circular arc. The annular groove 13 divides the P region into a first region and a second region. The first region is located within the annular shape of the annular groove 13, and the second region is located outside the annular shape of the annular groove 13. Furthermore, the depth of the annular groove 13 is greater than the thickness of the P region 11.

[0054] In step S4, secondary oxidation is performed on the epitaxial layer 1 to form a secondary thin film. At this time, the secondary thin film in the second region is stacked with the primary thin film to form the first oxide layer 2, and the material of the first oxide layer 2 is silicon dioxide. The secondary thin film at the bottom wall and side wall of the annular groove 13 is the second oxide layer 61, and the material of the second oxide layer 61 is silicon dioxide. Because the first oxide layer 2 is stacked by the primary thin film and the secondary thin film, the second oxide layer 61 is formed by the secondary thin film. Therefore, the thickness of the second oxide layer 61 is less than the thickness of the first oxide layer 2.

[0055] Since the epitaxial layer 1 is provided with a PN junction, ie, it divides the P region 11 and the N region 12 , in order to prevent the PN junction from being broken down, the thickness of the second oxide layer 61 is between 3000 Å and 5000 Å.

[0056] In step S5, during photolithography, the secondary thin film and the primary thin film in the first region are removed to expose the epitaxial layer 1, which is convenient for the subsequent sputtering of the potential barrier.

[0057] In step S6, metal is sputtered on the epitaxial layer 1 after photolithography. Metal materials such as platinum, titanium, and nickel can be selected to form a barrier metal layer. The barrier metal layer is heated and alloyed. Under heating conditions, some metal particles in the barrier metal layer diffuse into the epitaxial layer 1 to form a barrier layer 3.

[0058] In step S7, excess metal at the barrier layer 3 is removed by pickling to facilitate subsequent electrode plating.

[0059] In step S8, when plating the electrode, aluminum is selected as the material, and a first metal layer 4 is formed in the second region. The first metal layer 4 is located on the side of the first oxide layer 2 away from the epitaxial layer 1. A second metal layer 5 is formed in the first region. The second metal layer 5 is located on the side of the barrier layer 3 away from the epitaxial layer 1. A third metal layer 62 is formed in the annular groove 13. The third metal layer 62 is located on the surface of the second oxide layer 61. The thickness of the first metal layer 4, the second metal layer 5, and the third metal layer 62 are equal, and the first metal layer 4 and the second metal layer 5 are connected through the third metal layer 62.

[0060] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0061] It should be readily understood that “on,” “above,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “above” or “over” includes not only the meaning of “above” or “over,” but also includes “above” or “over” with no intervening features or layers therebetween (i.e., directly on something).

[0062] Additionally, spatially relative terms, such as "below," "beneath," "beneath," "above," and the like, may be used herein for ease of description to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A Schottky diode, characterized in that: include: The epitaxial layer is provided with a PN junction, wherein the PN junction divides the epitaxial layer into a P region and an N region along the thickness direction of the epitaxial layer, and the epitaxial layer is further provided with an annular groove, wherein the opening end of the annular groove is provided in the P region; A first oxide layer is provided on a side of the P region away from the N region and outside the annular shape of the annular groove; a barrier layer, disposed on a side of the P region away from the N region and located within the annular shape of the annular groove; a first metal layer, disposed on a side of the first oxide layer away from the epitaxial layer; a second metal layer, disposed on a side of the barrier layer away from the epitaxial layer; A filling structure disposed within the groove of the annular groove; The filling structure comprises: a second oxide layer, disposed on the inner wall of the annular groove; as well as A third metal layer is disposed in the annular groove, and the third metal layer is located on the surface of the second oxide layer.

2. The Schottky diode according to claim 1, wherein: The depth of the annular groove is greater than the thickness of the P region.

3. The Schottky diode according to claim 2, wherein: The annular groove is rectangular, and the length of the annular groove is 600 μm-640 μm, and the width of the annular groove is 600 μm-640 μm.

4. The Schottky diode according to claim 3, characterized in that: The depth of the annular groove is 1.2 μm-1.8 μm, and the width of the inner cavity of the annular groove is 15 μm-30 μm.

5. The Schottky diode according to claim 1, wherein: The thickness of the second oxide layer is 3000Å-5000Å, and the thickness of the first oxide layer is greater than that of the second oxide layer.

6. The Schottky diode according to claim 1, characterized in that: The first metal layer, the second metal layer, and the third metal layer have the same thickness.

7. A method for preparing a Schottky diode, characterized in that: The following steps are involved: Preparation of a PN junction: P-type ions are implanted throughout the epitaxial layer by diffusion or ion implantation to form a PN junction. The PN junction divides the epitaxial layer into a P region and an N region along the thickness direction of the epitaxial layer. Preliminary oxidation: oxidizing the side of the P region of the epitaxial layer away from the N region to form a primary thin film; Grooving is provided to provide an annular groove on the epitaxial layer; Secondary oxidation: performing secondary oxidation on the grooved epitaxial layer to form a secondary thin film, wherein the primary thin film located outside the annular groove and the secondary thin film are stacked to form a first oxide layer, and the secondary thin film located in the inner cavity of the annular groove is a second oxide layer; Photolithography is used to remove the primary thin film and the secondary thin film at the epitaxial layer located in the annular portion of the annular groove; Sputtering a barrier to form an alloy layer on the surface of the epitaxial layer in the annular portion of the annular groove after photolithography, and forming a barrier layer at a high temperature; Stripping the barrier, removing excess alloy at the barrier layer by an acidic solution; Electrodes are plated to form a first metal layer on a side of the first oxide layer away from the epitaxial layer, a second metal layer on a side of the barrier layer away from the epitaxial layer, and a third metal layer on a surface of the second oxide layer.

8. The method for preparing a Schottky diode according to claim 7, wherein: When P-type ions are injected or diffused at low temperature in vacuum, and the position of the PN junction is controlled at a high temperature of 1050°C-1100°C.

9. The method for preparing a Schottky diode according to claim 7, wherein: The depth of the annular groove is greater than the thickness of the P region.

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