Rail-to-rail input-output operational transconductance amplifier based on low ripple charge pump

Abstract

The invention discloses an operational transconductance amplifier based on a low-ripple charge pump. The circuit structure design is simple and reasonable, and the voltage fluctuation flatness effect of the equivalent input transconductance can be improved, and the application requirements of a wide temperature range can be met. The operational transconductance amplifier comprises a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage which are connected in sequence. The differential transconductance input stage comprises a low-ripple charge pump, a first current mirror, and a differential pair. Two input ends of the low-ripple charge pump are respectively connected to an external input clock signal and a voltage source VDD. The output end of the low-ripple charge pump is connected to a first current mirror power supply end. The output of the first current mirror is connected to a differential pair source. The drain of the differential pair is connected to the differential-to-single-ended transimpedance stage. The first current mirror comprises PMOS tubes P9-P12 and a resistor R3. The differential pair comprises PMOS tubes P13 and P14. The output of the push-pull output stage is the current output end of the operational transconductance amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a rail-to-rail input operational transconductance amplifier based on a low-ripple charge pump. Background Art

[0002] The operational transconductance amplifier is a commonly used unit in analog CMOS integrated circuit design. It is used to convert the input differential voltage signal into an output current. Combined with its negative feedback network, it can realize various analog signal operations. It is often referred to as "op amp". In low-voltage analog circuit applications with limited signal swing, the input and output of the operational transconductance amplifier are often required to be rail-to-rail to obtain the maximum voltage signal swing, that is: (1) The common-mode input level of the designed operational transconductance amplifier can approximately span the entire range from the negative power supply voltage to the positive power supply voltage, that is, the input is rail-to-rail; (2) The output voltage swing of the designed operational transconductance amplifier approximately reaches the entire range from the negative power supply voltage to the positive power supply voltage, that is, the output is rail-to-rail.

[0003] In order to achieve the above two goals, the small signal parameters such as the equivalent input transconductance of the operational transconductance amplifier must be kept basically constant to ensure the stability of the operational amplifier under various working conditions. In addition, the dependence of the operational amplifier small signal parameters on the input voltage is the main source of nonlinearity. In the circuit structure of the operational transconductance amplifier with rail-to-rail input and output, the rail-to-rail output is realized by push-pull output (i.e., class AB amplifier). The main difference between the existing operational transconductance amplifiers is that the rail-to-rail input and the basically constant equivalent input transconductance are realized in different ways. However, most of the existing circuit structures of rail-to-rail input and basically constant equivalent input transconductance are complex, and the change of equivalent input transconductance can only be controlled within a small range.

[0004] At present, the solution to the small common-mode input range is to set up PMOS differential pairs and NMOS differential pairs at the same time, and expand the allowable common-mode input voltage range through the cooperation of the two pairs of differential pairs. However, in the actual working process, it is necessary to ensure that the opening and closing of the two pairs of differential pairs can be perfectly connected, which greatly increases the process difficulty. Therefore, the actual traditional rail-to-rail input stage usually needs to be coordinated with a triple current mirror: when the PMOS differential pair is turned off, the tail current of the PMOS differential pair is amplified three times and sent to the NMOS differential pair; when the NMOS differential pair is turned off, the tail current of the NMOS differential pair is amplified three times and sent to the PMOS differential pair. This can achieve an equivalent input transconductance that is approximately flat over the entire input voltage range, but the triple current mirror technology has the following disadvantages: (1) The equivalent input transconductance changes with the input voltage. When the triple current mirror is introduced, the fluctuation of the equivalent input transconductance can generally only be controlled within 15%, and the fluctuation flatness effect of the equivalent input transconductance is poor; (2) The triple current mirror technology causes the bias current of the input transconductance stage to change with the input voltage, making the design of the subsequent circuit more complicated. This problem is more serious in applications with a wide temperature range. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention provides a rail-to-rail input-output operational transconductance amplifier based on a low ripple charge pump, which has a simple and reasonable circuit structure design, can improve the voltage fluctuation flattening effect of the equivalent input transconductance, and can meet the application requirements of a wide temperature range.

[0006] To achieve the above object, the present invention adopts the following technical solution:

[0007] A rail-to-rail input-output operational transconductance amplifier based on a low-ripple charge pump comprises a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage connected in sequence.

[0008] The bias circuit is used to provide a bias voltage and a bias current;

[0009] The differential transconductance input stage is used to convert the differential input voltage into a differential current;

[0010] The differential-to-single-ended transimpedance stage is used to convert the differential current into a single-ended current;

[0011] The push-pull output stage converts the single-ended current into current output by a push-pull method;

[0012] It is characterized in that the differential transconductance input stage includes a charge pump, a first current mirror, and a differential pair. The charge pump is a low ripple charge pump. The charge pump is used to raise the voltage source VDD and power the first current mirror. The first current mirror is used to mirror the bias current generated by the bias circuit. The two input ends of the charge pump are respectively connected to the external input clock signal and the voltage source VDD. The output end of the charge pump is connected to the power supply end of the first current mirror. The output of the first current mirror is respectively connected to the source of the differential pair. The drain of the differential pair is connected to the differential-to-single-ended transimpedance stage. The output of the differential-to-single-ended transimpedance stage is connected to the input of the push-pull output stage. The first current mirror includes PMOS tubes P9 to P12. The differential pair includes PMOS tubes P13 and P14. The voltage output end of the charge pump is respectively connected to the differential pair and the bias circuit through the first current mirror.

[0013] It is further characterized in that

[0014] The low ripple charge pump comprises a PMOS tube N17, capacitors C3, C4, C5, single-stage charge pumps CP1 and CP2, wherein pin 1 of the single-stage charge pump CP1 is respectively connected to the voltage source VDD and the single-stage charge pump CP2, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C3 and the source of the PMOS tube N17, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C4, the drain of the PMOS tube N17 is connected to one end of the capacitor C5, the other ends of the capacitors C3, C4, and C5 are grounded, and pin 3 of the single-stage charge pumps CP1 and CP2 is connected to an external input clock signal;

[0015] The single-stage charge pump CP1 includes PMOS tubes P20, P21, P22, P23, NMOS tubes N18, N19, N20, N21, capacitors C6, C7, the PMOS tube P20 is connected to the gate of the NMOS tube N18 and the drain of the PMOS tube P21, the PMOS tube P21 is connected to the gate of the NMOS tube N19 and the drain of the PMOS tube P20, the sources of the NMOS tubes N18 and N19 are connected to the voltage source VDD, the sources of the PMOS tubes P20 and P21 are voltage output terminals, the sources of the NMOS tubes N18 and N19 are connected to the capacitors C6 and C7, and the gate of the NMOS tube N18 and N19 is connected to the gate of the NMOS tube N19 and the drain of the PMOS tube P20. One end of C6 and one end of C7 are connected in one-to-one correspondence, the other end of the capacitor C6 is respectively connected to the gates of the PMOS tubes P22, P23, and the NMOS tubes N20 and N21, the other end of the capacitor C7 is respectively connected to the drain of the PMOS tube P23 and the drain of the NMOS tube N21, the gate of the PMOS tube P22 and the gate of the NMOS tube N21 are connected to the external input clock signal, the source of the PMOS tubes P23 and P22 are respectively connected to the voltage source VDD, and the source of the NMOS tubes N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is consistent with the structure of the single-stage charge pump CP1;

[0016] The bias circuit includes a first bias voltage generating unit and a first switch unit. The first bias voltage generating unit is used to generate a bias voltage VB2. The first switch unit is used to control the conduction of the bias voltage and the bias current. The first bias voltage generating unit includes PMOS tubes P1 and P5. The first switch unit includes NMOS tubes N1-N4, N7-N10, and resistors R1 and R2. The input end of the first bias voltage generating unit is connected to a voltage source VDD, and the output end is connected to the first switch unit. At the same time, the voltage source VDD is connected in series with a resistor R1 and then connected to the first switch unit.

[0017] The differential-to-single-ended transimpedance stage includes a second bias voltage generating unit, a second current mirror, a second switch unit, a current buffer unit and a third switch unit. The second bias voltage generating unit is used to generate a first bias voltage VB. The second current mirror is used to mirror the bias current of the second bias voltage generating unit. The second switch unit and the third switch unit are used for conduction control. The current buffer unit is used to provide a push-pull voltage. The second bias voltage generating unit includes PMOS tubes P16 and P17. The second current mirror includes PMOS tubes P2, P3, P6 and P7. The second switch unit includes PMOS The third switch unit includes PMOS tubes P4 and P8, the current buffer unit includes NMOS tubes N5, N6, N11 and N12, the second bias voltage generating unit, the second current mirror and the input end of the third switch unit are all connected to the voltage source VDD and the input end of the charge pump, the outputs of the second bias voltage generating unit, the second current mirror and the third switch unit are connected to the second switch unit, the output of the second switch unit is connected to the input of the current buffer unit, and the output of the current buffer unit is connected to the control end of the push-pull output stage;

[0018] The push-pull output stage includes the PMOS tube P15, the NMOS tube N13, the capacitors C1 and C2, and the resistors R4 and R5. The drain of the PMOS tube P15 and the drain of the NMOS tube N13 are connected and are the output end OUT of the operational transconductance amplifier. The source of the NMOS tube N13 is grounded. The other end of the resistor R4 is connected in series with the capacitor C1 and then connected to the output end OUT. The other end of the resistor R5 is connected in series with the capacitor C2 and then connected to the output end OUT.

[0019] The above structure and method of the present invention can achieve the following beneficial effects: the present application sets a low ripple charge pump in the differential transconductance input stage of the operational transconductance amplifier. The low ripple charge pump has the characteristics of simple design and little influence by temperature changes. Therefore, a higher voltage power supply is provided for the first current mirror of the differential transconductance input stage through the low ripple charge pump, thereby solving the problem that the common mode input voltage range allowed by the differential transconductance input stage cannot reach rail-to-rail.

[0020] In addition, the output end of the charge pump is provided with a first current mirror, which can suppress the fluctuation of the charge pump output voltage, so that the bias current of the input stage is almost unaffected by the charge pump input clock signal. Therefore, it does not need to set a triple current mirror to meet the requirement of constant equivalent input transconductance of the differential transconductance input stage, that is, it does not need to design a complex additional auxiliary circuit structure to suppress voltage fluctuations, and can obtain constant transconductance, thereby simplifying the circuit structure. In addition, the setting of the low ripple charge pump and the first current mirror makes the bias current of the differential transconductance input stage not change with the change of the common-mode input voltage, which is conducive to simplifying the design of the subsequent circuit to adapt to a wide operating temperature range, thereby meeting the application requirements of a wide temperature range. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the circuit schematic diagram of two differential pairs in a traditional operational transconductance amplifier;

[0022] Figure 2 is a graph showing the equivalent input transconductance changing with the input voltage source VDD;

[0023] Figure 3 It is the circuit schematic diagram of the rail-to-rail input stage in the traditional operational transconductance amplifier;

[0024] Figure 4 is a circuit schematic diagram of an operational transconductance amplifier of the present invention;

[0025] Figure 5 is a circuit schematic diagram of a low ripple charge pump of the present invention;

[0026] Figure 6 It is a circuit schematic diagram of a single-stage charge pump CP1 / electrode charge pump CP2 in the low ripple charge pump of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above drawings are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0028] Operational transconductance amplifiers combined with negative feedback networks can realize various analog signal operations. Some applications of operational transconductance amplifiers (op amps) require that the input and output of the operational transconductance amplifier can achieve rail-to-rail. Traditional rail-to-rail input is mainly achieved by a pair of PMOS tube differential pairs and a pair of NMOS tube differential pairs. For example, Figure 1 As shown in the figure, when the voltage value of the input voltage source VDD (i.e., the voltage source VDD) is relatively low, the PMOS tube differential pair composed of MP10 and MP20 realizes the function of differential transconductance conversion; when the voltage value of the input voltage source VDD is relatively high, the NMOS tube differential pair composed of MN10 and MN20 realizes the function of differential transconductance conversion; if the input voltage source VDD is at an intermediate value, the two differential pairs will input transconductance at the same time, as shown in the figure. Figure 2 As shown, Figure 2 Middle longitudinal axis g m The horizontal axis represents the voltage of the voltage source VDD. Figure 2 It can be seen that the equivalent input transconductance varies greatly with the input voltage source VDD, unless the value of the power supply voltage just makes the closing of the NMOS tube differential pair and the opening of the PMOS tube differential pair perfectly connected, but the existing process cannot achieve this perfect connection.

[0029] The dependence of the op amp's small signal parameters on the input voltage source VDD is the main source of nonlinearity, so the traditional rail-to-rail input stage usually needs to be combined with a triple current mirror to achieve an approximately flat equivalent input transconductance over the entire input voltage range. The traditional rail-to-rail input stage implementation circuit is as follows: Figure 3 As shown, the triple current mirror includes PMOS tubes MP3 and MP5, MP1 and MP2, and NMOS tubes MN4 and MN5. The replication multiple of the current mirror is selected as three because the relationship between the transconductance of the MOS tube MP4 and its bias current is the square root relationship.

[0030] In summary, the traditional rail-to-rail input stage has the following defects: (1) The equivalent input transconductance changes with the input voltage source VDD. When a triple current mirror is introduced, the fluctuation of the equivalent input transconductance can generally only be controlled within 15%, which is an important source of nonlinearity.

[0031] (2) The triple current mirror technology makes the bias current of the input transconductance stage change with the input voltage, making the design of the subsequent circuit more complicated. This problem is more serious in applications with a wide temperature range. The reason is that the threshold voltage of PMOS and NMOS tubes has a large negative temperature coefficient. The threshold voltage of PMOS and NMOS tubes at 125℃ is 200-300mV lower than that at -50℃, but the change amplitude of the drain-source saturation voltage of PMOS and NMOS tubes with temperature is very small; at the same time, the carrier mobility of PMOS and NMOS tubes also has a negative temperature coefficient, that is, the higher the temperature, the lower the carrier mobility. Therefore, the above-mentioned traditional triple current mirror technology faces great challenges in applications with a wide temperature range.

[0032] Since carrier mobility decreases with increasing temperature, the design of integrated circuits with a wide temperature range generally adopts a constant transconductance bias technology, that is, the bias current has a positive temperature coefficient to compensate for the negative temperature coefficient of carrier mobility. The small signal transconductance of PMOS and NMOS tubes is the core parameter to pay attention to when designing circuits. Therefore, the positive temperature coefficient of the tail current source and the amplification effect of the triple current mirror lead to great challenges in the design of the current buffer stage that converts the differential current output from the first stage into a single-ended current in the traditional rail-to-rail operational amplifier: the gate bias voltage of the common-gate MOS tube must ensure that the common-gate tube works in the saturation region when the bias current is minimum (that is, the VGS of the differential-to-single-ended current mirror is minimum), and must ensure that the differential-to-single-ended current mirror fully works in the saturation region to ensure the gain of the operational amplifier. The above two requirements have opposite requirements on the gate bias voltage of the common-gate MOS tube, resulting in very small design space, and may even be unsolvable when considering complex process corners.

[0033] In order to solve the above problems and realize good operation of rail-to-rail input-output operational transconductance amplifier in a wide temperature range, the present invention provides the following technical solutions: Figure 4 , a rail-to-rail input and output operational transconductance amplifier based on a low ripple charge pump, which includes a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage connected in sequence. Among them, the bias circuit is used to provide bias voltage and bias current, the differential transconductance input stage is used to convert the differential component of the common-mode input voltage rail-to-rail input voltage into a differential current, the differential-to-single-ended transimpedance stage is used to convert the differential current into a single-ended voltage, and the push-pull output stage converts the voltage signal into a current output in a push-pull manner.

[0034] The differential transconductance input stage includes a low ripple charge pump, a first current mirror, and a differential pair. The low ripple charge pump boosts the voltage source VDD and supplies power to the first current mirror. The first current mirror is used to mirror the bias current in the bias circuit to provide the tail current required by the differential pair. The input end of the low ripple charge pump is respectively connected to the differential-to-single-ended transimpedance stage and the voltage source VDD. The output end of the low ripple charge pump is connected to the first current mirror, which is used to supply power to the first current mirror. The first current mirror is connected to the source of the differential pair, and the drain of the differential pair is connected to the differential-to-single-ended transimpedance stage. The first current mirror includes PMOS tubes P9 to P12, and the differential pair includes PMOS tubes P13 and PMOS tubes P14.

[0035] See Figure 5 The specific circuit structure of the low ripple charge pump is as follows: it includes an NMOS tube N17, capacitors C3, C4, C5, single-stage charge pumps CP1 and CP2, wherein pin 1 of the single-stage charge pump CP1 is respectively connected to a voltage source VDD and a single-stage charge pump CP2, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C3 and the source of the NMOS tube N17, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C4, the drain of the NMOS tube N17 is connected to one end of the capacitor C5, the other ends of the capacitors C3, C4, and C5 are grounded, and pin 3 of the single-stage charge pumps CP1 and CP2 are connected to an external input clock signal.

[0036] See Figure 6 The single-stage charge pump CP1 includes PMOS tubes P20, P21, P22, P23, NMOS tubes N18, N19, N20, N21, capacitors C6 and C7. The PMOS tube P20 is connected to the gate of the NMOS tube N18 and the drain of the PMOS tube P21. The PMOS tube P21 is connected to the gate of the NMOS tube N19 and the drain of the PMOS tube P20. The sources of the NMOS tubes N18 and N19 are connected to the voltage source VDD. The sources of the PMOS tubes P20 and P21 are voltage output terminals. The sources of the NMOS tubes N18 and N19 are connected to one end of the capacitors C6 and C7 in a one-to-one correspondence. , NMOS tubes N18 and N19 are independent substrate NMOS tubes with deep N wells, the other end of capacitor C6 is connected to the gates of PMOS tubes P22, P23, NMOS tubes N20 and N21 respectively, the other end of capacitor C7 is connected to the drain of PMOS tube P23 and the drain of NMOS tube N21 respectively, the gate of PMOS tube P22 and the gate of NMOS tube N21 are connected to the external input clock signal, the sources of PMOS tubes P23 and P22 are connected to the voltage source VDD respectively, and the sources of NMOS tubes N20 and N23 are grounded respectively; the structure of the single-stage charge pump CP2 is consistent with the structure of the single-stage charge pump CP1.

[0037] The low ripple charge pump circuit is a low ripple boost circuit. In the circuit, the capacitance values ​​of capacitors C3 to C5 (capacitance values ​​are in the order of pF) are very small to ensure the low ripple of the output voltage of the charge pump circuit, and the chip area occupied by small capacitors is small, which is conducive to saving the space occupied by the charge pump in the entire operational amplifier. When the input clock frequency (i.e., the frequency of the external input clock signal) is fixed, the output voltage ripple of the charge pump is related to the output capacitance and the load current. The larger the output capacitance, the smaller the load current and the smaller the output voltage ripple. The single-stage charge pump CP1 needs to provide output current to the voltage output terminal through the NMOS tube N17, so the output voltage ripple is large; the single-stage charge pump CP2 does not need to provide output current, so the output voltage ripple is very small. Since the NMOS tube N17 operates in the saturation region, as long as the output voltage ripple of the single-stage charge pump CP1 is not large enough to force the NMOS tube N17 to enter the linear region, the voltage ripple at the source end of the NMOS tube N17 (that is, the output end of the low-ripple charge pump) will remain very small, thereby ensuring that the voltage output of the low-ripple charge pump remains in a relatively stable low-ripple state (that is, a state with small voltage fluctuations), thereby reducing the negative effects brought about by the introduction of the charge pump (the need for a larger area to implement the capacitor, and the output voltage ripple affecting the operation of the main circuit of the operational amplifier through feedthrough) to a very low level.

[0038] The specific structure of the differential transconductance input stage is as follows: the sources of the PMOS tubes P9 and P10 are connected to the output end of the charge pump, the gate of the PMOS tube P9 is respectively connected to the gate of the PMOS tube P10, one end of the resistor R3, and the drain of the PMOS tube P11, the gate of the PMOS tube P11 is respectively connected to the gate of the PMOS tube P12, the other end of the resistor R3, and the drain of the NMOS tube N3 in the bias circuit, the drain of the PMOS tube P12 is respectively connected to the sources of the PMOS tubes P13 and P14, the drain of the PMOS tube P13 is respectively connected to the NMOS tubes N5 and N11 in the differential transconductance input stage, the drain of the PMOS tube P14 is respectively connected to the NMOS tubes N6 and N12 in the differential transconductance input stage, the gate of the PMOS tube P13 is the inverting input end, and the gate of the PMOS tube P14 is the non-inverting input end.

[0039] In this differential transconductance input stage, a low ripple charge pump converts the voltage source V DD The voltage is raised to about 2*V DD -V GSAfterwards, it is provided to the first current mirror, the input of the first current mirror is connected to the bias circuit, the output of the first current mirror is connected to the source of the differential pair, and the drain of the differential pair is connected to the transimpedance stage of the differential to single-end. A pair of input differential pairs (in this embodiment, a PMOS tube differential pair: PMOS tube P13, PMOS tube P14) is used as the input stage, and the current drawn by its tail current source (PMOS tube P10) comes from a low-ripple charge pump. Due to the local characteristics of the first current mirror, the local characteristics refer to that the input and output characteristics of the first current mirror have almost nothing to do with the ripple of the voltage source, because the source of the PMOS tube P9 and the source of the PMOS tube P10 are connected together. Even if there is external interference such as ripple, it is the various devices in the first current mirror that are interfered together, ensuring that the gate-source voltages of the PMOS tube P9 and the PMOS tube P10 are the same, so the output voltage ripple (i.e., voltage fluctuation) of the charge pump has almost no effect on the first current mirror including the PMOS tubes P9 and P10. The current provided by the tail current source (PMOS tube P10) is constant, and the current of the tail current source is determined by the reference current IREF and the size ratio of the mutually matched PMOS tube and NMOS tube. Therefore, the use of a charge pump can meet the requirements of the flatness of the equivalent input transconductance fluctuation, and the bias current of the input stage hardly changes with the change of the common-mode input voltage. In addition, due to the use of a low-ripple charge pump, the negative impact of the additional introduction of the charge pump in the present invention (requiring a larger area to realize the capacitor, and the output voltage ripple affects the operation of the main circuit of the operational amplifier through feedthrough) is also very low.

[0040] The low ripple charge pump and the first current mirror (including PMOS tubes P9-P12 and resistor R3) provide a tail current source for the input differential pair (including PMOS tubes P13 and P14). The first current mirror providing the tail current source here adopts a common source and common gate structure, which is conducive to ensuring the constant input bias current within the entire input voltage range; secondly, it prevents the PMOS tube P10 from carrying an excessive drain-source voltage in extreme cases to prevent damage to the device or reduce the life of the device.

[0041] The bias circuit includes a first bias voltage generating unit and a first switch unit. The first bias voltage generating unit is used to generate a bias voltage VB2. The first switch unit is used to control the conduction of the bias voltage and the bias current. The first bias voltage generating unit includes PMOS tubes P1 and P5. The first switch unit includes NMOS tubes N1-N4, N7-N10, and a resistor R1. The input end of the first bias voltage generating unit is connected to a voltage source VDD, and the output end is connected to the first switch unit. At the same time, the voltage source VDD is connected in series with a resistor R1 and then connected to the first switch unit. The specific structure of the bias circuit is as follows: the source of the PMOS tube P1 is respectively connected to the voltage source VDD, one end of the resistor R1, and the gates of the NMOS tubes N1 and N2; the drain of the PMOS tube P1 is respectively connected to the gate of the PMOS tube P1 and the source of the PMOS tube P5; the gate of the PMOS tube P5 is respectively connected to the gate of the PMOS tube P5 and the source of the NMOS tube N2; the other end of the resistor R1 is respectively connected to the source of the NMOS tube N1 and the gate of the NMOS tube N7; the gates of the NMOS tubes N1 to N4 are connected; the gates of the NMOS tubes N7 to N10 are connected; the sources of the NMOS tubes N1, N2, N3, and N4 are connected to the drains of the NMOS tubes N7, N8, N9, and N10 in a one-to-one correspondence; and the sources of the NMOS tubes N7, N8, N9, and N10 are grounded.

[0042] In the bias circuit, the voltage source VDD generates bias voltages VB2 and VB3 through PMOS tubes P1 and P5, and the same as the reference current I REF They act together on the control ends of the NMOS tubes N1-N4, N7-N10 in the first switch unit, and at the same time, the current through the PMOS tubes P16 and P17 is also transmitted to the NMOS tubes N1-N4, N7-N10, so that the NMOS tubes N1-N4, N7-N10 are turned on and work, thereby providing a driving voltage for the PMOS tubes P18 and P19 in the differential-to-single-ended transimpedance stage.

[0043] The differential-to-single-ended transimpedance stage includes a second bias voltage generating unit, a second current mirror, a second switch unit, a current buffer unit and a third switch unit. The second bias voltage generating unit is used to generate a first bias voltage VB, the second current mirror is used to mirror the bias current of the second bias voltage generating unit, the second switch unit and the third switch unit are used for conduction control, the current buffer unit is used to provide a push-pull voltage, the second bias voltage generating unit includes PMOS tubes P16 and P17, the second current mirror includes PMOS tubes P2, P3, P6 and P7, and the second switch unit includes PM OS tubes P18, P19, N16, N15, and N14, the third switch unit includes PMOS tubes P4 and P8, the current buffer unit includes NMOS tubes N5, N6, N11, and N12, the input ends of the second bias voltage generating unit, the second current mirror, and the third switch unit are all connected to the voltage source VDD and the input end of the charge pump, the outputs of the second bias voltage generating unit, the second current mirror, and the third switch unit are connected to the second switch unit, the output of the second switch unit is connected to the input of the current buffer unit, and the output of the current buffer unit is connected to the control end of the push-pull output stage.

[0044] The specific circuit structure of the differential-to-single-ended transimpedance stage is as follows: the sources of the PMOS tubes P2, P3, and P4 are respectively connected to the voltage source VDD, the input end of the charge pump, the other end of the capacitor C1, the source of the PMOS tube P16, and the source of the PMOS tube P15 in the push-pull output stage; the gates of the PMOS tubes P2, P3, and P4 are connected; the drains of the PMOS tubes P2 and P3 are connected to the sources of the PMOS tubes P6 and P7 one by one; the gates of the PMOS tubes P6, P7, and P8 are connected; the drain of the PMOS tube P6 is connected to the source of the PMOS tube P18; the gates of the PMOS tubes P17, P18, and P19 are connected; and the gates of the PMOS tubes P The source of 17 is respectively connected to the drain and gate of the PMOS tube P16, the drain of the PMOS tube P18 is respectively connected to the source of the NMOS tube N5 and the gates of the NMOS tubes N11 and N12, the gates of the NMOS tubes N5 and N6 are connected, the source of the NMOS tube N6 is respectively connected to the drain of the PMOS tube P19, the source of the NMOS tube N16, and the NMOS tube N13 in the push-pull output stage, the gate of the NMOS tube N16 is respectively connected to the gate of the NMOS tube N15 and the drain of the PMOS tube P8, the source of the PMOS tube P8 is connected to the drain of the PMOS tube P4, and the NMOS tubes N11, N12, and N14 are grounded.

[0045] In the differential-to-single-ended transimpedance stage, NMOS tubes N5, N6, N11, and N12 constitute the current buffer stage of the differential-to-single-ended transimpedance stage (i.e., the differential current-to-single-ended current transimpedance stage). The present invention only requires one, while the traditional rail-to-rail operational amplifier requires two when using a triple current mirror, one each at the top and bottom. Therefore, compared with the traditional rail-to-rail operational amplifier, the circuit structure of the present application is simplified. The current signal output by the NMOS tube N6 is converted into a voltage signal with approximately the same phase and amplitude at the drain of the NMOS tube N6 and the drain of the PMOS tube P7, and drives the NMOS tube N13 and the PMOS tube P15 in the subsequent push-pull output stage to conduct and output in a push-pull manner.

[0046] The push-pull output stage includes a PMOS transistor P15, an NMOS transistor N13, capacitors C1, C2, resistors R4, and R5. The drain of the PMOS transistor P15 and the drain of the NMOS transistor N13 are connected to form the output terminal OUT of the operational transconductance amplifier. The source of the NMOS transistor N13 is grounded. The other end of the resistor R4 is connected in series with the capacitor C1 and then connected to the output terminal OUT. The other end of the resistor R5 is connected in series with the capacitor C2 and then connected to the output terminal OUT.

[0047] The implementation condition of the rail-to-rail input of the present application is: the voltage source VDD of the entire circuit satisfies VDD>VGS+VGS P13-14 +2Vdsat, where VGS N17 Refers to the gate-source voltage of NMOS tube N17, VGS P13-14 Refers to the gate-source voltage of PMOS tubes P13 and P14, Vdsat refers to the drain-source saturation voltage drop of PMOS tubes P10 and P12 (assuming they are equal). If the voltage source VDD is small, the gate bias voltage of PMOS tubes P11 and P12 is made the same as the bias voltage of NMOS tubes N1 to N4, and reliable rail-to-rail input of the operational transconductance amplifier can be achieved. The current of the voltage source VDD is converted into voltage by the charge pump, and the converted voltage (or current) is mirrored to the PMOS tubes P1 and P5 under the action of the first current mirror (including PMOS tubes P9 to P12), so as to provide bias current for the subsequent circuit. Similarly, the current at the input end of the low ripple charge pump is mirrored to the PMOS tubes P4 and P8 through the second current mirror (including PMOS tubes P2, P3, P6, and P7), so as to provide current for the NMOS tubes N15, N16, and the PMOS tubes P18 and P19, so that the NMOS tubes N5, N6, N11, and N12 generate voltage push-pull, and drive the push-pull output stage to output current in a voltage push-pull manner, thereby realizing analog signal operation.

[0048] In the operational transconductance amplifier, the bias current of the differential input pair PMOS tubes P13 and P14 (transconductance stage) and the bias current of the current buffer stage for converting the differential current to a single-ended current come from the same reference current I REF, and the differential input pair can always work normally. The bias current does not change with the change of the common-mode input voltage, but only increases with the increase of temperature to compensate for the negative temperature coefficient of carrier mobility; from the perspective of voltage, when the temperature increases, the threshold voltage of the PMOS tube and the NMOS tube becomes smaller, but the overdrive voltage increases, which reduces the temperature coefficient of VGS, so there is sufficient design space for the bias voltage VB3.

[0049] The present invention is characterized in that the circuit is simple, and the setting of the low-ripple charge pump fundamentally solves the problem that the common-mode input voltage range allowed by the differential input stage of the traditional operational transconductance amplifier is small. Therefore, there is no need to introduce a large number of auxiliary circuits such as a triple current mirror; moreover, although the output voltage of the charge pump has a small ripple (voltage fluctuation), the influence of the voltage fluctuation is largely shielded by the first current mirror. Under the action of the low-ripple charge pump and the first current mirror, the common-mode input voltage range of the differential transconductance input stage is increased, and at the same time, the basic constant of the equivalent input transconductance and the basic constant of the input stage bias current are ensured, thereby improving the operating temperature range that the entire rail-to-rail input and output operational transconductance amplifier can adapt to.

[0050] In summary, the rail-to-rail input operational transconductance amplifier of the present invention has the following advantages:

[0051] (1) The main circuit part of the amplified signal follows the mature traditional structure, and the additional low-ripple charge pump only provides power for a set of current mirrors to generate the tail current source required for the rail-to-rail input stage. Therefore, the equivalent input transconductance is almost constant in the entire common-mode input voltage range, unlike the traditional rail-to-rail input and output operational transconductance amplifier, which requires a transconductance compensation circuit. Under the action of the charge pump, the bias current of the differential transconductance input stage hardly changes with the common-mode input voltage, so it has the characteristic of constant transconductance, and there is no need to design complex additional auxiliary circuits;

[0052] (2) The bias current of the differential transconductance input stage hardly changes with the common-mode input voltage, which helps to simplify the design of the subsequent circuit to meet the requirements of a wide operating temperature range;

[0053] (3) The charge pump works in the form of a switch and is less affected by temperature changes, which is further conducive to meeting application requirements over a wide temperature range;

[0054] (4) The low ripple charge pump utilizes the characteristics of the NMOS tube biased in the saturation region. With a 3 pF capacitor, the voltage fluctuation caused by the charge pump can be reduced to a very low level, thus reducing the cost of introducing an additional charge pump.

[0055] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. An input-output operational transconductance amplifier based on a low-ripple charge pump, comprising a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage connected in sequence; The bias circuit is used to provide a bias voltage and a bias current; The differential transconductance input stage is used to convert the differential input voltage into a differential current; The differential-to-single-ended transimpedance stage is used to convert the differential current into a single-ended current; The push-pull output stage converts the single-ended current into current and outputs it in a push-pull manner; It is characterized in that The differential transconductance input stage includes a low ripple charge pump, a first current mirror, and a differential pair. The low ripple charge pump is used to generate a voltage source higher than the voltage source VDD and to power the first current mirror. The first current mirror is used to mirror the bias current generated by the bias circuit. The two input ends of the low ripple charge pump are respectively connected to the external input clock signal and the voltage source VDD. The output end of the low ripple charge pump is connected to the power supply end of the first current mirror. The output of the first current mirror is connected to the source of the differential pair. The drain of the differential pair is connected to the differential-to-single-ended transimpedance stage. The output of the differential-to-single-ended transimpedance stage is connected to the input of the push-pull output stage. The first current mirror includes PMOS tubes P9 to P12 and a resistor R3. The differential pair includes PMOS tubes P13 and P14. The output end of the low ripple charge pump is respectively connected to the differential pair and the bias circuit through the first current mirror.

2. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 1, characterized in that: The low ripple charge pump includes a PMOS tube N17, capacitors C3, C4, C5, single-stage charge pumps CP1 and CP2, wherein pin 1 of the single-stage charge pump CP1 is respectively connected to the voltage source VDD and the single-stage charge pump CP2, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C3 and the source of the PMOS tube N17, pin 2 of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C4, the drain of the PMOS tube N17 is connected to one end of the capacitor C5, the other ends of the capacitors C3, C4, C5 are grounded, and pin 3 of the single-stage charge pumps CP1 and CP2 are connected to an external input clock signal.

3. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 2, characterized in that: The single-stage charge pump CP1 includes PMOS tubes P20, P21, P22, P23, NMOS tubes N18, N19, N20, N21, capacitors C6, C7, the PMOS tube P20 is connected to the gate of the NMOS tube N18 and the drain of the PMOS tube P21, the PMOS tube P21 is connected to the gate of the NMOS tube N19 and the drain of the PMOS tube P20, the sources of the NMOS tubes N18 and N19 are connected to the voltage source VDD, the sources of the PMOS tubes P20 and P21 are voltage output terminals, the sources of the NMOS tubes N18 and N19 are connected to the capacitors C6 and C7, and the gate of the NMOS tube N18 and N19 is connected to the gate of the NMOS tube N19 and the drain of the PMOS tube P20. One end of C6 and one end of C7 are connected in one-to-one correspondence, the other end of the capacitor C6 is respectively connected to the gates of the PMOS tubes P22, P23, and the NMOS tubes N20 and N21, the other end of the capacitor C7 is respectively connected to the drain of the PMOS tube P23 and the drain of the NMOS tube N21, the gate of the PMOS tube P22 and the gate of the NMOS tube N21 are connected to the external input clock signal, the source of the PMOS tubes P23 and P22 are respectively connected to the voltage source VDD, and the source of the NMOS tubes N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is consistent with the structure of the single-stage charge pump CP1.

4. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 3, characterized in that: The sources of the PMOS tubes P9 and P10 of the first current mirror are connected to the output end of the charge pump, the gate of the PMOS tube P9 is respectively connected to the gate of the PMOS tube P10, one end of the resistor R3, and the drain of the PMOS tube P11, the gate of the PMOS tube P11 is respectively connected to the gate of the PMOS tube P12, the other end of the resistor R3, and the drain of the NMOS tube N3 in the bias circuit, the drain of the PMOS tube P12 is respectively connected to the sources of the PMOS tubes P13 and P14, the drain of the PMOS tube P13 is respectively connected to the NMOS tubes N5 and N11 in the differential transconductance input stage, the drain of the PMOS tube P14 is respectively connected to the NMOS tubes N6 and N12 in the differential transconductance input stage, the gate of the PMOS tube P13 is the inverting input end, and the gate of the PMOS tube P14 is the non-inverting input end.

5. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 4, characterized in that: The bias circuit includes a first bias voltage generating unit and a first switch unit. The first bias voltage generating unit is used to generate a bias voltage VB2. The first switch unit is used to control the conduction of the bias voltage and the bias current. The first bias voltage generating unit includes PMOS tubes P1 and P5. The first switch unit includes NMOS tubes N1-N4, N7-N10, and resistors R1 and R2. The input end of the first bias voltage generating unit is connected to a voltage source VDD, and the output end is connected to the first switch unit. At the same time, the voltage source VDD is connected in series with a resistor R1 and then connected to the first switch unit.

6. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 5, characterized in that: The source of the PMOS tube P1 is respectively connected to the voltage source VDD, one end of the resistor R1, and the gates of the NMOS tubes N1 and N2; the drain of the PMOS tube P1 is connected to the source of the PMOS tube P5; the gate of the PMOS tube P5 is respectively connected to the source of the NMOS tube N2 and one end of the resistor R2; the other end of the resistor R2 is respectively connected to the drain of the PMOS tube P5 and the gate of the PMOS tube P1; the other end of the resistor R1 is respectively connected to the source of the NMOS tube N1 and the gate of the NMOS tube N7; the gates of the NMOS tubes N1 to N4 are connected; the gates of the NMOS tubes N7 to N10 are connected; the sources of the NMOS tubes N1, N2, N3, and N4 are connected to the drains of the NMOS tubes N7, N8, N9, and N10 in a one-to-one correspondence; and the sources of the NMOS tubes N7, N8, N9, and N10 are grounded.

7. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 6, characterized in that: The differential-to-single-ended transimpedance stage includes a second bias voltage generating unit, a second current mirror, a second switch unit, a current buffer unit, a third switch unit, and resistors R4 and R5. The second bias voltage generating unit is used to generate a first bias voltage VB. The second current mirror is used to mirror the bias current of the second bias voltage generating unit. The second switch unit and the third switch unit are used for conduction control. The current buffer unit is used to provide a push-pull voltage. The second bias voltage generating unit includes PMOS tubes P16 and P17. The second current mirror includes PMOS tubes P2, P3, P6, and P7. The second switch unit includes PMOS tubes P18, P19, N16, N15, and N14, the third switch unit includes PMOS tubes P4 and P8, the current buffer unit includes NMOS tubes N5, N6, N11, and N12, the input ends of the second bias voltage generating unit, the second current mirror, and the third switch unit are all connected to the voltage source VDD and the input end of the charge pump, the outputs of the second bias voltage generating unit, the second current mirror, and the third switch unit are connected to the second switch unit, the output of the second switch unit is connected to the input of the current buffer unit, and the output of the current buffer unit is connected to the control end of the push-pull output stage.

8. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 7, characterized in that: The sources of the PMOS tubes P2, P3, and P4 are respectively connected to the voltage source VDD, the input end of the charge pump, the source of the PMOS tube P16, and the source of the PMOS tube P15 in the push-pull output stage. The gates of the PMOS tubes P2, P3, and P4 are connected. The drains of the PMOS tubes P2 and P3 are connected to the sources of the PMOS tubes P6, P7, and P8 in a one-to-one correspondence. The gates of the PMOS tubes P6, P7, and P8 are connected. The drain of the PMOS tube P6 is connected to the source of the PMOS tube P18. The gates of the PMOS tubes P17, P18, and P19 are connected. The source of the PMOS tube P17 is respectively connected to the drain and gate of the PMOS tube P16. The drain of the PMOS tube P18 is respectively connected to the drain and gate of the PMOS tube P16. The gates of the NMOS tubes N5 and N6 are connected to each other. The source of the NMOS tube N6 is connected to the drain of the PMOS tube P19, the source of the NMOS tube N16, the gate of the NMOS tube N13 in the push-pull output stage, and one end of the resistor R5. The gate of the NMOS tube N16 is connected to the gate of the NMOS tube N15 and the drain of the PMOS tube P8. The source of the PMOS tube P8 is connected to the drain of the PMOS tube P4. The drain of the PMOS tube P7 is connected to one end of the resistor R4, the source of the PMOS tube P19, and the drain of the NMOS tube N6. The NMOS tubes N11, N12, and N14 are grounded.

9. The input-output operational transconductance amplifier based on a low ripple charge pump according to claim 8, characterized in that: The push-pull output stage includes the PMOS tube P15, the NMOS tube N13, the capacitors C1 and C2, and the resistors R4 and R5. The drain of the PMOS tube P15 and the drain of the NMOS tube N13 are connected and are the output end OUT of the operational transconductance amplifier. The source of the NMOS tube N13 is grounded. The other end of the resistor R4 is connected in series with the capacitor C1 and then connected to the output end OUT. The other end of the resistor R5 is connected in series with the capacitor C2 and then connected to the output end OUT.

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