A homogeneous phase method for multi-phase switching circuit and multi-phase switching circuit

Abstract

The present invention discloses a homogeneous method of a multi-phase switching circuit and a multi-phase switching circuit, wherein the multi-phase switching circuit comprises an n-phase switching circuit, wherein n-phase clock signals with equal frequencies and equal phase differences are respectively used as clock signals of the n-phase switching circuit, and an m-th adjustment signal is obtained according to a first-phase clock signal, a first-phase switching signal, an m-th phase clock signal and an m-th phase switching signal; the m-th adjustment signal is used to adjust the switching signal of the next switching cycle of the m-th phase, so that the time difference between the m-th phase switching signal and the m-th phase clock signal and the time difference between the first-phase switching signal and the first-phase clock signal are equal, thereby making the phase difference of the n-phase switching signals equal; wherein n is an integer greater than 1, and m is an integer from 2 to n. The present application can achieve equal phase difference of the switching signals of each phase of the multi-phase switching circuit and small output ripple.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a homogeneous phase method of a multi-phase switching circuit and a multi-phase switching circuit. Background Art

[0002] The parallel connection of multi-phase switching circuits can easily increase the power supply current level to meet the needs of large currents. At the same time, by controlling the staggered conduction of each phase switch circuit, the input and output current ripple can be reduced while reducing the inductance of the single-phase switch circuit, which can effectively reduce the input and output capacitance. In a multi-phase switching circuit, an n-phase clock signal with equal frequency and equal phase difference is generally used as the clock signal of the n-phase switch circuit. Ideally, the frequency of each phase switch signal should also be equal and the phase difference should be equal, but the actual situation is that it is difficult to ensure that the inductance values ​​of the inductors of each phase switch circuit are completely equal, which will lead to unequal phase differences of the switch signals of each phase, resulting in an unbalanced system and large output ripple.

[0003] Taking a two-phase switching circuit as an example, Figure 1 The upper limit voltage Vtop and the first inductor current sampling signal i of the two-phase switch circuit in the prior art are shown. L1 , the first lower limit voltage Vbot1, the second inductor current sampling signal i L2 , the second lower limit voltage Vbot2, the first phase clock signal CLK1, the first phase switch signal PWM1, the second phase clock signal CLK2 and the second phase switch signal PWM2 waveform diagram, wherein the first phase clock signal CLK1 and the second phase clock signal CLK2 are the clock signals of the first phase switch circuit and the second phase switch circuit respectively, and the two have equal frequencies and equal phase differences. The first phase switch signal PWM1 and the second phase switch signal PWM2 respectively control the conduction and shutdown of the main switch tubes of the first phase switch circuit and the second phase switch circuit. The upper limit voltage Vtop and the first lower limit voltage Vbot1 respectively control the first inductor current sampling signal i of the first phase switch circuit L1 The upper limit voltage Vtop and the second lower limit voltage Vbot2 respectively control the second inductor current sampling signal i of the second phase switching circuit L2 Ideally, the inductance of the first-phase switching circuit inductor and the second-phase switching circuit inductor are equal, and accordingly, the second inductor current sampling signal i L2 The change speed of (dashed line) and the first inductor current sampling signal i L1The change speed is consistent, and the ideal time difference t2′ between the second-phase switching signal PWM2 (dashed line) and the second-phase clock signal CLK2 is equal to the time difference t1 between the first-phase switching signal PWM1 and the first-phase clock signal CLK1. In actual situations, taking the inductance value of the second-phase switching circuit inductor as an example, the corresponding second inductor current sampling signal i L2 The change speed of (solid line) is slower than that of the first inductor current sampling signal i L1 The actual time difference t2 between the second-phase switching signal PWM2 (solid line) and the second-phase clock signal CLK2 will be greater than the time difference t1 between the first-phase switching signal PWM1 and the first-phase clock signal CLK1, that is, the phase difference between the two-phase switching signals will be unequal. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a phase-homogenizing method for a multi-phase switching circuit and a multi-phase switching circuit, so as to solve the technical problem of unequal phase differences of switching signals of each phase of a multi-phase switching circuit existing in the prior art.

[0005] The technical solution of the present invention is to provide a homogeneous phase method of a multi-phase switching circuit, wherein the multi-phase switching circuit includes an n-phase switching circuit, including:

[0006] n-phase clock signals with equal frequency and equal phase difference are respectively used as clock signals of the n-phase switching circuits;

[0007] Obtaining an mth adjustment signal according to the first phase clock signal, the first phase switch signal, the mth phase clock signal and the mth phase switch signal;

[0008] Using the mth adjustment signal to adjust the switch signal of the next switch cycle of the mth phase, so that the time difference between the mth phase switch signal and the mth phase clock signal is equal to the time difference between the first phase switch signal and the first phase clock signal, thereby making the phase difference of the n-phase switch signals equal;

[0009] Herein, n is an integer greater than 1, and m is an integer from 2 to n.

[0010] Optionally, the method for obtaining the mth adjustment signal according to the first phase clock signal, the first phase switch signal, the mth phase clock signal and the mth phase switch signal further comprises:

[0011] Obtaining a first signal representing a first time difference according to the first phase clock signal and the first phase switch signal, obtaining an mth signal representing an mth time difference according to the mth phase clock signal and the mth phase switch signal, and obtaining the mth adjustment signal according to the first signal and the mth signal;

[0012] Among them, the first time difference is the period from when the first phase clock signal is effective to when the first phase switch signal jumps to effective; the mth time difference is the period from when the mth phase clock signal is effective to when the mth phase switch signal jumps to effective.

[0013] Optionally, when the first phase clock signal indicates validity, the first signal jumps to validity; when the first phase switch signal jumps to validity, the first signal jumps to invalidity;

[0014] When the m-th phase clock signal indicates validity, the m-th signal jumps to validity; when the m-th phase switch signal jumps to validity, the m-th signal jumps to invalidity.

[0015] Optionally, the method for obtaining the mth adjustment signal according to the first signal and the mth signal further includes:

[0016] When the mth signal is valid, charging the first capacitor using the first current source;

[0017] When the first signal is valid, using a second current source to discharge the first capacitor;

[0018] Filtering the voltage of the first capacitor by using a filter to obtain the mth adjustment signal;

[0019] The currents output by the first current source and the second current source are equal in magnitude.

[0020] Optionally, the mth lower limit voltage controls the valley value of the inductor current of the mth phase switching circuit. When the valley value of the mth inductor current sampling signal representing the inductor current of the mth phase switching circuit reaches the mth lower limit voltage, the mth phase switching signal jumps from invalid to valid, and the main switch tube of the mth phase switching circuit is turned on; the mth lower limit voltage is reset to the mth starting value before the mth phase clock signal represents validity, and starts to rise when the mth phase clock signal represents validity.

[0021] Optionally, the mth starting value is adjusted using the mth adjustment signal to adjust the mth lower limit voltage, thereby adjusting the switching signal of the next switching cycle of the mth phase.

[0022] Optionally, the mth regulating signal is used to adjust the slope of the mth lower limit voltage when it rises, so as to adjust the mth lower limit voltage, thereby adjusting the switching signal of the next switching cycle of the mth phase.

[0023] Optionally, the homogeneous method further comprises:

[0024] Obtaining an upper limit voltage according to an output feedback signal of the multi-phase switch circuit to control the peak value of the inductor current of the n-phase switch circuit;

[0025] The mth starting value is equal to the sum of the difference between the upper limit voltage and a bias voltage and the mth adjustment signal.

[0026] Optionally, the homogeneous method further comprises:

[0027] Obtaining an upper limit voltage according to an output feedback signal of the multi-phase switch circuit to control the peak value of the inductor current of the n-phase switch circuit;

[0028] The mth starting value is equal to a difference between the upper limit voltage and a bias voltage.

[0029] On the other hand, the present invention further provides a multi-phase switching circuit, the multi-phase switching circuit comprising an n-phase switching circuit, n-phase clock signals with equal frequency and equal phase difference serving as clock signals of the n-phase switching circuit, the multi-phase switching circuit comprising:

[0030] a uniform phase control circuit, receiving the n-phase clock signal and the n-phase switch signal to output an n-1-phase adjustment signal, wherein an m-th adjustment signal is output according to the 1st phase clock signal, the 1st phase switch signal, the m-th phase clock signal and the m-th phase switch signal;

[0031] an m-th switching signal generating circuit, configured to output an m-th phase switching signal, and to adjust the switching signal of the m-th phase in the next switching cycle according to the m-th adjustment signal, so that the time difference between the m-th phase switching signal and the m-th phase clock signal is equal to the time difference between the first phase switching signal and the first phase clock signal, thereby making the phase difference of the n-phase switching signals equal;

[0032] Herein, n is an integer greater than 1, and m is an integer from 2 to n.

[0033] Optionally, the homogeneous control circuit includes a first logic circuit and an mth logic circuit,

[0034] The first logic circuit obtains a first signal representing a first time difference according to the first phase clock signal and the first phase switch signal; the mth logic circuit obtains an mth signal representing an mth time difference according to the mth phase clock signal and the mth phase switch signal;

[0035] Among them, the first time difference is the period from when the first phase clock signal is effective to when the first phase switch signal jumps to effective; the mth time difference is the period from when the mth phase clock signal is effective to when the mth phase switch signal jumps to effective.

[0036] Optionally, the homogeneous control circuit comprises:

[0037] The mth regulating circuit receives the first signal and the mth signal to output the mth regulating signal, wherein when the mth time difference is greater than the first time difference, the mth regulating signal increases; when the mth time difference is less than the first time difference, the mth regulating signal decreases.

[0038] Optionally, when the first phase clock signal indicates validity, the first signal jumps to validity; when the first phase switch signal jumps to validity, the first signal jumps to invalidity;

[0039] When the m-th phase clock signal indicates validity, the m-th signal jumps to validity; when the m-th phase switch signal jumps to validity, the m-th signal jumps to invalidity.

[0040] Optionally, the mth regulating circuit includes an mth voltage regulating circuit and an mth filter,

[0041] The mth voltage regulation circuit comprises a first current source, a second current source, a first switch, a second switch and a first capacitor, wherein a first end of the first switch tube is connected to the first current source, a second end is connected to a first end of the first capacitor, a control end receives the mth signal, when the mth signal is valid, the first switch tube is turned on, and the first current source charges the first capacitor; a first end of the second switch tube is connected to a first end of the first capacitor, and a second end is connected to the second current source, a control end receives the first signal, when the first signal is valid, the second switch tube is turned on, and the second current source discharges the first capacitor; a second end of the first capacitor is grounded, and a first end is used as an output end of the mth voltage regulation circuit to output the mth voltage regulation signal;

[0042] The mth filter receives the mth voltage regulation signal, and filters the mth voltage regulation signal to output the mth regulation signal;

[0043] The currents output by the first current source and the second current source are equal in magnitude.

[0044] Optionally, the mth switch signal generating circuit includes:

[0045] The mth lower limit voltage generating circuit is used to output the mth lower limit voltage, the mth lower limit voltage controls the valley value of the inductor current of the mth phase switching circuit, the mth lower limit voltage is reset to the mth starting value before the mth phase clock signal is valid, and starts to rise when the mth phase clock signal is valid.

[0046] Optionally, the mth lower limit voltage generating circuit receives the mth signal and the mth adjustment signal to output the mth lower limit voltage, and when the mth signal jumps to invalid, the mth lower limit voltage is reset to the mth starting value; when the mth signal jumps to valid, the mth lower limit voltage starts to rise.

[0047] Optionally, the mth lower limit voltage generating circuit includes:

[0048] A first adder, having a first input terminal receiving a difference between an upper limit voltage and a bias voltage, a second input terminal receiving the mth adjustment signal, and performing an addition operation on the difference between the upper limit voltage and a bias voltage and the mth adjustment signal to output the mth starting value;

[0049] The mth slope generating circuit receives the mth starting value and the mth signal to output the mth lower limit voltage.

[0050] Optionally, the mth lower limit voltage generating circuit includes:

[0051] A second adder, a first input terminal receiving a first voltage, a second input terminal receiving the mth adjustment signal, performing an addition operation on the first voltage and the mth adjustment signal to output an mth voltage;

[0052] The mth slope generating circuit receives the mth voltage and the mth signal to output the mth lower limit voltage, the slope of the mth lower limit voltage when rising is related to the mth voltage, and the mth starting value is equal to the difference between the upper limit voltage and a bias voltage.

[0053] Optionally, the multi-phase switching circuit further includes:

[0054] The upper limit voltage generating circuit outputs the upper limit voltage according to the output feedback signal of the multi-phase switching circuit to control the peak value of the inductor current of the n-phase switching circuit.

[0055] Optionally, the multi-phase switching circuit further includes a first switching signal generating circuit, configured to output the first phase switching signal, wherein the first switching signal generating circuit includes:

[0056] The first lower limit voltage generating circuit receives the first signal to output the first lower limit voltage to control the valley value of the inductor current of the first phase switching circuit. The first lower limit voltage is reset to the first starting value before the first phase clock signal is valid, and starts to rise when the first phase clock signal is valid.

[0057] Optionally, the mth switch signal generating circuit further includes:

[0058] An mth upper comparator compares an mth inductor current sampling signal representing the inductor current of the mth phase switch circuit with the upper limit voltage, and when the main switch tube of the mth phase switch circuit is turned on, the mth inductor current sampling signal is greater than or equal to the upper limit voltage, and the output voltage of the mth upper comparator is reversed;

[0059] an mth lower comparator, comparing the mth inductor current sampling signal with the mth lower limit voltage, and when the main switch tube of the mth phase switch circuit is turned off, the mth inductor current sampling value is less than or equal to the mth lower limit voltage, and the output voltage of the mth lower comparator is reversed;

[0060] A trigger receives the output voltages of the mth upper comparator and the mth lower comparator to output the mth phase switching signal, wherein the mth phase switching signal controls the on and off of the main switch tube of the mth phase switching circuit.

[0061] Compared with the prior art, the present invention has the following advantages: by adopting the homogeneous phase method and the multi-phase switching circuit provided by the present invention, the phase difference of the switching signals of each phase of the multi-phase switching circuit can be equal, the system is more balanced, and the output ripple is smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is the upper limit voltage Vtop of the two-phase switch circuit in the prior art, the first inductor current sampling signal i L1 , the first lower limit voltage Vbot1, the second inductor current sampling signal i L2 , schematic waveform diagrams of the second lower limit voltage Vbot2, the first phase clock signal CLK1, the first phase switching signal PWM1, the second phase clock signal CLK2 and the second phase switching signal PWM2;

[0063] Figure 2 The upper limit voltage Vtop and the first inductor current sampling signal i of the two-phase switch circuit in a homogeneous mode of the present invention are L1 , the first lower limit voltage Vbot1, the second inductor current sampling signal i L2 , schematic waveform diagrams of the second lower limit voltage Vbot2, the first phase clock signal CLK1, the first phase switching signal PWM1, the second phase clock signal CLK2 and the second phase switching signal PWM2;

[0064] Figure 3 is the upper limit voltage Vtop of the two-phase switch circuit in another homogeneous mode of the present invention, the first inductor current sampling signal i L1 , the first lower limit voltage Vbot1, the second inductor current sampling signal i L2, schematic waveform diagrams of the second lower limit voltage Vbot2, the first phase clock signal CLK1, the first phase switching signal PWM1, the second phase clock signal CLK2 and the second phase switching signal PWM2;

[0065] Figure 4 A schematic diagram of the circuit principle of a multi-phase switching circuit according to an embodiment of the present invention;

[0066] Figure 5 is a circuit structure diagram of an embodiment of the mth regulating circuit of the present invention;

[0067] Figure 6 Schematic diagram of the circuit structure of an embodiment of the mth switch signal generating circuit and the first switch signal generating circuit of the present invention;

[0068] Figure 7 Schematic diagram of the circuit structure of an mth lower limit voltage generating circuit and a first lower limit voltage generating circuit according to an embodiment of the present invention;

[0069] Figure 8 Schematic diagram of the circuit structure of an mth lower limit voltage generating circuit and a first lower limit voltage generating circuit according to another embodiment of the present invention;

[0070] Fig. 9 The figure is a circuit structure diagram of an embodiment of an upper limit voltage generating circuit of the present invention. DETAILED DESCRIPTION

[0071] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made within the spirit and scope of the present invention.

[0072] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without these detailed descriptions.

[0073] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and not in exact proportion, and are only used for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0074] Figure 2 and Figure 3 The upper limit voltage Vtop and the first inductor current sampling signal i of the two-phase switch circuit in two homogeneous modes of the present invention are shown. L1 , the first lower limit voltage Vbot1, the second inductor current sampling signal i L2, the second lower limit voltage Vbot2, the first phase clock signal CLK1, the first phase switch signal PWM1, the second phase clock signal CLK2 and the second phase switch signal PWM2. The first phase clock signal CLK1 and the second phase clock signal CLK2 are the clock signals of the first phase switch circuit and the second phase switch circuit respectively, and the frequencies of the two are equal and the phase difference is equal. The upper limit voltage Vtop is obtained by controlling the first inductor current sampling signal i L1 and the second inductor current sampling signal i L2 The peak value is used to control the peak value of the inductor current of the first phase switching circuit and the second phase switching circuit. When the first inductor current sampling signal i L1 When the peak value of the inductor current sampling signal i reaches the upper limit voltage Vtop, the first phase switch signal PWM1 changes from valid to invalid, and the main switch of the first phase switch circuit is turned off; when the second inductor current sampling signal i L2 When the peak value reaches the upper limit voltage Vtop, the second phase switch signal PWM2 changes from valid to invalid, and the main switch of the second phase switch circuit is turned off. The first lower limit voltage Vbot1 is generated by controlling the first inductor current sampling signal i L1 The valley value of the inductor current of the first phase switching circuit is controlled by the valley value of the inductor current. When the first inductor current sampling signal i L1 When the valley value of the first phase clock signal reaches the first lower limit voltage Vbot1, the first phase switch signal PWM1 changes from invalid to valid, and the first phase switch circuit main switch tube is turned on; the first lower limit voltage Vbot1 is reset to the first starting value before the first phase clock signal is valid, and starts to rise when the first phase clock signal is valid. The second lower limit voltage Vbot2 is generated by controlling the second inductor current sampling signal i L2 The valley value of the inductor current of the second phase switching circuit is controlled by the valley value of the inductor current. When the second inductor current sampling signal i L2 The valley value reaches the second lower limit voltage Vbot2, the second phase switch signal PWM2 jumps from invalid to valid, and the main switch tube of the second phase switch circuit is turned on; the second lower limit voltage Vbot2 is reset to the second starting value before the second phase clock signal is effective, and starts to rise when the second phase clock signal is effective. It should be noted that the first lower limit voltage Vbot1 and / or the second lower limit voltage Vbot2 can rise linearly or nonlinearly; nonlinearity includes various forms such as piecewise linear, parabolic, exponential, etc. In addition, the "valid" and "invalid" mentioned in this application can correspond to a high level for valid and a low level for invalid; in another embodiment, it can also correspond to a low level for valid and a high level for invalid.

[0075] exist Figure 2 and Figure 3In the examples, the second time difference t2 between the second-phase switch signal PWM2 (solid line) and the second-phase clock signal CLK2 before the phase-matching is greater than the first time difference t1 between the first-phase switch signal PWM1 and the first-phase clock signal CLK1 is used as an example. The phase-matching method of the two-phase switch circuit of the present invention is: a first signal representing the first time difference t1 is obtained according to the first-phase clock signal CLK1 and the first-phase switch signal PWM1, a second signal representing the second time difference t2 is obtained according to the second-phase clock signal CLK2 and the second-phase switch signal PWM2 (solid line), and the second adjustment signal is obtained according to the first signal and the second signal; wherein the first time difference t1 is the time from the first-phase clock signal CLK1 representing the validity to the first-phase switch signal PWM1 jumping to the validity; the second time difference t2 is the time from the second-phase clock signal CLK2 representing the validity to the second-phase switch signal PWM2 (solid line) jumping to the validity. The second adjustment signal is used to adjust the second lower limit voltage Vbot2, thereby adjusting the switching signal of the next switching cycle of the second phase, so that the second time difference t2″ between the second phase switching signal PWM2 (dashed line) after homogenization and the second phase clock signal is equal to the first time difference t1, so that the phase difference between the second phase switching signal PWM2 (dashed line) and the first phase switching signal PWM1 is equal; wherein, the second time difference t2″ after homogenization is the period from the time when the second phase clock signal CLK2 becomes valid to the time when the second phase switching signal PWM2 (dashed line) after homogenization jumps to valid.

[0076] like Figure 2 As shown, in a homogeneous mode of the present invention, the second adjustment signal is used to adjust the second starting value, that is, to adjust the voltage when the second lower limit voltage Vbot2 starts to rise, so as to adjust the second lower limit voltage Vbot2. The second time difference t2 before homogeneous phase is greater than the first time difference t1. In this case, the second adjustment signal is used to increase the second starting value, so that the waveform of the second lower limit voltage Vbot2 moves up, and the second inductor current sampling signal i L2 The valley value of the second lower limit voltage Vbot2 will reach the second lower limit voltage Vbot2 earlier, and the second phase switching signal PWM2 can be adjusted from the solid line position to the dotted line position, and finally the second time difference t2″ after the phase is equalized is equal to the first time difference t1. It can be understood that in another embodiment, if the second time difference t2 is less than the first time difference t1, the second adjustment signal can be used to reduce the second starting value, so that the waveform of the second lower limit voltage Vbot2 moves downward, and the second inductor current sampling signal i L2 The valley value of will reach the second lower limit voltage Vbot2 later, so that the second time difference t2″ after averaging can be equal to the first time difference t1.

[0077] like Figure 3 As shown, in another homogeneous mode of the present invention, the second lower limit voltage Vbot2 is adjusted by adjusting the slope of the second lower limit voltage Vbot2 when it rises using the second adjustment signal. The second time difference t2 before homogeneous phase is greater than the first time difference t1. In this case, the second adjustment signal is used to increase the slope of the mth lower limit voltage when it rises, and the second inductor current sampling signal i L2 The valley value of the mth lower limit voltage Vbot2 will reach the second lower limit voltage Vbot2 earlier, and the second phase switching signal PWM2 can be adjusted from the solid line position to the dotted line position, and finally the second time difference t2″ after the phase is equalized is equal to the first time difference t1. It can be understood that in another embodiment, if the second time difference t2 is less than the first time difference t1, the second adjustment signal is used to reduce the slope of the mth lower limit voltage when it rises, and the second inductor current sampling signal i L2 The valley value of will reach the second lower limit voltage Vbot2 later, so that the second time difference t2″ after averaging can be equal to the first time difference t1.

[0078] refer to Figure 4 The multi-phase switching circuit of the embodiment of the present invention includes an n-phase switching circuit 40, a uniform phase control circuit 10, a first switching signal generating circuit 20 and an mth switching signal generating circuit 21, and n-phase clock signals CLK1, CLK2...CLKn with equal frequencies and equal phase differences are respectively used as clock signals of the n-phase switching circuit, wherein n is an integer greater than 1, and m is an integer from 2 to n. The uniform phase control circuit 10 includes an n-phase logic circuit 101 and an n-1-phase adjustment circuit 102. The first logic circuit obtains the first signal S1 representing the first time difference t1 according to the first-phase clock signal CLK1 and the first-phase switching signal PWM1; the m-th logic circuit obtains the m-th signal Sm representing the m-th time difference tm according to the m-th phase clock signal CLKm and the m-th phase switching signal PWMm; the first time difference t1 is the time from the first-phase clock signal CLK1 representing the validity to the first-phase switching signal PWM1 jumping to the validity; the m-th time difference tm is the time from the m-phase clock signal CLKm representing the validity to the m-phase switching signal PWMm jumping to the validity. The m-th adjustment circuit 102 receives the first signal S1 and the m-th signal Sm to output the m-th adjustment signal V Rm The first switching signal generating circuit 20 outputs the first phase switching signal PWM1 according to the first signal S1. The mth switching signal generating circuit 21 receives the mth signal Sm and the mth adjustment signal V Rm To output the m-th phase switching signal PWMm, according to the m-th adjustment signal V RmThe switch signal of the next switch cycle of the m-th phase is adjusted so that the time difference between the m-th phase switch signal PWMm and the m-th phase clock signal CLKm is equal to the time difference between the first phase switch signal PWM1 and the first phase clock signal CLK1, thereby making the phase difference of the n-phase switch signals equal. For example, the multi-phase switch circuit of the embodiment of the present invention also includes an n-phase drive circuit 30, and the n-phase drive circuit 30 receives the n-phase switch signals PWM1, PWM2...PWMn to drive the main switch tube and the synchronous rectifier tube of the n-phase switch circuit 40. If there is no synchronous rectifier tube in the switch circuit 40, but a freewheeling diode, only the main switch tube needs to be driven.

[0079] It should be noted that the 1st phase or the mth phase in the present application is for the convenience of description and does not limit the specific position of the phase. The 1st phase can be one of the n phases, and the mth phase can be another phase among the n phases. The 1st phase serves as the basis for adjusting the other phases.

[0080] Figure 5 A circuit structure diagram of an embodiment of the m-th regulating circuit 102 is shown, including an m-th voltage regulating circuit 1021 and an m-th filter 1022. In one embodiment, when the first-phase clock signal is valid, the first signal jumps to valid; when the first-phase switch signal jumps to valid, the first signal jumps to invalid; when the m-th-phase clock signal is valid, the m-th signal jumps to valid; when the m-th-phase switch signal jumps to valid, the m-th signal jumps to invalid. By way of example, the mth voltage regulation circuit includes a first current source U01, a second current source U02, a first switch K01, a second switch K02 and a first capacitor C01, wherein a first end of the first switch tube K01 is connected to the first current source U01, a second end is connected to the first end of the first capacitor C01, a control end receives the mth signal Sm, when the mth signal Sm is valid, the first switch tube K01 is turned on, and the first current source U01 charges the first capacitor C01; a first end of the second switch tube K02 is connected to the first end of the first capacitor C01, a second end is connected to the second current source U02, a control end receives the first signal S1, when the first signal S1 is valid, the second switch tube K02 is turned on, and the second current source U02 discharges the first capacitor C01; wherein the currents output by the first current source U01 and the second current source U02 are equal in magnitude; a second end of the first capacitor C01 is grounded, and a first end serves as an output end of the mth voltage regulation circuit 1021 to output the mth voltage regulation signal. The mth filter 1022 receives the mth voltage regulation signal and filters the mth voltage regulation signal to output the mth regulation signal V RmFor example, the mth filter 1022 includes a first filter resistor R01 and a second filter capacitor C02 connected in series, and the common end of the first filter resistor R01 and the second filter capacitor C02 is used as the output end of the mth adjustment circuit 102 to output the mth adjustment signal V Rm The other end of the first filter resistor R01 receives the mth voltage adjustment signal, and the other end of the second filter capacitor C02 is grounded.

[0081] When the mth time difference tm is greater than the first time difference t1, that is, the effective time of the mth signal Sm is greater than the effective time of the first signal S1, the charging time of the first capacitor C01 is greater than the discharging time, and the mth adjustment signal V Rm When the mth time difference is less than the first time difference, that is, the effective time of the mth signal Sm is less than the effective time of the first signal S1, the charging time of the first capacitor C01 is less than the discharging time, and the mth adjustment signal V Rm Reduce.

[0082] It can be understood that in another embodiment, if the first switch tube K01 is turned on when the mth signal Sm is valid, and the second switch tube K02 is turned on when the first signal S1 is valid, and only the positions of the first switch K01 and the second switch K02 are swapped; or the positions of the first switch K01 and the second switch K02 are kept unchanged, and only the second switch tube K02 is turned on when the mth signal Sm is valid, and the first switch tube K01 is turned on when the first signal S1 is valid, both can make the mth adjustment signal V Rm When the mth time difference tm is less than the first time difference t1, the mth adjustment signal V Rm Increase.

[0083] refer to Figure 6 The mth switch signal generating circuit 21 includes an mth lower limit voltage generating circuit 212, an mth upper comparator U03, an mth lower comparator U04 and a trigger 213. The mth lower limit voltage generating circuit 212 receives the mth signal Sm and the mth adjustment signal V Rm The mth upper comparator U03 compares the mth inductor current sampling signal i representing the inductor current of the mth phase switch circuit. Lm and the upper limit voltage Vtop, when the main switch tube of the m-th phase switch circuit is turned on, the m-th inductor current sampling signal i LmThe mth lower comparator U04 compares the mth inductor current sampling signal i Lm and the mth lower limit voltage Vbotm, when the main switch tube of the mth phase switch circuit is turned off, the mth inductor current sampling value i Lm When the output voltage of the mth upper comparator U03 is less than or equal to the mth lower limit voltage Vbotm, the output voltage of the mth lower comparator U04 is reversed. The trigger 213 receives the output voltages of the mth upper comparator U03 and the mth lower comparator U04 to output the mth phase switching signal PWMm; when the output voltage of the mth upper comparator U03 is reversed, the mth phase switching signal PWMm changes from valid to invalid, and the main switch tube of the mth phase switching circuit is turned off; when the output voltage of the mth lower comparator U04 is reversed, the mth phase switching signal PWMm changes from invalid to valid, and the main switch tube of the mth phase switching circuit is turned on.

[0084] Continue to refer Figure 6 The circuit structure and working principle of the first switch signal generating circuit 20 are basically similar to those of the mth switch signal generating circuit 21, and will not be described in detail here. The difference is that the first lower limit voltage generating circuit 202 in the first switch signal generating circuit 20 receives the first signal S1 to output the first lower limit voltage Vbot1. In one embodiment, the first switch signal generating circuit 20 also includes an upper limit voltage generating circuit 201 for outputting the upper limit voltage Vtop.

[0085] refer to Figure 7 , is a schematic diagram of the circuit structure of the mth lower limit voltage generating circuit and the first lower limit voltage generating circuit according to an embodiment of the present invention. In one embodiment, when the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm When the mth time difference is less than the first time difference, the mth adjustment signal V Rm For example, the mth lower limit voltage generating circuit 212 includes a first adder 2121 and an mth slope generating circuit 2122. The first adder 2121 receives the difference Vtop-ΔV between the upper limit voltage and a bias voltage at a first input terminal, and receives the mth adjustment signal V Rm , the difference between the upper limit voltage and a bias voltage Vtop-ΔV and the mth adjustment signal V Rm Perform addition operation to output the mth starting value Vsm=Vtop-ΔV+V RmThe m-th slope generating circuit 2122 receives the m-th starting value Vsm to output the m-th lower limit voltage Vbotm, and the m-th lower limit voltage Vbotm is reset to the m-th starting value Vsm before the m-th phase clock signal CLKm is effective, and starts to rise when the m-th phase clock signal CLKm is effective. By way of example, the m-th slope generating circuit 2122 includes a third current source U05, a third capacitor C03, and a third switch K03. The first end of the third capacitor C03 is connected to the third current source U05, and the second end receives the m-th starting value Vsm. The first end of the third capacitor C03 serves as the output end of the m-th lower limit voltage generating circuit 212 to output the m-th lower limit voltage Vbotm. The third switch K03 is connected in parallel with the third capacitor C03, and the control end of the third switch K03 receives the mth signal Sm. When the mth signal Sm jumps to invalid, the third switch K03 starts to turn on, and the mth lower limit voltage Vbotm is reset to the mth starting value Vsm. When the mth signal Sm is invalid, the third switch K03 is turned on, and the mth lower limit voltage Vbotm is equal to the mth starting value Vsm; when the mth signal Sm jumps to valid, the third switch K03 starts to turn off, the third current source U05 starts to charge the third capacitor C03, and the mth lower limit voltage Vbotm starts to rise. When the mth signal Sm is valid, the third switch K03 is turned off, the third current source U05 continues to charge the third capacitor C03, and the mth lower limit voltage Vbotm continues to rise.

[0086] Continue to refer Figure 7 The circuit structure and working principle of the circuit structure diagram of the first lower limit voltage generating circuit 202 are basically similar to those of the mth lower limit voltage generating circuit 212, and are not repeated here. The difference is that the first lower limit voltage generating circuit 202 does not include the first adder, and the second end of the third capacitor C03′ receives the difference Vtop-ΔV between the upper limit voltage and a bias voltage, and the difference Vtop-ΔV between the upper limit voltage and a bias voltage is used as the first starting value Vs1 of the circuit of the first lower limit voltage generating circuit 202.

[0087] When the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm increases, the mth starting value Vsm also increases accordingly, and Figure 2 Similar to Vbot2 shown in, Figure 7 The waveform of the mth lower limit voltage Vbotm shown in FIG. 1 moves upward, and the mth inductor current sampling signal i LmThe valley value of the mth lower limit voltage Vbotm will reach the mth lower limit voltage Vbotm earlier, and finally the mth time difference tm″ between the mth phase switch signal PWMm and the mth phase clock signal CLKm after balancing can be equal to the first time difference t1 between the first phase switch signal PWM1 and the first phase clock signal CLK1; when the mth time difference tm is less than the first time difference t1, the mth adjustment signal V Rm The mth starting value Vsm also decreases accordingly, the mth lower limit voltage Vbotm waveform moves downward, and the mth inductor current sampling signal i Lm The valley value of will reach the mth lower limit voltage Vbotm later, and finally the mth time difference tm″ between the mth phase switching signal PWMm and the mth phase clock signal CLKm after balancing can be equal to the first time difference t1 between the first phase switching signal PWM1 and the first phase clock signal CLK1.

[0088] It can be understood that, in another embodiment, if the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm When the mth time difference tm is less than the first time difference t1, the mth adjustment signal V Rm Increase. Figure 7 The first adder 2121 in the mth lower limit voltage generating circuit 212 can be replaced by a first subtractor, which performs a calculation on the difference Vtop-ΔV between the upper limit voltage and a bias voltage and the mth adjustment signal V Rm Subtraction operation is performed to output the mth starting value Vsm=Vtop-ΔV-V Rm That is, the mth time difference tm″ between the mth phase switching signal PWMm and the mth phase clock signal CLKm after balancing and the first time difference t1 between the first phase switching signal PWM1 and the first phase clock signal CLK1 are equal.

[0089] In this embodiment, the mth adjustment signal V Rm The mth starting value Vsm is adjusted, that is, the voltage value when the mth lower limit voltage Vbotm starts to rise is adjusted to adjust the mth lower limit voltage Vbotm, so as to adjust the switching signal of the next switching cycle of the mth phase, so that the time difference between the mth phase switching signal and the mth phase clock signal is equal to the time difference between the 1st phase switching signal and the 1st phase clock signal, thereby making the phase difference of the n-phase switching signals equal, the system more balanced, and the output ripple smaller.

[0090] refer to Figure 8, is a circuit structure diagram of an mth lower limit voltage generating circuit and a first lower limit voltage generating circuit according to another embodiment of the present invention. In one embodiment, when the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm When the mth time difference is less than the first time difference, the mth adjustment signal V Rm For example, the mth lower limit voltage generating circuit 212 includes a second adder 2123 and an mth slope generating circuit 2124. The first input terminal of the second adder 2123 receives the first voltage V1, and the second input terminal receives the mth adjustment signal V Rm , and the first voltage V1 and the mth adjustment signal V Rm Perform addition operation to output the mth voltage Vm=V1+V Rm. The mth slope generating circuit 2124 receives the mth voltage Vm to output the mth lower limit voltage Vbotm, the mth lower limit voltage Vbotm is reset to the mth starting value Vsm before the mth phase clock signal CLKm is effective, and starts to rise when the mth phase clock signal CLKm is effective. By way of example, the mth slope generating circuit 2124 includes a voltage-to-current circuit 21241, a fourth capacitor C04, and a fourth switch K04. The voltage-to-current circuit 21241 receives the mth voltage Vm to output the mth current im that is positively correlated with the mth voltage Vm. The first end of the fourth capacitor C04 receives the mth current im, and the second end receives the difference Vtop-ΔV between the upper limit voltage and a bias voltage, the difference Vtop-ΔV between the upper limit voltage and a bias voltage being used as the mth starting value Vsm, and the first end of the fourth capacitor C04 is used as the output end of the mth lower limit voltage generating circuit 212 to output the mth lower limit voltage Vbotm. The fourth switch K04 is connected in parallel with the fourth capacitor C04, and the control end of the fourth switch K04 receives the mth signal Sm. When the mth signal Sm jumps to invalid, the fourth switch K04 starts to conduct, and the mth lower limit voltage Vbotm is reset to the mth starting value Vsm (Vsm=Vtop-ΔV). When the mth signal Sm is invalid, the fourth switch K04 is turned on, and the mth lower limit voltage Vbotm is equal to the mth starting value Vsm. When the mth signal Sm jumps to valid, the fourth switch K04 starts to turn off, the mth current im starts to charge the fourth capacitor C04, and the mth lower limit voltage Vbotm starts to rise. When the mth signal Sm is valid, the fourth switch K04 is turned off, the mth current im continues to charge the fourth capacitor C04, and the mth lower limit voltage Vbotm continues to rise. In one embodiment, the voltage-to-current circuit 21241 includes a fourth controlled current source U06, the first input terminal of the fourth controlled current source U06 receives the mth voltage Vm, the first input terminal is grounded, and the output terminal outputs the mth current im, and the mth current im is proportional to the mth voltage Vm.

[0091] Continue to refer Figure 8 The circuit structure and working principle of the circuit structure diagram of the first lower limit voltage generating circuit 202 are basically similar to those of the mth lower limit voltage generating circuit 212, and will not be repeated here. The difference is that the first lower limit voltage generating circuit 202 does not include a second adder, and the first input terminal of the fourth controlled current source U06′ receives the first voltage V1.

[0092] When the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm increases, the mth voltage Vm will increase accordingly, and the mth current im will also increase accordingly, Figure 3 Similar to Vbot2 shown in, Figure 8 The slope of the mth lower limit voltage Vbotm shown in FIG. 1 increases when it rises, and the mth inductor current sampling signal i Lm The valley value of the mth lower limit voltage Vbotm will reach the mth lower limit voltage Vbotm earlier, and finally the mth time difference tm″ between the mth phase switch signal PWMm and the mth phase clock signal CLKm after averaging can be equal to the first time difference t1 between the first phase switch signal PWM1 and the first phase clock signal CLK1. When the mth time difference tm is less than the first time difference t1, the mth adjustment signal V Rm The mth voltage Vm will decrease accordingly, the mth current im will also decrease accordingly, the slope of the mth lower limit voltage Vbotm when it rises decreases, and the mth inductor current sampling signal i Lm The valley value of will reach the mth lower limit voltage Vbotm later, and finally the mth time difference tm″ between the mth phase switching signal PWMm and the mth phase clock signal CLKm after balancing can be equal to the first time difference t1 between the first phase switching signal PWM1 and the first phase clock signal CLK1.

[0093] It can be understood that, in another embodiment, if the mth time difference tm is greater than the first time difference t1, the mth adjustment signal V Rm When the mth time difference tm is less than the first time difference t1, the mth adjustment signal V Rm In this case, just increase Figure 8 The second adder 2123 in the mth lower limit voltage generating circuit 212 can be replaced by a second subtractor, which subtracts the difference Vtop-ΔV between the upper limit voltage and a bias voltage and the mth adjustment signal V Rm Subtraction operation is performed to output the mth starting value Vsm=Vtop-ΔV-V Rm That is, the mth time difference tm″ between the mth phase switching signal PWMm and the mth phase clock signal CLKm after balancing and the first time difference t1 between the first phase switching signal PWM1 and the first phase clock signal CLK1 are equal.

[0094] In this embodiment, the mth adjustment signal V Rm The mth lower limit voltage Vbotm is adjusted by adjusting the slope of the mth lower limit voltage Vbotm when it rises, so as to adjust the switching signal of the next switching cycle of the mth phase, so that the time difference between the mth phase switching signal and the mth phase clock signal is equal to the time difference between the 1st phase switching signal and the 1st phase clock signal, thereby making the phase difference of the n-phase switching signals equal, the system more balanced, and the output ripple smaller.

[0095] The multi-phase switching circuit of the embodiment of the present invention further includes an upper limit voltage generating circuit, which is used to output the upper limit voltage Vtop according to the output feedback signal FB of the multi-phase switching circuit, and the upper limit voltage Vtop controls the peak value of the inductor current of the n-phase switching circuit. Fig. 9 The upper limit voltage generating circuit 201 includes an error amplifier U07 and a compensation circuit 2011. The error amplifier U07 receives the feedback voltage FB and the reference voltage Vref for operational amplification, and the output signal of the error amplifier U07 is processed by the compensation circuit 2011 to obtain the upper limit voltage Vtop.

[0096] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A homogeneous phase method for a multi-phase switching circuit, wherein the multi-phase switching circuit comprises an n-phase switching circuit, characterized in that: include: n-phase clock signals with equal frequency and equal phase difference are respectively used as clock signals of the n-phase switching circuits; Obtaining an mth adjustment signal according to the first phase clock signal, the first phase switch signal, the mth phase clock signal and the mth phase switch signal; Using the mth adjustment signal to adjust the switch signal of the next switch cycle of the mth phase, so that the time difference between the mth phase switch signal and the mth phase clock signal is equal to the time difference between the first phase switch signal and the first phase clock signal, thereby making the phase difference of the n-phase switch signals equal; Herein, n is an integer greater than 1, and m is an integer from 2 to n.

2. The homogeneous method according to claim 1, characterized in that The method for obtaining the mth adjustment signal according to the first phase clock signal, the first phase switch signal, the mth phase clock signal and the mth phase switch signal further comprises: Obtaining a first signal representing a first time difference according to the first phase clock signal and the first phase switch signal, obtaining an mth signal representing an mth time difference according to the mth phase clock signal and the mth phase switch signal, and obtaining the mth adjustment signal according to the first signal and the mth signal; Among them, the first time difference is the period from when the first phase clock signal is effective to when the first phase switch signal jumps to effective; the mth time difference is the period from when the mth phase clock signal is effective to when the mth phase switch signal jumps to effective.

3. The homogeneous method according to claim 2, characterized in that When the first phase clock signal indicates that it is valid, the first signal jumps to be valid; when the first phase switch signal jumps to be valid, the first signal jumps to be invalid; When the m-th phase clock signal indicates validity, the m-th signal jumps to validity; when the m-th phase switch signal jumps to validity, the m-th signal jumps to invalidity.

4. The homogeneous method according to claim 3, characterized in that The method for obtaining the mth adjustment signal according to the first signal and the mth signal further comprises: When the mth signal is valid, charging the first capacitor using the first current source; When the first signal is valid, using a second current source to discharge the first capacitor; Filtering the voltage of the first capacitor by using a filter to obtain the mth adjustment signal; The currents output by the first current source and the second current source are equal in magnitude.

5. The homogeneous method according to claim 2, characterized in that The mth lower limit voltage controls the valley value of the inductor current of the mth phase switching circuit. When the valley value of the mth inductor current sampling signal representing the inductor current of the mth phase switching circuit reaches the mth lower limit voltage, the mth phase switching signal jumps from invalid to valid, and the main switch tube of the mth phase switching circuit is turned on; the mth lower limit voltage is reset to the mth starting value before the mth phase clock signal represents validity, and starts to rise when the mth phase clock signal represents validity.

6. The homogeneous method according to claim 5, characterized in that The mth starting value is adjusted by utilizing the mth adjustment signal to adjust the mth lower limit voltage, thereby adjusting the switching signal of the next switching cycle of the mth phase.

7. The homogeneous method according to claim 5, characterized in that The mth regulating signal is used to adjust the slope of the mth lower limit voltage when it rises, so as to adjust the mth lower limit voltage, thereby adjusting the switching signal of the next switching cycle of the mth phase.

8. The homogeneous method according to claim 6, characterized in that The homogeneous method further comprises: Obtaining an upper limit voltage according to an output feedback signal of the multi-phase switch circuit to control the peak value of the inductor current of the n-phase switch circuit; The mth starting value is equal to the sum of the difference between the upper limit voltage and a bias voltage and the mth adjustment signal.

9. The homogeneous method according to claim 7, characterized in that The homogeneous method further comprises: Obtaining an upper limit voltage according to an output feedback signal of the multi-phase switch circuit to control the peak value of the inductor current of the n-phase switch circuit; The mth starting value is equal to a difference between the upper limit voltage and a bias voltage.

10. A multi-phase switching circuit, comprising an n-phase switching circuit, characterized in that: n-phase clock signals with equal frequency and equal phase difference are used as clock signals of the n-phase switching circuit, and the multi-phase switching circuit comprises: a uniform phase control circuit, receiving the n-phase clock signal and the n-phase switch signal to output an n-1-phase adjustment signal, wherein an m-th adjustment signal is output according to the 1st phase clock signal, the 1st phase switch signal, the m-th phase clock signal and the m-th phase switch signal; an m-th switching signal generating circuit, configured to output an m-th phase switching signal, and to adjust the switching signal of the m-th phase in the next switching cycle according to the m-th adjustment signal, so that the time difference between the m-th phase switching signal and the m-th phase clock signal is equal to the time difference between the first phase switching signal and the first phase clock signal, thereby making the phase difference of the n-phase switching signals equal; Herein, n is an integer greater than 1, and m is an integer from 2 to n.

11. The multi-phase switching circuit according to claim 10, characterized in that: The homogeneous control circuit includes a first logic circuit and an mth logic circuit. The first logic circuit obtains a first signal representing a first time difference according to the first phase clock signal and the first phase switch signal; the mth logic circuit obtains an mth signal representing an mth time difference according to the mth phase clock signal and the mth phase switch signal; Among them, the first time difference is the period from when the first phase clock signal is effective to when the first phase switch signal jumps to effective; the mth time difference is the period from when the mth phase clock signal is effective to when the mth phase switch signal jumps to effective.

12. The multi-phase switching circuit according to claim 11, characterized in that: The homogeneous control circuit comprises: The mth regulating circuit receives the first signal and the mth signal to output the mth regulating signal, wherein when the mth time difference is greater than the first time difference, the mth regulating signal increases; when the mth time difference is less than the first time difference, the mth regulating signal decreases.

13. The multi-phase switching circuit according to claim 12, characterized in that: When the first phase clock signal indicates that it is valid, the first signal jumps to be valid; when the first phase switch signal jumps to be valid, the first signal jumps to be invalid; When the m-th phase clock signal indicates validity, the m-th signal jumps to validity; when the m-th phase switch signal jumps to validity, the m-th signal jumps to invalidity.

14. The multi-phase switching circuit according to claim 13, characterized in that: The mth regulating circuit comprises an mth voltage regulating circuit and an mth filter, The mth voltage regulation circuit comprises a first current source, a second current source, a first switch, a second switch and a first capacitor, wherein a first end of the first switch tube is connected to the first current source, a second end is connected to a first end of the first capacitor, a control end receives the mth signal, when the mth signal is valid, the first switch tube is turned on, and the first current source charges the first capacitor; a first end of the second switch tube is connected to a first end of the first capacitor, and a second end is connected to the second current source, a control end receives the first signal, when the first signal is valid, the second switch tube is turned on, and the second current source discharges the first capacitor; a second end of the first capacitor is grounded, and a first end is used as an output end of the mth voltage regulation circuit to output the mth voltage regulation signal; The mth filter receives the mth voltage regulation signal, and filters the mth voltage regulation signal to output the mth regulation signal; The currents output by the first current source and the second current source are equal in magnitude.

15. The multi-phase switching circuit according to claim 13, characterized in that: The mth switch signal generating circuit comprises: The mth lower limit voltage generating circuit is used to output the mth lower limit voltage, the mth lower limit voltage controls the valley value of the inductor current of the mth phase switching circuit, the mth lower limit voltage is reset to the mth starting value before the mth phase clock signal is valid, and starts to rise when the mth phase clock signal is valid.

16. The multi-phase switching circuit according to claim 15, characterized in that: The mth lower limit voltage generating circuit receives the mth signal and the mth adjustment signal to output the mth lower limit voltage. When the mth signal jumps to invalid, the mth lower limit voltage is reset to the mth starting value; when the mth signal jumps to valid, the mth lower limit voltage starts to rise.

17. The multi-phase switching circuit according to claim 16, characterized in that: The mth lower limit voltage generating circuit comprises: A first adder, having a first input terminal receiving a difference between an upper limit voltage and a bias voltage, a second input terminal receiving the mth adjustment signal, and performing an addition operation on the difference between the upper limit voltage and a bias voltage and the mth adjustment signal to output the mth starting value; The mth slope generating circuit receives the mth starting value and the mth signal to output the mth lower limit voltage.

18. The multi-phase switching circuit according to claim 16, characterized in that: The mth lower limit voltage generating circuit comprises: A second adder, a first input terminal receiving a first voltage, a second input terminal receiving the mth adjustment signal, performing an addition operation on the first voltage and the mth adjustment signal to output an mth voltage; The mth slope generating circuit receives the mth voltage and the mth signal to output the mth lower limit voltage, the slope of the mth lower limit voltage when rising is related to the mth voltage, and the mth starting value is equal to the difference between the upper limit voltage and a bias voltage.

19. The multi-phase switching circuit according to claim 17 or 18, characterized in that: The multi-phase switching circuit further includes: The upper limit voltage generating circuit outputs the upper limit voltage according to the output feedback signal of the multi-phase switching circuit to control the peak value of the inductor current of the n-phase switching circuit.

20. The multi-phase switching circuit according to claim 19, characterized in that: The multi-phase switching circuit further includes a first switching signal generating circuit, which is used to output the first phase switching signal, and the first switching signal generating circuit includes: The first lower limit voltage generating circuit receives the first signal to output the first lower limit voltage to control the valley value of the inductor current of the first phase switching circuit. The first lower limit voltage is reset to the first starting value before the first phase clock signal is valid, and starts to rise when the first phase clock signal is valid.

21. The multi-phase switching circuit according to claim 19, characterized in that: The mth switch signal generating circuit further includes: An mth upper comparator compares an mth inductor current sampling signal representing the inductor current of the mth phase switch circuit with the upper limit voltage, and when the main switch tube of the mth phase switch circuit is turned on, the mth inductor current sampling signal is greater than or equal to the upper limit voltage, and the output voltage of the mth upper comparator is reversed; an mth lower comparator, comparing the mth inductor current sampling signal with the mth lower limit voltage, and when the main switch tube of the mth phase switch circuit is turned off, the mth inductor current sampling value is less than or equal to the mth lower limit voltage, and the output voltage of the mth lower comparator is reversed; A trigger receives the output voltages of the mth upper comparator and the mth lower comparator to output the mth phase switching signal, wherein the mth phase switching signal controls the on and off of the main switch tube of the mth phase switching circuit.

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